1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/boards.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/pci-host/grackle.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 52 #define MAX_IDE_BUS 2 53 #define CFG_ADDR 0xf0000510 54 #define TBFREQ 16600000UL 55 #define CLOCKFREQ 266000000UL 56 #define BUSFREQ 66000000UL 57 58 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 59 60 #define PROM_FILENAME "openbios-ppc" 61 #define PROM_BASE 0xffc00000 62 #define PROM_SIZE (4 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x01000000 65 #define KERNEL_GAP 0x00100000 66 67 #define GRACKLE_BASE 0xfec00000 68 69 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 70 Error **errp) 71 { 72 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 73 } 74 75 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 76 { 77 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 78 } 79 80 static void ppc_heathrow_reset(void *opaque) 81 { 82 PowerPCCPU *cpu = opaque; 83 84 cpu_reset(CPU(cpu)); 85 } 86 87 static void ppc_heathrow_init(MachineState *machine) 88 { 89 const char *bios_name = machine->firmware ?: PROM_FILENAME; 90 PowerPCCPU *cpu = NULL; 91 CPUPPCState *env = NULL; 92 char *filename; 93 int i, bios_size = -1; 94 MemoryRegion *bios = g_new(MemoryRegion, 1); 95 uint64_t bios_addr; 96 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 97 int32_t kernel_size = 0, initrd_size = 0; 98 PCIBus *pci_bus; 99 Object *macio; 100 MACIOIDEState *macio_ide; 101 SysBusDevice *s; 102 DeviceState *dev, *pic_dev, *grackle_dev; 103 BusState *adb_bus; 104 uint16_t ppc_boot_device; 105 DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 106 void *fw_cfg; 107 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 108 109 /* init CPUs */ 110 for (i = 0; i < machine->smp.cpus; i++) { 111 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 112 env = &cpu->env; 113 114 /* Set time-base frequency to 16.6 Mhz */ 115 cpu_ppc_tb_init(env, TBFREQ); 116 qemu_register_reset(ppc_heathrow_reset, cpu); 117 } 118 119 /* allocate RAM */ 120 if (machine->ram_size > 2047 * MiB) { 121 error_report("Too much memory for this machine: %" PRId64 " MB, " 122 "maximum 2047 MB", machine->ram_size / MiB); 123 exit(1); 124 } 125 126 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 127 128 /* allocate and load firmware ROM */ 129 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 130 &error_fatal); 131 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 132 133 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 134 if (filename) { 135 /* Load OpenBIOS (ELF) */ 136 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 137 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 138 /* Unfortunately, load_elf sign-extends reading elf32 */ 139 bios_addr = (uint32_t)bios_addr; 140 141 if (bios_size <= 0) { 142 /* or if could not load ELF try loading a binary ROM image */ 143 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 144 bios_addr = PROM_BASE; 145 } 146 g_free(filename); 147 } 148 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 149 error_report("could not load PowerPC bios '%s'", bios_name); 150 exit(1); 151 } 152 153 if (machine->kernel_filename) { 154 int bswap_needed = 0; 155 156 #ifdef BSWAP_NEEDED 157 bswap_needed = 1; 158 #endif 159 kernel_base = KERNEL_LOAD_ADDR; 160 kernel_size = load_elf(machine->kernel_filename, NULL, 161 translate_kernel_address, NULL, NULL, NULL, 162 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 163 if (kernel_size < 0) { 164 kernel_size = load_aout(machine->kernel_filename, kernel_base, 165 machine->ram_size - kernel_base, 166 bswap_needed, TARGET_PAGE_SIZE); 167 } 168 if (kernel_size < 0) { 169 kernel_size = load_image_targphys(machine->kernel_filename, 170 kernel_base, 171 machine->ram_size - kernel_base); 172 } 173 if (kernel_size < 0) { 174 error_report("could not load kernel '%s'", 175 machine->kernel_filename); 176 exit(1); 177 } 178 /* load initrd */ 179 if (machine->initrd_filename) { 180 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 181 KERNEL_GAP); 182 initrd_size = load_image_targphys(machine->initrd_filename, 183 initrd_base, 184 machine->ram_size - initrd_base); 185 if (initrd_size < 0) { 186 error_report("could not load initial ram disk '%s'", 187 machine->initrd_filename); 188 exit(1); 189 } 190 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 191 } else { 192 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 193 } 194 ppc_boot_device = 'm'; 195 } else { 196 ppc_boot_device = '\0'; 197 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 198 /* 199 * TOFIX: for now, the second IDE channel is not properly 200 * used by OHW. The Mac floppy disk are not emulated. 201 * For now, OHW cannot boot from the network. 202 */ 203 #if 0 204 if (machine->boot_config.order[i] >= 'a' && 205 machine->boot_config.order[i] <= 'f') { 206 ppc_boot_device = machine->boot_config.order[i]; 207 break; 208 } 209 #else 210 if (machine->boot_config.order[i] >= 'c' && 211 machine->boot_config.order[i] <= 'd') { 212 ppc_boot_device = machine->boot_config.order[i]; 213 break; 214 } 215 #endif 216 } 217 if (ppc_boot_device == '\0') { 218 error_report("No valid boot device for G3 Beige machine"); 219 exit(1); 220 } 221 } 222 223 /* Grackle PCI host bridge */ 224 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 225 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 226 s = SYS_BUS_DEVICE(grackle_dev); 227 sysbus_realize_and_unref(s, &error_fatal); 228 229 sysbus_mmio_map(s, 0, GRACKLE_BASE); 230 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 231 /* PCI hole */ 232 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 233 sysbus_mmio_get_region(s, 2)); 234 /* Register 2 MB of ISA IO space */ 235 memory_region_add_subregion(get_system_memory(), 0xfe000000, 236 sysbus_mmio_get_region(s, 3)); 237 238 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 239 240 /* MacIO */ 241 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 242 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 243 244 dev = DEVICE(object_resolve_path_component(macio, "escc")); 245 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 246 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 247 248 dinfo = drive_get(IF_MTD, 0, 0); 249 if (dinfo) { 250 dev = DEVICE(object_resolve_path_component(macio, "nvram")); 251 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 252 } 253 254 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 255 256 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 257 for (i = 0; i < 4; i++) { 258 qdev_connect_gpio_out(grackle_dev, i, 259 qdev_get_gpio_in(pic_dev, 0x15 + i)); 260 } 261 262 /* Connect the heathrow PIC outputs to the 6xx bus */ 263 for (i = 0; i < machine->smp.cpus; i++) { 264 switch (PPC_INPUT(env)) { 265 case PPC_FLAGS_INPUT_6xx: 266 /* XXX: we register only 1 output pin for heathrow PIC */ 267 qdev_connect_gpio_out(pic_dev, 0, 268 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 269 break; 270 default: 271 error_report("Bus model not supported on OldWorld Mac machine"); 272 exit(1); 273 } 274 } 275 276 pci_vga_init(pci_bus); 277 278 for (i = 0; i < nb_nics; i++) { 279 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 280 } 281 282 /* MacIO IDE */ 283 ide_drive_get(hd, ARRAY_SIZE(hd)); 284 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 285 macio_ide_init_drives(macio_ide, hd); 286 287 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 288 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 289 290 /* MacIO CUDA/ADB */ 291 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 292 adb_bus = qdev_get_child_bus(dev, "adb.0"); 293 dev = qdev_new(TYPE_ADB_KEYBOARD); 294 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 295 dev = qdev_new(TYPE_ADB_MOUSE); 296 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 297 298 if (machine_usb(machine)) { 299 pci_create_simple(pci_bus, -1, "pci-ohci"); 300 } 301 302 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 303 graphic_depth = 15; 304 } 305 306 /* No PCI init: the BIOS will do it */ 307 308 dev = qdev_new(TYPE_FW_CFG_MEM); 309 fw_cfg = FW_CFG(dev); 310 qdev_prop_set_uint32(dev, "data_width", 1); 311 qdev_prop_set_bit(dev, "dma_enabled", false); 312 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); 313 s = SYS_BUS_DEVICE(dev); 314 sysbus_realize_and_unref(s, &error_fatal); 315 sysbus_mmio_map(s, 0, CFG_ADDR); 316 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 317 318 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 319 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 320 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 321 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 322 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 323 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 324 if (machine->kernel_cmdline) { 325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 326 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 327 machine->kernel_cmdline); 328 } else { 329 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 330 } 331 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 332 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 333 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 334 335 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 336 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 337 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 338 339 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 340 if (kvm_enabled()) { 341 uint8_t *hypercall; 342 343 hypercall = g_malloc(16); 344 kvmppc_get_hypercall(env, hypercall, 16); 345 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 346 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 347 } 348 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 349 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 351 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 352 353 /* MacOS NDRV VGA driver */ 354 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 355 if (filename) { 356 gchar *ndrv_file; 357 gsize ndrv_size; 358 359 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 360 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 361 } 362 g_free(filename); 363 } 364 365 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 366 } 367 368 /* 369 * Implementation of an interface to adjust firmware path 370 * for the bootindex property handling. 371 */ 372 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 373 DeviceState *dev) 374 { 375 PCIDevice *pci; 376 MACIOIDEState *macio_ide; 377 378 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 379 pci = PCI_DEVICE(dev); 380 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 381 } 382 383 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 384 macio_ide = MACIO_IDE(dev); 385 return g_strdup_printf("ata-3@%x", macio_ide->addr); 386 } 387 388 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 389 return g_strdup("disk"); 390 } 391 392 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 393 return g_strdup("cdrom"); 394 } 395 396 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 397 return g_strdup("disk"); 398 } 399 400 return NULL; 401 } 402 403 static int heathrow_kvm_type(MachineState *machine, const char *arg) 404 { 405 /* Always force PR KVM */ 406 return 2; 407 } 408 409 static void heathrow_class_init(ObjectClass *oc, void *data) 410 { 411 MachineClass *mc = MACHINE_CLASS(oc); 412 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 413 414 mc->desc = "Heathrow based PowerMAC"; 415 mc->init = ppc_heathrow_init; 416 mc->block_default_type = IF_IDE; 417 /* SMP is not supported currently */ 418 mc->max_cpus = 1; 419 #ifndef TARGET_PPC64 420 mc->is_default = true; 421 #endif 422 /* TOFIX "cad" when Mac floppy is implemented */ 423 mc->default_boot_order = "cd"; 424 mc->kvm_type = heathrow_kvm_type; 425 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 426 mc->default_display = "std"; 427 mc->ignore_boot_device_suffixes = true; 428 mc->default_ram_id = "ppc_heathrow.ram"; 429 fwc->get_dev_path = heathrow_fw_dev_path; 430 } 431 432 static const TypeInfo ppc_heathrow_machine_info = { 433 .name = MACHINE_TYPE_NAME("g3beige"), 434 .parent = TYPE_MACHINE, 435 .class_init = heathrow_class_init, 436 .interfaces = (InterfaceInfo[]) { 437 { TYPE_FW_PATH_PROVIDER }, 438 { } 439 }, 440 }; 441 442 static void ppc_heathrow_register_types(void) 443 { 444 type_register_static(&ppc_heathrow_machine_info); 445 } 446 447 type_init(ppc_heathrow_register_types); 448