1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/ppc/ppc.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/boards.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/pci-host/grackle.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/loader.h" 45 #include "hw/fw-path-provider.h" 46 #include "elf.h" 47 #include "qemu/error-report.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/reset.h" 50 #include "kvm_ppc.h" 51 52 #define MAX_IDE_BUS 2 53 #define CFG_ADDR 0xf0000510 54 #define TBFREQ 16600000UL 55 #define CLOCKFREQ 266000000UL 56 #define BUSFREQ 66000000UL 57 58 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 59 60 #define PROM_FILENAME "openbios-ppc" 61 #define PROM_BASE 0xffc00000 62 #define PROM_SIZE (4 * MiB) 63 64 #define KERNEL_LOAD_ADDR 0x01000000 65 #define KERNEL_GAP 0x00100000 66 67 #define GRACKLE_BASE 0xfec00000 68 69 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 70 Error **errp) 71 { 72 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 73 } 74 75 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 76 { 77 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 78 } 79 80 static void ppc_heathrow_reset(void *opaque) 81 { 82 PowerPCCPU *cpu = opaque; 83 84 cpu_ppc_tb_reset(&cpu->env); 85 cpu_reset(CPU(cpu)); 86 } 87 88 static void ppc_heathrow_init(MachineState *machine) 89 { 90 const char *bios_name = machine->firmware ?: PROM_FILENAME; 91 MachineClass *mc = MACHINE_GET_CLASS(machine); 92 PowerPCCPU *cpu = NULL; 93 CPUPPCState *env = NULL; 94 char *filename; 95 int i, bios_size = -1; 96 MemoryRegion *bios = g_new(MemoryRegion, 1); 97 uint64_t bios_addr; 98 uint32_t kernel_base = 0, initrd_base = 0, cmdline_base = 0; 99 int32_t kernel_size = 0, initrd_size = 0; 100 PCIBus *pci_bus; 101 Object *macio; 102 MACIOIDEState *macio_ide; 103 SysBusDevice *s; 104 DeviceState *dev, *pic_dev, *grackle_dev; 105 BusState *adb_bus; 106 uint16_t ppc_boot_device; 107 DriveInfo *dinfo, *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 108 void *fw_cfg; 109 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 110 111 /* init CPUs */ 112 for (i = 0; i < machine->smp.cpus; i++) { 113 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &cpu->env; 115 116 /* Set time-base frequency to 16.6 Mhz */ 117 cpu_ppc_tb_init(env, TBFREQ); 118 qemu_register_reset(ppc_heathrow_reset, cpu); 119 } 120 121 /* allocate RAM */ 122 if (machine->ram_size > 2047 * MiB) { 123 error_report("Too much memory for this machine: %" PRId64 " MB, " 124 "maximum 2047 MB", machine->ram_size / MiB); 125 exit(1); 126 } 127 128 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 129 130 /* allocate and load firmware ROM */ 131 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE, 132 &error_fatal); 133 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 134 135 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 136 if (filename) { 137 /* Load OpenBIOS (ELF) */ 138 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr, 139 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 140 /* Unfortunately, load_elf sign-extends reading elf32 */ 141 bios_addr = (uint32_t)bios_addr; 142 143 if (bios_size <= 0) { 144 /* or if could not load ELF try loading a binary ROM image */ 145 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 146 bios_addr = PROM_BASE; 147 } 148 g_free(filename); 149 } 150 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) { 151 error_report("could not load PowerPC bios '%s'", bios_name); 152 exit(1); 153 } 154 155 if (machine->kernel_filename) { 156 int bswap_needed = 0; 157 158 #ifdef BSWAP_NEEDED 159 bswap_needed = 1; 160 #endif 161 kernel_base = KERNEL_LOAD_ADDR; 162 kernel_size = load_elf(machine->kernel_filename, NULL, 163 translate_kernel_address, NULL, NULL, NULL, 164 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 165 if (kernel_size < 0) { 166 kernel_size = load_aout(machine->kernel_filename, kernel_base, 167 machine->ram_size - kernel_base, 168 bswap_needed, TARGET_PAGE_SIZE); 169 } 170 if (kernel_size < 0) { 171 kernel_size = load_image_targphys(machine->kernel_filename, 172 kernel_base, 173 machine->ram_size - kernel_base); 174 } 175 if (kernel_size < 0) { 176 error_report("could not load kernel '%s'", 177 machine->kernel_filename); 178 exit(1); 179 } 180 /* load initrd */ 181 if (machine->initrd_filename) { 182 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + 183 KERNEL_GAP); 184 initrd_size = load_image_targphys(machine->initrd_filename, 185 initrd_base, 186 machine->ram_size - initrd_base); 187 if (initrd_size < 0) { 188 error_report("could not load initial ram disk '%s'", 189 machine->initrd_filename); 190 exit(1); 191 } 192 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 193 } else { 194 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 195 } 196 ppc_boot_device = 'm'; 197 } else { 198 ppc_boot_device = '\0'; 199 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 200 /* 201 * TOFIX: for now, the second IDE channel is not properly 202 * used by OHW. The Mac floppy disk are not emulated. 203 * For now, OHW cannot boot from the network. 204 */ 205 #if 0 206 if (machine->boot_config.order[i] >= 'a' && 207 machine->boot_config.order[i] <= 'f') { 208 ppc_boot_device = machine->boot_config.order[i]; 209 break; 210 } 211 #else 212 if (machine->boot_config.order[i] >= 'c' && 213 machine->boot_config.order[i] <= 'd') { 214 ppc_boot_device = machine->boot_config.order[i]; 215 break; 216 } 217 #endif 218 } 219 if (ppc_boot_device == '\0') { 220 error_report("No valid boot device for G3 Beige machine"); 221 exit(1); 222 } 223 } 224 225 /* Grackle PCI host bridge */ 226 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE); 227 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000); 228 s = SYS_BUS_DEVICE(grackle_dev); 229 sysbus_realize_and_unref(s, &error_fatal); 230 231 sysbus_mmio_map(s, 0, GRACKLE_BASE); 232 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 233 /* PCI hole */ 234 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 235 sysbus_mmio_get_region(s, 2)); 236 /* Register 2 MB of ISA IO space */ 237 memory_region_add_subregion(get_system_memory(), 0xfe000000, 238 sysbus_mmio_get_region(s, 3)); 239 240 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus; 241 242 /* MacIO */ 243 macio = OBJECT(pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO)); 244 qdev_prop_set_uint64(DEVICE(macio), "frequency", tbfreq); 245 246 dev = DEVICE(object_resolve_path_component(macio, "escc")); 247 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 248 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 249 250 dinfo = drive_get(IF_MTD, 0, 0); 251 if (dinfo) { 252 dev = DEVICE(object_resolve_path_component(macio, "nvram")); 253 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 254 } 255 256 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 257 258 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 259 for (i = 0; i < 4; i++) { 260 qdev_connect_gpio_out(grackle_dev, i, 261 qdev_get_gpio_in(pic_dev, 0x15 + i)); 262 } 263 264 /* Connect the heathrow PIC outputs to the 6xx bus */ 265 for (i = 0; i < machine->smp.cpus; i++) { 266 switch (PPC_INPUT(env)) { 267 case PPC_FLAGS_INPUT_6xx: 268 /* XXX: we register only 1 output pin for heathrow PIC */ 269 qdev_connect_gpio_out(pic_dev, 0, 270 qdev_get_gpio_in(DEVICE(cpu), PPC6xx_INPUT_INT)); 271 break; 272 default: 273 error_report("Bus model not supported on OldWorld Mac machine"); 274 exit(1); 275 } 276 } 277 278 pci_vga_init(pci_bus); 279 280 for (i = 0; i < nb_nics; i++) { 281 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 282 } 283 284 /* MacIO IDE */ 285 ide_drive_get(hd, ARRAY_SIZE(hd)); 286 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 287 macio_ide_init_drives(macio_ide, hd); 288 289 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 290 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 291 292 /* MacIO CUDA/ADB */ 293 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 294 adb_bus = qdev_get_child_bus(dev, "adb.0"); 295 dev = qdev_new(TYPE_ADB_KEYBOARD); 296 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 297 dev = qdev_new(TYPE_ADB_MOUSE); 298 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 299 300 if (machine_usb(machine)) { 301 pci_create_simple(pci_bus, -1, "pci-ohci"); 302 } 303 304 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 305 graphic_depth = 15; 306 } 307 308 /* No PCI init: the BIOS will do it */ 309 310 dev = qdev_new(TYPE_FW_CFG_MEM); 311 fw_cfg = FW_CFG(dev); 312 qdev_prop_set_uint32(dev, "data_width", 1); 313 qdev_prop_set_bit(dev, "dma_enabled", false); 314 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); 315 s = SYS_BUS_DEVICE(dev); 316 sysbus_realize_and_unref(s, &error_fatal); 317 sysbus_mmio_map(s, 0, CFG_ADDR); 318 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 319 320 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 321 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 322 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 323 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 324 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 325 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 326 if (machine->kernel_cmdline) { 327 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 328 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 329 machine->kernel_cmdline); 330 } else { 331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 332 } 333 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 334 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 335 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 336 337 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 338 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 339 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 340 341 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 342 if (kvm_enabled()) { 343 uint8_t *hypercall; 344 345 hypercall = g_malloc(16); 346 kvmppc_get_hypercall(env, hypercall, 16); 347 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 348 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 349 } 350 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 351 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 352 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 353 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 354 355 /* MacOS NDRV VGA driver */ 356 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 357 if (filename) { 358 gchar *ndrv_file; 359 gsize ndrv_size; 360 361 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 362 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 363 } 364 g_free(filename); 365 } 366 367 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 368 } 369 370 /* 371 * Implementation of an interface to adjust firmware path 372 * for the bootindex property handling. 373 */ 374 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 375 DeviceState *dev) 376 { 377 PCIDevice *pci; 378 MACIOIDEState *macio_ide; 379 380 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 381 pci = PCI_DEVICE(dev); 382 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 383 } 384 385 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 386 macio_ide = MACIO_IDE(dev); 387 return g_strdup_printf("ata-3@%x", macio_ide->addr); 388 } 389 390 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 391 return g_strdup("disk"); 392 } 393 394 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 395 return g_strdup("cdrom"); 396 } 397 398 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 399 return g_strdup("disk"); 400 } 401 402 return NULL; 403 } 404 405 static int heathrow_kvm_type(MachineState *machine, const char *arg) 406 { 407 /* Always force PR KVM */ 408 return 2; 409 } 410 411 static void heathrow_class_init(ObjectClass *oc, void *data) 412 { 413 MachineClass *mc = MACHINE_CLASS(oc); 414 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 415 416 mc->desc = "Heathrow based PowerMAC"; 417 mc->init = ppc_heathrow_init; 418 mc->block_default_type = IF_IDE; 419 /* SMP is not supported currently */ 420 mc->max_cpus = 1; 421 #ifndef TARGET_PPC64 422 mc->is_default = true; 423 #endif 424 /* TOFIX "cad" when Mac floppy is implemented */ 425 mc->default_boot_order = "cd"; 426 mc->kvm_type = heathrow_kvm_type; 427 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 428 mc->default_display = "std"; 429 mc->default_nic = "ne2k_pci"; 430 mc->ignore_boot_device_suffixes = true; 431 mc->default_ram_id = "ppc_heathrow.ram"; 432 fwc->get_dev_path = heathrow_fw_dev_path; 433 } 434 435 static const TypeInfo ppc_heathrow_machine_info = { 436 .name = MACHINE_TYPE_NAME("g3beige"), 437 .parent = TYPE_MACHINE, 438 .class_init = heathrow_class_init, 439 .interfaces = (InterfaceInfo[]) { 440 { TYPE_FW_PATH_PROVIDER }, 441 { } 442 }, 443 }; 444 445 static void ppc_heathrow_register_types(void) 446 { 447 type_register_static(&ppc_heathrow_machine_info); 448 } 449 450 type_init(ppc_heathrow_register_types); 451