1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu-common.h" 29 #include "qemu/units.h" 30 #include "qapi/error.h" 31 #include "hw/hw.h" 32 #include "hw/ppc/ppc.h" 33 #include "mac.h" 34 #include "hw/input/adb.h" 35 #include "sysemu/sysemu.h" 36 #include "net/net.h" 37 #include "hw/isa/isa.h" 38 #include "hw/pci/pci.h" 39 #include "hw/pci/pci_host.h" 40 #include "hw/boards.h" 41 #include "hw/nvram/fw_cfg.h" 42 #include "hw/char/escc.h" 43 #include "hw/misc/macio/macio.h" 44 #include "hw/ide.h" 45 #include "hw/loader.h" 46 #include "hw/fw-path-provider.h" 47 #include "elf.h" 48 #include "qemu/error-report.h" 49 #include "sysemu/kvm.h" 50 #include "kvm_ppc.h" 51 #include "exec/address-spaces.h" 52 53 #define MAX_IDE_BUS 2 54 #define CFG_ADDR 0xf0000510 55 #define TBFREQ 16600000UL 56 #define CLOCKFREQ 266000000UL 57 #define BUSFREQ 66000000UL 58 59 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 60 61 #define GRACKLE_BASE 0xfec00000 62 63 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 64 Error **errp) 65 { 66 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 67 } 68 69 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 70 { 71 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 72 } 73 74 static void ppc_heathrow_reset(void *opaque) 75 { 76 PowerPCCPU *cpu = opaque; 77 78 cpu_reset(CPU(cpu)); 79 } 80 81 static void ppc_heathrow_init(MachineState *machine) 82 { 83 ram_addr_t ram_size = machine->ram_size; 84 const char *kernel_filename = machine->kernel_filename; 85 const char *kernel_cmdline = machine->kernel_cmdline; 86 const char *initrd_filename = machine->initrd_filename; 87 const char *boot_device = machine->boot_order; 88 MemoryRegion *sysmem = get_system_memory(); 89 PowerPCCPU *cpu = NULL; 90 CPUPPCState *env = NULL; 91 char *filename; 92 int linux_boot, i; 93 MemoryRegion *ram = g_new(MemoryRegion, 1); 94 MemoryRegion *bios = g_new(MemoryRegion, 1); 95 uint32_t kernel_base, initrd_base, cmdline_base = 0; 96 int32_t kernel_size, initrd_size; 97 PCIBus *pci_bus; 98 OldWorldMacIOState *macio; 99 MACIOIDEState *macio_ide; 100 SysBusDevice *s; 101 DeviceState *dev, *pic_dev; 102 BusState *adb_bus; 103 int bios_size; 104 uint16_t ppc_boot_device; 105 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 106 void *fw_cfg; 107 uint64_t tbfreq; 108 109 linux_boot = (kernel_filename != NULL); 110 111 /* init CPUs */ 112 for (i = 0; i < smp_cpus; i++) { 113 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 114 env = &cpu->env; 115 116 /* Set time-base frequency to 16.6 Mhz */ 117 cpu_ppc_tb_init(env, TBFREQ); 118 qemu_register_reset(ppc_heathrow_reset, cpu); 119 } 120 121 /* allocate RAM */ 122 if (ram_size > 2047 * MiB) { 123 error_report("Too much memory for this machine: %" PRId64 " MB, " 124 "maximum 2047 MB", ram_size / MiB); 125 exit(1); 126 } 127 128 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 129 ram_size); 130 memory_region_add_subregion(sysmem, 0, ram); 131 132 /* allocate and load BIOS */ 133 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, 134 &error_fatal); 135 136 if (bios_name == NULL) 137 bios_name = PROM_FILENAME; 138 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 139 memory_region_set_readonly(bios, true); 140 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 141 142 /* Load OpenBIOS (ELF) */ 143 if (filename) { 144 bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL, 145 1, PPC_ELF_MACHINE, 0, 0); 146 g_free(filename); 147 } else { 148 bios_size = -1; 149 } 150 if (bios_size < 0 || bios_size > BIOS_SIZE) { 151 error_report("could not load PowerPC bios '%s'", bios_name); 152 exit(1); 153 } 154 155 if (linux_boot) { 156 uint64_t lowaddr = 0; 157 int bswap_needed; 158 159 #ifdef BSWAP_NEEDED 160 bswap_needed = 1; 161 #else 162 bswap_needed = 0; 163 #endif 164 kernel_base = KERNEL_LOAD_ADDR; 165 kernel_size = load_elf(kernel_filename, NULL, 166 translate_kernel_address, NULL, 167 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 168 0, 0); 169 if (kernel_size < 0) 170 kernel_size = load_aout(kernel_filename, kernel_base, 171 ram_size - kernel_base, bswap_needed, 172 TARGET_PAGE_SIZE); 173 if (kernel_size < 0) 174 kernel_size = load_image_targphys(kernel_filename, 175 kernel_base, 176 ram_size - kernel_base); 177 if (kernel_size < 0) { 178 error_report("could not load kernel '%s'", kernel_filename); 179 exit(1); 180 } 181 /* load initrd */ 182 if (initrd_filename) { 183 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 184 initrd_size = load_image_targphys(initrd_filename, initrd_base, 185 ram_size - initrd_base); 186 if (initrd_size < 0) { 187 error_report("could not load initial ram disk '%s'", 188 initrd_filename); 189 exit(1); 190 } 191 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 192 } else { 193 initrd_base = 0; 194 initrd_size = 0; 195 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 196 } 197 ppc_boot_device = 'm'; 198 } else { 199 kernel_base = 0; 200 kernel_size = 0; 201 initrd_base = 0; 202 initrd_size = 0; 203 ppc_boot_device = '\0'; 204 for (i = 0; boot_device[i] != '\0'; i++) { 205 /* TOFIX: for now, the second IDE channel is not properly 206 * used by OHW. The Mac floppy disk are not emulated. 207 * For now, OHW cannot boot from the network. 208 */ 209 #if 0 210 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 211 ppc_boot_device = boot_device[i]; 212 break; 213 } 214 #else 215 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 216 ppc_boot_device = boot_device[i]; 217 break; 218 } 219 #endif 220 } 221 if (ppc_boot_device == '\0') { 222 error_report("No valid boot device for G3 Beige machine"); 223 exit(1); 224 } 225 } 226 227 /* XXX: we register only 1 output pin for heathrow PIC */ 228 pic_dev = qdev_create(NULL, TYPE_HEATHROW); 229 qdev_init_nofail(pic_dev); 230 231 /* Connect the heathrow PIC outputs to the 6xx bus */ 232 for (i = 0; i < smp_cpus; i++) { 233 switch (PPC_INPUT(env)) { 234 case PPC_FLAGS_INPUT_6xx: 235 qdev_connect_gpio_out(pic_dev, 0, 236 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]); 237 break; 238 default: 239 error_report("Bus model not supported on OldWorld Mac machine"); 240 exit(1); 241 } 242 } 243 244 /* Timebase Frequency */ 245 if (kvm_enabled()) { 246 tbfreq = kvmppc_get_tbfreq(); 247 } else { 248 tbfreq = TBFREQ; 249 } 250 251 /* init basic PC hardware */ 252 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 253 error_report("Only 6xx bus is supported on heathrow machine"); 254 exit(1); 255 } 256 257 /* Grackle PCI host bridge */ 258 dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE); 259 qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000); 260 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 261 &error_abort); 262 qdev_init_nofail(dev); 263 s = SYS_BUS_DEVICE(dev); 264 sysbus_mmio_map(s, 0, GRACKLE_BASE); 265 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000); 266 /* PCI hole */ 267 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 268 sysbus_mmio_get_region(s, 2)); 269 /* Register 2 MB of ISA IO space */ 270 memory_region_add_subregion(get_system_memory(), 0xfe000000, 271 sysbus_mmio_get_region(s, 3)); 272 273 pci_bus = PCI_HOST_BRIDGE(dev)->bus; 274 275 pci_vga_init(pci_bus); 276 277 for (i = 0; i < nb_nics; i++) { 278 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 279 } 280 281 ide_drive_get(hd, ARRAY_SIZE(hd)); 282 283 /* MacIO */ 284 macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO)); 285 dev = DEVICE(macio); 286 qdev_prop_set_uint64(dev, "frequency", tbfreq); 287 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 288 &error_abort); 289 qdev_init_nofail(dev); 290 291 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 292 "ide[0]")); 293 macio_ide_init_drives(macio_ide, hd); 294 295 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 296 "ide[1]")); 297 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 298 299 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 300 adb_bus = qdev_get_child_bus(dev, "adb.0"); 301 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 302 qdev_init_nofail(dev); 303 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 304 qdev_init_nofail(dev); 305 306 if (machine_usb(machine)) { 307 pci_create_simple(pci_bus, -1, "pci-ohci"); 308 } 309 310 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 311 graphic_depth = 15; 312 313 /* No PCI init: the BIOS will do it */ 314 315 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 316 fw_cfg = FW_CFG(dev); 317 qdev_prop_set_uint32(dev, "data_width", 1); 318 qdev_prop_set_bit(dev, "dma_enabled", false); 319 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 320 OBJECT(fw_cfg), NULL); 321 qdev_init_nofail(dev); 322 s = SYS_BUS_DEVICE(dev); 323 sysbus_mmio_map(s, 0, CFG_ADDR); 324 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 325 326 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 327 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 328 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 329 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 330 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 332 if (kernel_cmdline) { 333 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 334 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 335 } else { 336 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 337 } 338 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 339 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 340 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 341 342 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 343 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 344 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 345 346 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 347 if (kvm_enabled()) { 348 uint8_t *hypercall; 349 350 hypercall = g_malloc(16); 351 kvmppc_get_hypercall(env, hypercall, 16); 352 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 353 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 354 } 355 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 356 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 357 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 358 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 359 360 /* MacOS NDRV VGA driver */ 361 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 362 if (filename) { 363 gchar *ndrv_file; 364 gsize ndrv_size; 365 366 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 367 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 368 } 369 g_free(filename); 370 } 371 372 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 373 } 374 375 /* 376 * Implementation of an interface to adjust firmware path 377 * for the bootindex property handling. 378 */ 379 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, 380 DeviceState *dev) 381 { 382 PCIDevice *pci; 383 IDEBus *ide_bus; 384 IDEState *ide_s; 385 MACIOIDEState *macio_ide; 386 387 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) { 388 pci = PCI_DEVICE(dev); 389 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 390 } 391 392 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 393 macio_ide = MACIO_IDE(dev); 394 return g_strdup_printf("ata-3@%x", macio_ide->addr); 395 } 396 397 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 398 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 399 ide_s = idebus_active_if(ide_bus); 400 401 if (ide_s->drive_kind == IDE_CD) { 402 return g_strdup("cdrom"); 403 } 404 405 return g_strdup("disk"); 406 } 407 408 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 409 return g_strdup("disk"); 410 } 411 412 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 413 return g_strdup("cdrom"); 414 } 415 416 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 417 return g_strdup("disk"); 418 } 419 420 return NULL; 421 } 422 423 static int heathrow_kvm_type(MachineState *machine, const char *arg) 424 { 425 /* Always force PR KVM */ 426 return 2; 427 } 428 429 static void heathrow_class_init(ObjectClass *oc, void *data) 430 { 431 MachineClass *mc = MACHINE_CLASS(oc); 432 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 433 434 mc->desc = "Heathrow based PowerMAC"; 435 mc->init = ppc_heathrow_init; 436 mc->block_default_type = IF_IDE; 437 mc->max_cpus = MAX_CPUS; 438 #ifndef TARGET_PPC64 439 mc->is_default = 1; 440 #endif 441 /* TOFIX "cad" when Mac floppy is implemented */ 442 mc->default_boot_order = "cd"; 443 mc->kvm_type = heathrow_kvm_type; 444 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); 445 mc->default_display = "std"; 446 mc->ignore_boot_device_suffixes = true; 447 fwc->get_dev_path = heathrow_fw_dev_path; 448 } 449 450 static const TypeInfo ppc_heathrow_machine_info = { 451 .name = MACHINE_TYPE_NAME("g3beige"), 452 .parent = TYPE_MACHINE, 453 .class_init = heathrow_class_init, 454 .interfaces = (InterfaceInfo[]) { 455 { TYPE_FW_PATH_PROVIDER }, 456 { } 457 }, 458 }; 459 460 static void ppc_heathrow_register_types(void) 461 { 462 type_register_static(&ppc_heathrow_machine_info); 463 } 464 465 type_init(ppc_heathrow_register_types); 466