1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "hw/hw.h" 27 #include "hw/ppc/ppc.h" 28 #include "mac.h" 29 #include "hw/input/adb.h" 30 #include "hw/timer/m48t59.h" 31 #include "sysemu/sysemu.h" 32 #include "net/net.h" 33 #include "hw/isa/isa.h" 34 #include "hw/pci/pci.h" 35 #include "hw/boards.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/char/escc.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "sysemu/kvm.h" 42 #include "kvm_ppc.h" 43 #include "sysemu/blockdev.h" 44 #include "exec/address-spaces.h" 45 46 #define MAX_IDE_BUS 2 47 #define CFG_ADDR 0xf0000510 48 #define TBFREQ 16600000UL 49 #define CLOCKFREQ 266000000UL 50 #define BUSFREQ 66000000UL 51 52 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 53 { 54 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 55 return 0; 56 } 57 58 59 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 60 { 61 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 62 } 63 64 static hwaddr round_page(hwaddr addr) 65 { 66 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 67 } 68 69 static void ppc_heathrow_reset(void *opaque) 70 { 71 PowerPCCPU *cpu = opaque; 72 73 cpu_reset(CPU(cpu)); 74 } 75 76 static void ppc_heathrow_init(MachineState *machine) 77 { 78 ram_addr_t ram_size = machine->ram_size; 79 const char *cpu_model = machine->cpu_model; 80 const char *kernel_filename = machine->kernel_filename; 81 const char *kernel_cmdline = machine->kernel_cmdline; 82 const char *initrd_filename = machine->initrd_filename; 83 const char *boot_device = machine->boot_order; 84 MemoryRegion *sysmem = get_system_memory(); 85 PowerPCCPU *cpu = NULL; 86 CPUPPCState *env = NULL; 87 char *filename; 88 qemu_irq *pic, **heathrow_irqs; 89 int linux_boot, i; 90 MemoryRegion *ram = g_new(MemoryRegion, 1); 91 MemoryRegion *bios = g_new(MemoryRegion, 1); 92 MemoryRegion *isa = g_new(MemoryRegion, 1); 93 uint32_t kernel_base, initrd_base, cmdline_base = 0; 94 int32_t kernel_size, initrd_size; 95 PCIBus *pci_bus; 96 PCIDevice *macio; 97 MACIOIDEState *macio_ide; 98 DeviceState *dev; 99 BusState *adb_bus; 100 int bios_size; 101 MemoryRegion *pic_mem; 102 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 103 uint16_t ppc_boot_device; 104 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 105 void *fw_cfg; 106 107 linux_boot = (kernel_filename != NULL); 108 109 /* init CPUs */ 110 if (cpu_model == NULL) 111 cpu_model = "G3"; 112 for (i = 0; i < smp_cpus; i++) { 113 cpu = cpu_ppc_init(cpu_model); 114 if (cpu == NULL) { 115 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 116 exit(1); 117 } 118 env = &cpu->env; 119 120 /* Set time-base frequency to 16.6 Mhz */ 121 cpu_ppc_tb_init(env, TBFREQ); 122 qemu_register_reset(ppc_heathrow_reset, cpu); 123 } 124 125 /* allocate RAM */ 126 if (ram_size > (2047 << 20)) { 127 fprintf(stderr, 128 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 129 ((unsigned int)ram_size / (1 << 20))); 130 exit(1); 131 } 132 133 memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", 134 ram_size); 135 memory_region_add_subregion(sysmem, 0, ram); 136 137 /* allocate and load BIOS */ 138 memory_region_allocate_system_memory(bios, NULL, "ppc_heathrow.bios", 139 BIOS_SIZE); 140 if (bios_name == NULL) 141 bios_name = PROM_FILENAME; 142 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 143 memory_region_set_readonly(bios, true); 144 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 145 146 /* Load OpenBIOS (ELF) */ 147 if (filename) { 148 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 149 1, ELF_MACHINE, 0); 150 g_free(filename); 151 } else { 152 bios_size = -1; 153 } 154 if (bios_size < 0 || bios_size > BIOS_SIZE) { 155 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); 156 exit(1); 157 } 158 159 if (linux_boot) { 160 uint64_t lowaddr = 0; 161 int bswap_needed; 162 163 #ifdef BSWAP_NEEDED 164 bswap_needed = 1; 165 #else 166 bswap_needed = 0; 167 #endif 168 kernel_base = KERNEL_LOAD_ADDR; 169 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 170 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 171 if (kernel_size < 0) 172 kernel_size = load_aout(kernel_filename, kernel_base, 173 ram_size - kernel_base, bswap_needed, 174 TARGET_PAGE_SIZE); 175 if (kernel_size < 0) 176 kernel_size = load_image_targphys(kernel_filename, 177 kernel_base, 178 ram_size - kernel_base); 179 if (kernel_size < 0) { 180 hw_error("qemu: could not load kernel '%s'\n", 181 kernel_filename); 182 exit(1); 183 } 184 /* load initrd */ 185 if (initrd_filename) { 186 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 187 initrd_size = load_image_targphys(initrd_filename, initrd_base, 188 ram_size - initrd_base); 189 if (initrd_size < 0) { 190 hw_error("qemu: could not load initial ram disk '%s'\n", 191 initrd_filename); 192 exit(1); 193 } 194 cmdline_base = round_page(initrd_base + initrd_size); 195 } else { 196 initrd_base = 0; 197 initrd_size = 0; 198 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 199 } 200 ppc_boot_device = 'm'; 201 } else { 202 kernel_base = 0; 203 kernel_size = 0; 204 initrd_base = 0; 205 initrd_size = 0; 206 ppc_boot_device = '\0'; 207 for (i = 0; boot_device[i] != '\0'; i++) { 208 /* TOFIX: for now, the second IDE channel is not properly 209 * used by OHW. The Mac floppy disk are not emulated. 210 * For now, OHW cannot boot from the network. 211 */ 212 #if 0 213 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 214 ppc_boot_device = boot_device[i]; 215 break; 216 } 217 #else 218 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 219 ppc_boot_device = boot_device[i]; 220 break; 221 } 222 #endif 223 } 224 if (ppc_boot_device == '\0') { 225 fprintf(stderr, "No valid boot device for G3 Beige machine\n"); 226 exit(1); 227 } 228 } 229 230 /* Register 2 MB of ISA IO space */ 231 memory_region_init_alias(isa, NULL, "isa_mmio", 232 get_system_io(), 0, 0x00200000); 233 memory_region_add_subregion(sysmem, 0xfe000000, isa); 234 235 /* XXX: we register only 1 output pin for heathrow PIC */ 236 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 237 heathrow_irqs[0] = 238 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 239 /* Connect the heathrow PIC outputs to the 6xx bus */ 240 for (i = 0; i < smp_cpus; i++) { 241 switch (PPC_INPUT(env)) { 242 case PPC_FLAGS_INPUT_6xx: 243 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 244 heathrow_irqs[i][0] = 245 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 246 break; 247 default: 248 hw_error("Bus model not supported on OldWorld Mac machine\n"); 249 } 250 } 251 252 /* init basic PC hardware */ 253 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 254 hw_error("Only 6xx bus is supported on heathrow machine\n"); 255 } 256 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 257 pci_bus = pci_grackle_init(0xfec00000, pic, 258 get_system_memory(), 259 get_system_io()); 260 pci_vga_init(pci_bus); 261 262 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], 263 serial_hds[1], ESCC_CLOCK, 4); 264 memory_region_init_alias(escc_bar, NULL, "escc-bar", 265 escc_mem, 0, memory_region_size(escc_mem)); 266 267 for(i = 0; i < nb_nics; i++) 268 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 269 270 271 ide_drive_get(hd, MAX_IDE_BUS); 272 273 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 274 dev = DEVICE(macio); 275 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 276 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 277 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 278 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 279 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 280 macio_init(macio, pic_mem, escc_bar); 281 282 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 283 "ide[0]")); 284 macio_ide_init_drives(macio_ide, hd); 285 286 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 287 "ide[1]")); 288 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 289 290 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 291 adb_bus = qdev_get_child_bus(dev, "adb.0"); 292 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 293 qdev_init_nofail(dev); 294 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 295 qdev_init_nofail(dev); 296 297 if (usb_enabled(false)) { 298 pci_create_simple(pci_bus, -1, "pci-ohci"); 299 } 300 301 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 302 graphic_depth = 15; 303 304 /* No PCI init: the BIOS will do it */ 305 306 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 307 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 308 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 309 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 310 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 311 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 312 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 313 if (kernel_cmdline) { 314 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 315 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 316 } else { 317 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 318 } 319 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 320 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 321 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 322 323 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 324 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 325 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 326 327 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 328 if (kvm_enabled()) { 329 #ifdef CONFIG_KVM 330 uint8_t *hypercall; 331 332 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 333 hypercall = g_malloc(16); 334 kvmppc_get_hypercall(env, hypercall, 16); 335 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 336 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 337 #endif 338 } else { 339 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ); 340 } 341 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 342 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 343 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 344 345 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 346 } 347 348 static QEMUMachine heathrow_machine = { 349 .name = "g3beige", 350 .desc = "Heathrow based PowerMAC", 351 .init = ppc_heathrow_init, 352 .max_cpus = MAX_CPUS, 353 #ifndef TARGET_PPC64 354 .is_default = 1, 355 #endif 356 .default_boot_order = "cd", /* TOFIX "cad" when Mac floppy is implemented */ 357 }; 358 359 static void heathrow_machine_init(void) 360 { 361 qemu_register_machine(&heathrow_machine); 362 } 363 364 machine_init(heathrow_machine_init); 365