1 2 /* 3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator 4 * 5 * Copyright (c) 2004-2007 Fabrice Bellard 6 * Copyright (c) 2007 Jocelyn Mayer 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 #include "hw/hw.h" 27 #include "hw/ppc/ppc.h" 28 #include "mac.h" 29 #include "hw/input/adb.h" 30 #include "hw/timer/m48t59.h" 31 #include "sysemu/sysemu.h" 32 #include "net/net.h" 33 #include "hw/isa/isa.h" 34 #include "hw/pci/pci.h" 35 #include "hw/boards.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/char/escc.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "sysemu/kvm.h" 42 #include "kvm_ppc.h" 43 #include "sysemu/blockdev.h" 44 #include "exec/address-spaces.h" 45 46 #define MAX_IDE_BUS 2 47 #define CFG_ADDR 0xf0000510 48 #define TBFREQ 16600000UL 49 50 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 51 { 52 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 53 return 0; 54 } 55 56 57 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 58 { 59 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 60 } 61 62 static hwaddr round_page(hwaddr addr) 63 { 64 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 65 } 66 67 static void ppc_heathrow_reset(void *opaque) 68 { 69 PowerPCCPU *cpu = opaque; 70 71 cpu_reset(CPU(cpu)); 72 } 73 74 static void ppc_heathrow_init(QEMUMachineInitArgs *args) 75 { 76 ram_addr_t ram_size = args->ram_size; 77 const char *cpu_model = args->cpu_model; 78 const char *kernel_filename = args->kernel_filename; 79 const char *kernel_cmdline = args->kernel_cmdline; 80 const char *initrd_filename = args->initrd_filename; 81 const char *boot_device = args->boot_device; 82 MemoryRegion *sysmem = get_system_memory(); 83 PowerPCCPU *cpu = NULL; 84 CPUPPCState *env = NULL; 85 char *filename; 86 qemu_irq *pic, **heathrow_irqs; 87 int linux_boot, i; 88 MemoryRegion *ram = g_new(MemoryRegion, 1); 89 MemoryRegion *bios = g_new(MemoryRegion, 1); 90 uint32_t kernel_base, initrd_base, cmdline_base = 0; 91 int32_t kernel_size, initrd_size; 92 PCIBus *pci_bus; 93 PCIDevice *macio; 94 MACIOIDEState *macio_ide; 95 DeviceState *dev; 96 BusState *adb_bus; 97 int bios_size; 98 MemoryRegion *pic_mem; 99 MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1); 100 uint16_t ppc_boot_device; 101 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 102 void *fw_cfg; 103 104 linux_boot = (kernel_filename != NULL); 105 106 /* init CPUs */ 107 if (cpu_model == NULL) 108 cpu_model = "G3"; 109 for (i = 0; i < smp_cpus; i++) { 110 cpu = cpu_ppc_init(cpu_model); 111 if (cpu == NULL) { 112 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 113 exit(1); 114 } 115 env = &cpu->env; 116 117 /* Set time-base frequency to 16.6 Mhz */ 118 cpu_ppc_tb_init(env, TBFREQ); 119 qemu_register_reset(ppc_heathrow_reset, cpu); 120 } 121 122 /* allocate RAM */ 123 if (ram_size > (2047 << 20)) { 124 fprintf(stderr, 125 "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n", 126 ((unsigned int)ram_size / (1 << 20))); 127 exit(1); 128 } 129 130 memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size); 131 vmstate_register_ram_global(ram); 132 memory_region_add_subregion(sysmem, 0, ram); 133 134 /* allocate and load BIOS */ 135 memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE); 136 vmstate_register_ram_global(bios); 137 if (bios_name == NULL) 138 bios_name = PROM_FILENAME; 139 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 140 memory_region_set_readonly(bios, true); 141 memory_region_add_subregion(sysmem, PROM_ADDR, bios); 142 143 /* Load OpenBIOS (ELF) */ 144 if (filename) { 145 bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL, 146 1, ELF_MACHINE, 0); 147 g_free(filename); 148 } else { 149 bios_size = -1; 150 } 151 if (bios_size < 0 || bios_size > BIOS_SIZE) { 152 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); 153 exit(1); 154 } 155 156 if (linux_boot) { 157 uint64_t lowaddr = 0; 158 int bswap_needed; 159 160 #ifdef BSWAP_NEEDED 161 bswap_needed = 1; 162 #else 163 bswap_needed = 0; 164 #endif 165 kernel_base = KERNEL_LOAD_ADDR; 166 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 167 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 168 if (kernel_size < 0) 169 kernel_size = load_aout(kernel_filename, kernel_base, 170 ram_size - kernel_base, bswap_needed, 171 TARGET_PAGE_SIZE); 172 if (kernel_size < 0) 173 kernel_size = load_image_targphys(kernel_filename, 174 kernel_base, 175 ram_size - kernel_base); 176 if (kernel_size < 0) { 177 hw_error("qemu: could not load kernel '%s'\n", 178 kernel_filename); 179 exit(1); 180 } 181 /* load initrd */ 182 if (initrd_filename) { 183 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 184 initrd_size = load_image_targphys(initrd_filename, initrd_base, 185 ram_size - initrd_base); 186 if (initrd_size < 0) { 187 hw_error("qemu: could not load initial ram disk '%s'\n", 188 initrd_filename); 189 exit(1); 190 } 191 cmdline_base = round_page(initrd_base + initrd_size); 192 } else { 193 initrd_base = 0; 194 initrd_size = 0; 195 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 196 } 197 ppc_boot_device = 'm'; 198 } else { 199 kernel_base = 0; 200 kernel_size = 0; 201 initrd_base = 0; 202 initrd_size = 0; 203 ppc_boot_device = '\0'; 204 for (i = 0; boot_device[i] != '\0'; i++) { 205 /* TOFIX: for now, the second IDE channel is not properly 206 * used by OHW. The Mac floppy disk are not emulated. 207 * For now, OHW cannot boot from the network. 208 */ 209 #if 0 210 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 211 ppc_boot_device = boot_device[i]; 212 break; 213 } 214 #else 215 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') { 216 ppc_boot_device = boot_device[i]; 217 break; 218 } 219 #endif 220 } 221 if (ppc_boot_device == '\0') { 222 fprintf(stderr, "No valid boot device for G3 Beige machine\n"); 223 exit(1); 224 } 225 } 226 227 /* Register 2 MB of ISA IO space */ 228 isa_mmio_init(0xfe000000, 0x00200000); 229 230 /* XXX: we register only 1 output pin for heathrow PIC */ 231 heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 232 heathrow_irqs[0] = 233 g_malloc0(smp_cpus * sizeof(qemu_irq) * 1); 234 /* Connect the heathrow PIC outputs to the 6xx bus */ 235 for (i = 0; i < smp_cpus; i++) { 236 switch (PPC_INPUT(env)) { 237 case PPC_FLAGS_INPUT_6xx: 238 heathrow_irqs[i] = heathrow_irqs[0] + (i * 1); 239 heathrow_irqs[i][0] = 240 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 241 break; 242 default: 243 hw_error("Bus model not supported on OldWorld Mac machine\n"); 244 } 245 } 246 247 /* init basic PC hardware */ 248 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 249 hw_error("Only 6xx bus is supported on heathrow machine\n"); 250 } 251 pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs); 252 pci_bus = pci_grackle_init(0xfec00000, pic, 253 get_system_memory(), 254 get_system_io()); 255 pci_vga_init(pci_bus); 256 257 escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0], 258 serial_hds[1], ESCC_CLOCK, 4); 259 memory_region_init_alias(escc_bar, NULL, "escc-bar", 260 escc_mem, 0, memory_region_size(escc_mem)); 261 262 for(i = 0; i < nb_nics; i++) 263 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 264 265 266 ide_drive_get(hd, MAX_IDE_BUS); 267 268 macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO); 269 dev = DEVICE(macio); 270 qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */ 271 qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */ 272 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */ 273 qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */ 274 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */ 275 macio_init(macio, pic_mem, escc_bar); 276 277 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 278 "ide[0]")); 279 macio_ide_init_drives(macio_ide, hd); 280 281 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 282 "ide[1]")); 283 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 284 285 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 286 adb_bus = qdev_get_child_bus(dev, "adb.0"); 287 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 288 qdev_init_nofail(dev); 289 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 290 qdev_init_nofail(dev); 291 292 if (usb_enabled(false)) { 293 pci_create_simple(pci_bus, -1, "pci-ohci"); 294 } 295 296 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) 297 graphic_depth = 15; 298 299 /* No PCI init: the BIOS will do it */ 300 301 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 302 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 303 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 304 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 305 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW); 306 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 307 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 308 if (kernel_cmdline) { 309 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 310 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 311 } else { 312 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 313 } 314 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 315 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 316 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 317 318 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 319 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 320 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 321 322 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 323 if (kvm_enabled()) { 324 #ifdef CONFIG_KVM 325 uint8_t *hypercall; 326 327 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 328 hypercall = g_malloc(16); 329 kvmppc_get_hypercall(env, hypercall, 16); 330 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 331 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 332 #endif 333 } else { 334 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ); 335 } 336 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 337 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, 266000000); 338 339 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 340 } 341 342 static QEMUMachine heathrow_machine = { 343 .name = "g3beige", 344 .desc = "Heathrow based PowerMAC", 345 .init = ppc_heathrow_init, 346 .max_cpus = MAX_CPUS, 347 #ifndef TARGET_PPC64 348 .is_default = 1, 349 #endif 350 DEFAULT_MACHINE_OPTIONS, 351 }; 352 353 static void heathrow_machine_init(void) 354 { 355 qemu_register_machine(&heathrow_machine); 356 } 357 358 machine_init(heathrow_machine_init); 359