1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/misc/macio/macio.h" 64 #include "hw/ppc/openpic.h" 65 #include "hw/ide.h" 66 #include "hw/loader.h" 67 #include "elf.h" 68 #include "qemu/error-report.h" 69 #include "sysemu/kvm.h" 70 #include "kvm_ppc.h" 71 #include "hw/usb.h" 72 #include "sysemu/block-backend.h" 73 #include "exec/address-spaces.h" 74 #include "hw/sysbus.h" 75 #include "qemu/cutils.h" 76 #include "trace.h" 77 78 #define MAX_IDE_BUS 2 79 #define CFG_ADDR 0xf0000510 80 #define TBFREQ (100UL * 1000UL * 1000UL) 81 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 82 #define BUSFREQ (100UL * 1000UL * 1000UL) 83 84 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 85 86 /* UniN device */ 87 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 88 unsigned size) 89 { 90 trace_mac99_uninorth_write(addr, value); 91 if (addr == 0x0) { 92 *(int*)opaque = value; 93 } 94 } 95 96 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 97 { 98 uint32_t value; 99 100 value = 0; 101 switch (addr) { 102 case 0: 103 value = *(int*)opaque; 104 } 105 106 trace_mac99_uninorth_read(addr, value); 107 108 return value; 109 } 110 111 static const MemoryRegionOps unin_ops = { 112 .read = unin_read, 113 .write = unin_write, 114 .endianness = DEVICE_NATIVE_ENDIAN, 115 }; 116 117 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 118 Error **errp) 119 { 120 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 121 } 122 123 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 124 { 125 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 126 } 127 128 static void ppc_core99_reset(void *opaque) 129 { 130 PowerPCCPU *cpu = opaque; 131 132 cpu_reset(CPU(cpu)); 133 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 134 cpu->env.nip = PROM_ADDR + 0x100; 135 } 136 137 /* PowerPC Mac99 hardware initialisation */ 138 static void ppc_core99_init(MachineState *machine) 139 { 140 ram_addr_t ram_size = machine->ram_size; 141 const char *kernel_filename = machine->kernel_filename; 142 const char *kernel_cmdline = machine->kernel_cmdline; 143 const char *initrd_filename = machine->initrd_filename; 144 const char *boot_device = machine->boot_order; 145 PowerPCCPU *cpu = NULL; 146 CPUPPCState *env = NULL; 147 char *filename; 148 qemu_irq *pic, **openpic_irqs; 149 MemoryRegion *isa = g_new(MemoryRegion, 1); 150 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 151 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 152 int linux_boot, i, j, k; 153 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 154 hwaddr kernel_base, initrd_base, cmdline_base = 0; 155 long kernel_size, initrd_size; 156 PCIBus *pci_bus; 157 NewWorldMacIOState *macio; 158 MACIOIDEState *macio_ide; 159 BusState *adb_bus; 160 MacIONVRAMState *nvr; 161 int bios_size, ndrv_size; 162 uint8_t *ndrv_file; 163 int ppc_boot_device; 164 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 165 void *fw_cfg; 166 int machine_arch; 167 SysBusDevice *s; 168 DeviceState *dev, *pic_dev; 169 int *token = g_new(int, 1); 170 hwaddr nvram_addr = 0xFFF04000; 171 uint64_t tbfreq; 172 173 linux_boot = (kernel_filename != NULL); 174 175 /* init CPUs */ 176 for (i = 0; i < smp_cpus; i++) { 177 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 178 env = &cpu->env; 179 180 /* Set time-base frequency to 100 Mhz */ 181 cpu_ppc_tb_init(env, TBFREQ); 182 qemu_register_reset(ppc_core99_reset, cpu); 183 } 184 185 /* allocate RAM */ 186 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 187 memory_region_add_subregion(get_system_memory(), 0, ram); 188 189 /* allocate and load BIOS */ 190 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 191 &error_fatal); 192 193 if (bios_name == NULL) 194 bios_name = PROM_FILENAME; 195 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 196 memory_region_set_readonly(bios, true); 197 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 198 199 /* Load OpenBIOS (ELF) */ 200 if (filename) { 201 bios_size = load_elf(filename, NULL, NULL, NULL, 202 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 203 204 g_free(filename); 205 } else { 206 bios_size = -1; 207 } 208 if (bios_size < 0 || bios_size > BIOS_SIZE) { 209 error_report("could not load PowerPC bios '%s'", bios_name); 210 exit(1); 211 } 212 213 if (linux_boot) { 214 uint64_t lowaddr = 0; 215 int bswap_needed; 216 217 #ifdef BSWAP_NEEDED 218 bswap_needed = 1; 219 #else 220 bswap_needed = 0; 221 #endif 222 kernel_base = KERNEL_LOAD_ADDR; 223 224 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 225 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 226 0, 0); 227 if (kernel_size < 0) 228 kernel_size = load_aout(kernel_filename, kernel_base, 229 ram_size - kernel_base, bswap_needed, 230 TARGET_PAGE_SIZE); 231 if (kernel_size < 0) 232 kernel_size = load_image_targphys(kernel_filename, 233 kernel_base, 234 ram_size - kernel_base); 235 if (kernel_size < 0) { 236 error_report("could not load kernel '%s'", kernel_filename); 237 exit(1); 238 } 239 /* load initrd */ 240 if (initrd_filename) { 241 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 242 initrd_size = load_image_targphys(initrd_filename, initrd_base, 243 ram_size - initrd_base); 244 if (initrd_size < 0) { 245 error_report("could not load initial ram disk '%s'", 246 initrd_filename); 247 exit(1); 248 } 249 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 250 } else { 251 initrd_base = 0; 252 initrd_size = 0; 253 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 254 } 255 ppc_boot_device = 'm'; 256 } else { 257 kernel_base = 0; 258 kernel_size = 0; 259 initrd_base = 0; 260 initrd_size = 0; 261 ppc_boot_device = '\0'; 262 /* We consider that NewWorld PowerMac never have any floppy drive 263 * For now, OHW cannot boot from the network. 264 */ 265 for (i = 0; boot_device[i] != '\0'; i++) { 266 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 267 ppc_boot_device = boot_device[i]; 268 break; 269 } 270 } 271 if (ppc_boot_device == '\0') { 272 error_report("No valid boot device for Mac99 machine"); 273 exit(1); 274 } 275 } 276 277 /* Register 8 MB of ISA IO space */ 278 memory_region_init_alias(isa, NULL, "isa_mmio", 279 get_system_io(), 0, 0x00800000); 280 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 281 282 /* UniN init: XXX should be a real device */ 283 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 284 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 285 286 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 287 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 288 289 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 290 openpic_irqs[0] = 291 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 292 for (i = 0; i < smp_cpus; i++) { 293 /* Mac99 IRQ connection between OpenPIC outputs pins 294 * and PowerPC input pins 295 */ 296 switch (PPC_INPUT(env)) { 297 case PPC_FLAGS_INPUT_6xx: 298 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 299 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 300 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 301 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 302 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 303 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 304 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 305 /* Not connected ? */ 306 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 307 /* Check this */ 308 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 309 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 310 break; 311 #if defined(TARGET_PPC64) 312 case PPC_FLAGS_INPUT_970: 313 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 314 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 315 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 316 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 317 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 318 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 319 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 320 /* Not connected ? */ 321 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 322 /* Check this */ 323 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 324 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 325 break; 326 #endif /* defined(TARGET_PPC64) */ 327 default: 328 error_report("Bus model not supported on mac99 machine"); 329 exit(1); 330 } 331 } 332 333 pic = g_new0(qemu_irq, 64); 334 335 pic_dev = qdev_create(NULL, TYPE_OPENPIC); 336 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 337 qdev_init_nofail(pic_dev); 338 s = SYS_BUS_DEVICE(pic_dev); 339 k = 0; 340 for (i = 0; i < smp_cpus; i++) { 341 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 342 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 343 } 344 } 345 346 for (i = 0; i < 64; i++) { 347 pic[i] = qdev_get_gpio_in(pic_dev, i); 348 } 349 350 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 351 /* 970 gets a U3 bus */ 352 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 353 machine_arch = ARCH_MAC99_U3; 354 } else { 355 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 356 machine_arch = ARCH_MAC99; 357 } 358 object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort); 359 360 machine->usb |= defaults_enabled() && !machine->usb_disabled; 361 362 /* Timebase Frequency */ 363 if (kvm_enabled()) { 364 tbfreq = kvmppc_get_tbfreq(); 365 } else { 366 tbfreq = TBFREQ; 367 } 368 369 /* MacIO */ 370 macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO)); 371 dev = DEVICE(macio); 372 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 373 qdev_connect_gpio_out(dev, 1, pic[0x24]); /* ESCC-B */ 374 qdev_connect_gpio_out(dev, 2, pic[0x25]); /* ESCC-A */ 375 qdev_connect_gpio_out(dev, 3, pic[0x0d]); /* IDE */ 376 qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE DMA */ 377 qdev_connect_gpio_out(dev, 5, pic[0x0e]); /* IDE */ 378 qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE DMA */ 379 qdev_prop_set_uint64(dev, "frequency", tbfreq); 380 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 381 &error_abort); 382 qdev_init_nofail(dev); 383 384 /* We only emulate 2 out of 3 IDE controllers for now */ 385 ide_drive_get(hd, ARRAY_SIZE(hd)); 386 387 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 388 "ide[0]")); 389 macio_ide_init_drives(macio_ide, hd); 390 391 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 392 "ide[1]")); 393 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 394 395 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 396 adb_bus = qdev_get_child_bus(dev, "adb.0"); 397 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 398 qdev_init_nofail(dev); 399 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 400 qdev_init_nofail(dev); 401 402 if (machine->usb) { 403 pci_create_simple(pci_bus, -1, "pci-ohci"); 404 405 /* U3 needs to use USB for input because Linux doesn't support via-cuda 406 on PPC64 */ 407 if (machine_arch == ARCH_MAC99_U3) { 408 USBBus *usb_bus = usb_bus_find(-1); 409 410 usb_create_simple(usb_bus, "usb-kbd"); 411 usb_create_simple(usb_bus, "usb-mouse"); 412 } 413 } 414 415 pci_vga_init(pci_bus); 416 417 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 418 graphic_depth = 15; 419 } 420 421 for (i = 0; i < nb_nics; i++) { 422 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 423 } 424 425 /* The NewWorld NVRAM is not located in the MacIO device */ 426 #ifdef CONFIG_KVM 427 if (kvm_enabled() && getpagesize() > 4096) { 428 /* We can't combine read-write and read-only in a single page, so 429 move the NVRAM out of ROM again for KVM */ 430 nvram_addr = 0xFFE00000; 431 } 432 #endif 433 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 434 qdev_prop_set_uint32(dev, "size", 0x2000); 435 qdev_prop_set_uint32(dev, "it_shift", 1); 436 qdev_init_nofail(dev); 437 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 438 nvr = MACIO_NVRAM(dev); 439 pmac_format_nvram_partition(nvr, 0x2000); 440 /* No PCI init: the BIOS will do it */ 441 442 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 443 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 444 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 445 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 446 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 447 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 448 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 449 if (kernel_cmdline) { 450 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 451 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 452 } else { 453 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 454 } 455 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 456 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 457 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 458 459 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 460 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 461 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 462 463 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 464 if (kvm_enabled()) { 465 #ifdef CONFIG_KVM 466 uint8_t *hypercall; 467 468 hypercall = g_malloc(16); 469 kvmppc_get_hypercall(env, hypercall, 16); 470 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 471 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 472 #endif 473 } 474 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 475 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 476 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 477 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 478 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 479 480 /* MacOS NDRV VGA driver */ 481 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 482 if (filename) { 483 ndrv_size = get_image_size(filename); 484 if (ndrv_size != -1) { 485 ndrv_file = g_malloc(ndrv_size); 486 ndrv_size = load_image(filename, ndrv_file); 487 488 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 489 } 490 g_free(filename); 491 } 492 493 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 494 } 495 496 static int core99_kvm_type(const char *arg) 497 { 498 /* Always force PR KVM */ 499 return 2; 500 } 501 502 static void core99_machine_class_init(ObjectClass *oc, void *data) 503 { 504 MachineClass *mc = MACHINE_CLASS(oc); 505 506 mc->desc = "Mac99 based PowerMAC"; 507 mc->init = ppc_core99_init; 508 mc->block_default_type = IF_IDE; 509 mc->max_cpus = MAX_CPUS; 510 mc->default_boot_order = "cd"; 511 mc->kvm_type = core99_kvm_type; 512 #ifdef TARGET_PPC64 513 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 514 #else 515 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 516 #endif 517 } 518 519 static const TypeInfo core99_machine_info = { 520 .name = MACHINE_TYPE_NAME("mac99"), 521 .parent = TYPE_MACHINE, 522 .class_init = core99_machine_class_init, 523 }; 524 525 static void mac_machine_register_types(void) 526 { 527 type_register_static(&core99_machine_info); 528 } 529 530 type_init(mac_machine_register_types) 531