1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/ppc/openpic.h" 64 #include "hw/ide.h" 65 #include "hw/loader.h" 66 #include "elf.h" 67 #include "qemu/error-report.h" 68 #include "sysemu/kvm.h" 69 #include "kvm_ppc.h" 70 #include "hw/usb.h" 71 #include "sysemu/block-backend.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 75 #define MAX_IDE_BUS 2 76 #define CFG_ADDR 0xf0000510 77 #define TBFREQ (100UL * 1000UL * 1000UL) 78 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 79 #define BUSFREQ (100UL * 1000UL * 1000UL) 80 81 /* debug UniNorth */ 82 //#define DEBUG_UNIN 83 84 #ifdef DEBUG_UNIN 85 #define UNIN_DPRINTF(fmt, ...) \ 86 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 87 #else 88 #define UNIN_DPRINTF(fmt, ...) 89 #endif 90 91 /* UniN device */ 92 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 93 unsigned size) 94 { 95 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 96 if (addr == 0x0) { 97 *(int*)opaque = value; 98 } 99 } 100 101 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 102 { 103 uint32_t value; 104 105 value = 0; 106 switch (addr) { 107 case 0: 108 value = *(int*)opaque; 109 } 110 111 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 112 113 return value; 114 } 115 116 static const MemoryRegionOps unin_ops = { 117 .read = unin_read, 118 .write = unin_write, 119 .endianness = DEVICE_NATIVE_ENDIAN, 120 }; 121 122 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 123 Error **errp) 124 { 125 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 126 } 127 128 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 129 { 130 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 131 } 132 133 static hwaddr round_page(hwaddr addr) 134 { 135 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 136 } 137 138 static void ppc_core99_reset(void *opaque) 139 { 140 PowerPCCPU *cpu = opaque; 141 142 cpu_reset(CPU(cpu)); 143 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 144 cpu->env.nip = PROM_ADDR + 0x100; 145 } 146 147 /* PowerPC Mac99 hardware initialisation */ 148 static void ppc_core99_init(MachineState *machine) 149 { 150 ram_addr_t ram_size = machine->ram_size; 151 const char *kernel_filename = machine->kernel_filename; 152 const char *kernel_cmdline = machine->kernel_cmdline; 153 const char *initrd_filename = machine->initrd_filename; 154 const char *boot_device = machine->boot_order; 155 PowerPCCPU *cpu = NULL; 156 CPUPPCState *env = NULL; 157 char *filename; 158 qemu_irq *pic, **openpic_irqs; 159 MemoryRegion *isa = g_new(MemoryRegion, 1); 160 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 161 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 162 int linux_boot, i, j, k; 163 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 164 hwaddr kernel_base, initrd_base, cmdline_base = 0; 165 long kernel_size, initrd_size; 166 PCIBus *pci_bus; 167 PCIDevice *macio; 168 MACIOIDEState *macio_ide; 169 BusState *adb_bus; 170 MacIONVRAMState *nvr; 171 int bios_size; 172 MemoryRegion *pic_mem, *escc_mem; 173 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 174 int ppc_boot_device; 175 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 176 void *fw_cfg; 177 int machine_arch; 178 SysBusDevice *s; 179 DeviceState *dev; 180 int *token = g_new(int, 1); 181 hwaddr nvram_addr = 0xFFF04000; 182 uint64_t tbfreq; 183 184 linux_boot = (kernel_filename != NULL); 185 186 /* init CPUs */ 187 if (machine->cpu_model == NULL) { 188 #ifdef TARGET_PPC64 189 machine->cpu_model = "970fx"; 190 #else 191 machine->cpu_model = "G4"; 192 #endif 193 } 194 for (i = 0; i < smp_cpus; i++) { 195 cpu = cpu_ppc_init(machine->cpu_model); 196 if (cpu == NULL) { 197 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 198 exit(1); 199 } 200 env = &cpu->env; 201 202 /* Set time-base frequency to 100 Mhz */ 203 cpu_ppc_tb_init(env, TBFREQ); 204 qemu_register_reset(ppc_core99_reset, cpu); 205 } 206 207 /* allocate RAM */ 208 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 209 memory_region_add_subregion(get_system_memory(), 0, ram); 210 211 /* allocate and load BIOS */ 212 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 213 &error_fatal); 214 vmstate_register_ram_global(bios); 215 216 if (bios_name == NULL) 217 bios_name = PROM_FILENAME; 218 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 219 memory_region_set_readonly(bios, true); 220 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 221 222 /* Load OpenBIOS (ELF) */ 223 if (filename) { 224 bios_size = load_elf(filename, NULL, NULL, NULL, 225 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 226 227 g_free(filename); 228 } else { 229 bios_size = -1; 230 } 231 if (bios_size < 0 || bios_size > BIOS_SIZE) { 232 error_report("could not load PowerPC bios '%s'", bios_name); 233 exit(1); 234 } 235 236 if (linux_boot) { 237 uint64_t lowaddr = 0; 238 int bswap_needed; 239 240 #ifdef BSWAP_NEEDED 241 bswap_needed = 1; 242 #else 243 bswap_needed = 0; 244 #endif 245 kernel_base = KERNEL_LOAD_ADDR; 246 247 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 248 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 249 0, 0); 250 if (kernel_size < 0) 251 kernel_size = load_aout(kernel_filename, kernel_base, 252 ram_size - kernel_base, bswap_needed, 253 TARGET_PAGE_SIZE); 254 if (kernel_size < 0) 255 kernel_size = load_image_targphys(kernel_filename, 256 kernel_base, 257 ram_size - kernel_base); 258 if (kernel_size < 0) { 259 error_report("could not load kernel '%s'", kernel_filename); 260 exit(1); 261 } 262 /* load initrd */ 263 if (initrd_filename) { 264 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 265 initrd_size = load_image_targphys(initrd_filename, initrd_base, 266 ram_size - initrd_base); 267 if (initrd_size < 0) { 268 error_report("could not load initial ram disk '%s'", 269 initrd_filename); 270 exit(1); 271 } 272 cmdline_base = round_page(initrd_base + initrd_size); 273 } else { 274 initrd_base = 0; 275 initrd_size = 0; 276 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 277 } 278 ppc_boot_device = 'm'; 279 } else { 280 kernel_base = 0; 281 kernel_size = 0; 282 initrd_base = 0; 283 initrd_size = 0; 284 ppc_boot_device = '\0'; 285 /* We consider that NewWorld PowerMac never have any floppy drive 286 * For now, OHW cannot boot from the network. 287 */ 288 for (i = 0; boot_device[i] != '\0'; i++) { 289 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 290 ppc_boot_device = boot_device[i]; 291 break; 292 } 293 } 294 if (ppc_boot_device == '\0') { 295 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 296 exit(1); 297 } 298 } 299 300 /* Register 8 MB of ISA IO space */ 301 memory_region_init_alias(isa, NULL, "isa_mmio", 302 get_system_io(), 0, 0x00800000); 303 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 304 305 /* UniN init: XXX should be a real device */ 306 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 307 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 308 309 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 310 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 311 312 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 313 openpic_irqs[0] = 314 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 315 for (i = 0; i < smp_cpus; i++) { 316 /* Mac99 IRQ connection between OpenPIC outputs pins 317 * and PowerPC input pins 318 */ 319 switch (PPC_INPUT(env)) { 320 case PPC_FLAGS_INPUT_6xx: 321 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 322 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 323 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 324 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 325 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 326 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 327 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 328 /* Not connected ? */ 329 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 330 /* Check this */ 331 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 332 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 333 break; 334 #if defined(TARGET_PPC64) 335 case PPC_FLAGS_INPUT_970: 336 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 337 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 338 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 339 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 340 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 341 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 342 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 343 /* Not connected ? */ 344 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 345 /* Check this */ 346 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 347 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 348 break; 349 #endif /* defined(TARGET_PPC64) */ 350 default: 351 error_report("Bus model not supported on mac99 machine"); 352 exit(1); 353 } 354 } 355 356 pic = g_new0(qemu_irq, 64); 357 358 dev = qdev_create(NULL, TYPE_OPENPIC); 359 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 360 qdev_init_nofail(dev); 361 s = SYS_BUS_DEVICE(dev); 362 pic_mem = s->mmio[0].memory; 363 k = 0; 364 for (i = 0; i < smp_cpus; i++) { 365 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 366 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 367 } 368 } 369 370 for (i = 0; i < 64; i++) { 371 pic[i] = qdev_get_gpio_in(dev, i); 372 } 373 374 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 375 /* 970 gets a U3 bus */ 376 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 377 machine_arch = ARCH_MAC99_U3; 378 } else { 379 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 380 machine_arch = ARCH_MAC99; 381 } 382 383 machine->usb |= defaults_enabled() && !machine->usb_disabled; 384 385 /* Timebase Frequency */ 386 if (kvm_enabled()) { 387 tbfreq = kvmppc_get_tbfreq(); 388 } else { 389 tbfreq = TBFREQ; 390 } 391 392 /* init basic PC hardware */ 393 escc_mem = escc_init(0, pic[0x25], pic[0x24], 394 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 395 memory_region_init_alias(escc_bar, NULL, "escc-bar", 396 escc_mem, 0, memory_region_size(escc_mem)); 397 398 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 399 dev = DEVICE(macio); 400 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 401 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 402 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 403 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 404 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 405 qdev_prop_set_uint64(dev, "frequency", tbfreq); 406 macio_init(macio, pic_mem, escc_bar); 407 408 /* We only emulate 2 out of 3 IDE controllers for now */ 409 ide_drive_get(hd, ARRAY_SIZE(hd)); 410 411 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 412 "ide[0]")); 413 macio_ide_init_drives(macio_ide, hd); 414 415 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 416 "ide[1]")); 417 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 418 419 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 420 adb_bus = qdev_get_child_bus(dev, "adb.0"); 421 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 422 qdev_init_nofail(dev); 423 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 424 qdev_init_nofail(dev); 425 426 if (machine->usb) { 427 pci_create_simple(pci_bus, -1, "pci-ohci"); 428 429 /* U3 needs to use USB for input because Linux doesn't support via-cuda 430 on PPC64 */ 431 if (machine_arch == ARCH_MAC99_U3) { 432 USBBus *usb_bus = usb_bus_find(-1); 433 434 usb_create_simple(usb_bus, "usb-kbd"); 435 usb_create_simple(usb_bus, "usb-mouse"); 436 } 437 } 438 439 pci_vga_init(pci_bus); 440 441 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 442 graphic_depth = 15; 443 } 444 445 for (i = 0; i < nb_nics; i++) { 446 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 447 } 448 449 /* The NewWorld NVRAM is not located in the MacIO device */ 450 #ifdef CONFIG_KVM 451 if (kvm_enabled() && getpagesize() > 4096) { 452 /* We can't combine read-write and read-only in a single page, so 453 move the NVRAM out of ROM again for KVM */ 454 nvram_addr = 0xFFE00000; 455 } 456 #endif 457 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 458 qdev_prop_set_uint32(dev, "size", 0x2000); 459 qdev_prop_set_uint32(dev, "it_shift", 1); 460 qdev_init_nofail(dev); 461 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 462 nvr = MACIO_NVRAM(dev); 463 pmac_format_nvram_partition(nvr, 0x2000); 464 /* No PCI init: the BIOS will do it */ 465 466 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 467 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 468 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 469 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 470 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 471 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 472 if (kernel_cmdline) { 473 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 474 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 475 } else { 476 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 477 } 478 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 479 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 480 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 481 482 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 484 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 485 486 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 487 if (kvm_enabled()) { 488 #ifdef CONFIG_KVM 489 uint8_t *hypercall; 490 491 hypercall = g_malloc(16); 492 kvmppc_get_hypercall(env, hypercall, 16); 493 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 495 #endif 496 } 497 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 498 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 499 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 501 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 502 503 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 504 } 505 506 static int core99_kvm_type(const char *arg) 507 { 508 /* Always force PR KVM */ 509 return 2; 510 } 511 512 static void core99_machine_class_init(ObjectClass *oc, void *data) 513 { 514 MachineClass *mc = MACHINE_CLASS(oc); 515 516 mc->desc = "Mac99 based PowerMAC"; 517 mc->init = ppc_core99_init; 518 mc->max_cpus = MAX_CPUS; 519 mc->default_boot_order = "cd"; 520 mc->kvm_type = core99_kvm_type; 521 } 522 523 static const TypeInfo core99_machine_info = { 524 .name = MACHINE_TYPE_NAME("mac99"), 525 .parent = TYPE_MACHINE, 526 .class_init = core99_machine_class_init, 527 }; 528 529 static void mac_machine_register_types(void) 530 { 531 type_register_static(&core99_machine_info); 532 } 533 534 type_init(mac_machine_register_types) 535