1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "hw/hw.h" 51 #include "hw/ppc/ppc.h" 52 #include "hw/ppc/mac.h" 53 #include "hw/input/adb.h" 54 #include "hw/ppc/mac_dbdma.h" 55 #include "hw/timer/m48t59.h" 56 #include "hw/pci/pci.h" 57 #include "net/net.h" 58 #include "sysemu/sysemu.h" 59 #include "hw/boards.h" 60 #include "hw/nvram/fw_cfg.h" 61 #include "hw/char/escc.h" 62 #include "hw/ppc/openpic.h" 63 #include "hw/ide.h" 64 #include "hw/loader.h" 65 #include "elf.h" 66 #include "qemu/error-report.h" 67 #include "sysemu/kvm.h" 68 #include "kvm_ppc.h" 69 #include "hw/usb.h" 70 #include "sysemu/block-backend.h" 71 #include "exec/address-spaces.h" 72 #include "hw/sysbus.h" 73 74 #define MAX_IDE_BUS 2 75 #define CFG_ADDR 0xf0000510 76 #define TBFREQ (100UL * 1000UL * 1000UL) 77 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 78 #define BUSFREQ (100UL * 1000UL * 1000UL) 79 80 /* debug UniNorth */ 81 //#define DEBUG_UNIN 82 83 #ifdef DEBUG_UNIN 84 #define UNIN_DPRINTF(fmt, ...) \ 85 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 86 #else 87 #define UNIN_DPRINTF(fmt, ...) 88 #endif 89 90 /* UniN device */ 91 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 92 unsigned size) 93 { 94 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 95 if (addr == 0x0) { 96 *(int*)opaque = value; 97 } 98 } 99 100 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 101 { 102 uint32_t value; 103 104 value = 0; 105 switch (addr) { 106 case 0: 107 value = *(int*)opaque; 108 } 109 110 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 111 112 return value; 113 } 114 115 static const MemoryRegionOps unin_ops = { 116 .read = unin_read, 117 .write = unin_write, 118 .endianness = DEVICE_NATIVE_ENDIAN, 119 }; 120 121 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 122 Error **errp) 123 { 124 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 125 } 126 127 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 128 { 129 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 130 } 131 132 static hwaddr round_page(hwaddr addr) 133 { 134 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 135 } 136 137 static void ppc_core99_reset(void *opaque) 138 { 139 PowerPCCPU *cpu = opaque; 140 141 cpu_reset(CPU(cpu)); 142 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 143 cpu->env.nip = PROM_ADDR + 0x100; 144 } 145 146 /* PowerPC Mac99 hardware initialisation */ 147 static void ppc_core99_init(MachineState *machine) 148 { 149 ram_addr_t ram_size = machine->ram_size; 150 const char *kernel_filename = machine->kernel_filename; 151 const char *kernel_cmdline = machine->kernel_cmdline; 152 const char *initrd_filename = machine->initrd_filename; 153 const char *boot_device = machine->boot_order; 154 PowerPCCPU *cpu = NULL; 155 CPUPPCState *env = NULL; 156 char *filename; 157 qemu_irq *pic, **openpic_irqs; 158 MemoryRegion *isa = g_new(MemoryRegion, 1); 159 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 160 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 161 int linux_boot, i, j, k; 162 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 163 hwaddr kernel_base, initrd_base, cmdline_base = 0; 164 long kernel_size, initrd_size; 165 PCIBus *pci_bus; 166 PCIDevice *macio; 167 MACIOIDEState *macio_ide; 168 BusState *adb_bus; 169 MacIONVRAMState *nvr; 170 int bios_size; 171 MemoryRegion *pic_mem, *escc_mem; 172 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 173 int ppc_boot_device; 174 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 175 void *fw_cfg; 176 int machine_arch; 177 SysBusDevice *s; 178 DeviceState *dev; 179 int *token = g_new(int, 1); 180 hwaddr nvram_addr = 0xFFF04000; 181 uint64_t tbfreq; 182 183 linux_boot = (kernel_filename != NULL); 184 185 /* init CPUs */ 186 if (machine->cpu_model == NULL) { 187 #ifdef TARGET_PPC64 188 machine->cpu_model = "970fx"; 189 #else 190 machine->cpu_model = "G4"; 191 #endif 192 } 193 for (i = 0; i < smp_cpus; i++) { 194 cpu = cpu_ppc_init(machine->cpu_model); 195 if (cpu == NULL) { 196 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 197 exit(1); 198 } 199 env = &cpu->env; 200 201 /* Set time-base frequency to 100 Mhz */ 202 cpu_ppc_tb_init(env, TBFREQ); 203 qemu_register_reset(ppc_core99_reset, cpu); 204 } 205 206 /* allocate RAM */ 207 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 208 memory_region_add_subregion(get_system_memory(), 0, ram); 209 210 /* allocate and load BIOS */ 211 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 212 &error_fatal); 213 vmstate_register_ram_global(bios); 214 215 if (bios_name == NULL) 216 bios_name = PROM_FILENAME; 217 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 218 memory_region_set_readonly(bios, true); 219 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 220 221 /* Load OpenBIOS (ELF) */ 222 if (filename) { 223 bios_size = load_elf(filename, NULL, NULL, NULL, 224 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 225 226 g_free(filename); 227 } else { 228 bios_size = -1; 229 } 230 if (bios_size < 0 || bios_size > BIOS_SIZE) { 231 error_report("could not load PowerPC bios '%s'", bios_name); 232 exit(1); 233 } 234 235 if (linux_boot) { 236 uint64_t lowaddr = 0; 237 int bswap_needed; 238 239 #ifdef BSWAP_NEEDED 240 bswap_needed = 1; 241 #else 242 bswap_needed = 0; 243 #endif 244 kernel_base = KERNEL_LOAD_ADDR; 245 246 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 247 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 248 0, 0); 249 if (kernel_size < 0) 250 kernel_size = load_aout(kernel_filename, kernel_base, 251 ram_size - kernel_base, bswap_needed, 252 TARGET_PAGE_SIZE); 253 if (kernel_size < 0) 254 kernel_size = load_image_targphys(kernel_filename, 255 kernel_base, 256 ram_size - kernel_base); 257 if (kernel_size < 0) { 258 error_report("could not load kernel '%s'", kernel_filename); 259 exit(1); 260 } 261 /* load initrd */ 262 if (initrd_filename) { 263 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 264 initrd_size = load_image_targphys(initrd_filename, initrd_base, 265 ram_size - initrd_base); 266 if (initrd_size < 0) { 267 error_report("could not load initial ram disk '%s'", 268 initrd_filename); 269 exit(1); 270 } 271 cmdline_base = round_page(initrd_base + initrd_size); 272 } else { 273 initrd_base = 0; 274 initrd_size = 0; 275 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 276 } 277 ppc_boot_device = 'm'; 278 } else { 279 kernel_base = 0; 280 kernel_size = 0; 281 initrd_base = 0; 282 initrd_size = 0; 283 ppc_boot_device = '\0'; 284 /* We consider that NewWorld PowerMac never have any floppy drive 285 * For now, OHW cannot boot from the network. 286 */ 287 for (i = 0; boot_device[i] != '\0'; i++) { 288 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 289 ppc_boot_device = boot_device[i]; 290 break; 291 } 292 } 293 if (ppc_boot_device == '\0') { 294 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 295 exit(1); 296 } 297 } 298 299 /* Register 8 MB of ISA IO space */ 300 memory_region_init_alias(isa, NULL, "isa_mmio", 301 get_system_io(), 0, 0x00800000); 302 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 303 304 /* UniN init: XXX should be a real device */ 305 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 306 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 307 308 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 309 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 310 311 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 312 openpic_irqs[0] = 313 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 314 for (i = 0; i < smp_cpus; i++) { 315 /* Mac99 IRQ connection between OpenPIC outputs pins 316 * and PowerPC input pins 317 */ 318 switch (PPC_INPUT(env)) { 319 case PPC_FLAGS_INPUT_6xx: 320 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 321 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 322 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 323 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 324 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 325 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 326 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 327 /* Not connected ? */ 328 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 329 /* Check this */ 330 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 331 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 332 break; 333 #if defined(TARGET_PPC64) 334 case PPC_FLAGS_INPUT_970: 335 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 336 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 337 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 338 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 339 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 340 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 341 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 342 /* Not connected ? */ 343 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 344 /* Check this */ 345 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 346 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 347 break; 348 #endif /* defined(TARGET_PPC64) */ 349 default: 350 error_report("Bus model not supported on mac99 machine"); 351 exit(1); 352 } 353 } 354 355 pic = g_new0(qemu_irq, 64); 356 357 dev = qdev_create(NULL, TYPE_OPENPIC); 358 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 359 qdev_init_nofail(dev); 360 s = SYS_BUS_DEVICE(dev); 361 pic_mem = s->mmio[0].memory; 362 k = 0; 363 for (i = 0; i < smp_cpus; i++) { 364 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 365 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 366 } 367 } 368 369 for (i = 0; i < 64; i++) { 370 pic[i] = qdev_get_gpio_in(dev, i); 371 } 372 373 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 374 /* 970 gets a U3 bus */ 375 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 376 machine_arch = ARCH_MAC99_U3; 377 } else { 378 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 379 machine_arch = ARCH_MAC99; 380 } 381 382 machine->usb |= defaults_enabled() && !machine->usb_disabled; 383 384 /* Timebase Frequency */ 385 if (kvm_enabled()) { 386 tbfreq = kvmppc_get_tbfreq(); 387 } else { 388 tbfreq = TBFREQ; 389 } 390 391 /* init basic PC hardware */ 392 escc_mem = escc_init(0, pic[0x25], pic[0x24], 393 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 394 memory_region_init_alias(escc_bar, NULL, "escc-bar", 395 escc_mem, 0, memory_region_size(escc_mem)); 396 397 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 398 dev = DEVICE(macio); 399 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 400 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 401 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 402 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 403 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 404 qdev_prop_set_uint64(dev, "frequency", tbfreq); 405 macio_init(macio, pic_mem, escc_bar); 406 407 /* We only emulate 2 out of 3 IDE controllers for now */ 408 ide_drive_get(hd, ARRAY_SIZE(hd)); 409 410 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 411 "ide[0]")); 412 macio_ide_init_drives(macio_ide, hd); 413 414 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 415 "ide[1]")); 416 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 417 418 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 419 adb_bus = qdev_get_child_bus(dev, "adb.0"); 420 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 421 qdev_init_nofail(dev); 422 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 423 qdev_init_nofail(dev); 424 425 if (machine->usb) { 426 pci_create_simple(pci_bus, -1, "pci-ohci"); 427 428 /* U3 needs to use USB for input because Linux doesn't support via-cuda 429 on PPC64 */ 430 if (machine_arch == ARCH_MAC99_U3) { 431 USBBus *usb_bus = usb_bus_find(-1); 432 433 usb_create_simple(usb_bus, "usb-kbd"); 434 usb_create_simple(usb_bus, "usb-mouse"); 435 } 436 } 437 438 pci_vga_init(pci_bus); 439 440 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 441 graphic_depth = 15; 442 } 443 444 for (i = 0; i < nb_nics; i++) { 445 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 446 } 447 448 /* The NewWorld NVRAM is not located in the MacIO device */ 449 #ifdef CONFIG_KVM 450 if (kvm_enabled() && getpagesize() > 4096) { 451 /* We can't combine read-write and read-only in a single page, so 452 move the NVRAM out of ROM again for KVM */ 453 nvram_addr = 0xFFE00000; 454 } 455 #endif 456 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 457 qdev_prop_set_uint32(dev, "size", 0x2000); 458 qdev_prop_set_uint32(dev, "it_shift", 1); 459 qdev_init_nofail(dev); 460 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 461 nvr = MACIO_NVRAM(dev); 462 pmac_format_nvram_partition(nvr, 0x2000); 463 /* No PCI init: the BIOS will do it */ 464 465 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 466 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 467 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 468 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 469 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 470 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 471 if (kernel_cmdline) { 472 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 473 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 474 } else { 475 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 476 } 477 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 478 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 479 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 480 481 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 482 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 484 485 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 486 if (kvm_enabled()) { 487 #ifdef CONFIG_KVM 488 uint8_t *hypercall; 489 490 hypercall = g_malloc(16); 491 kvmppc_get_hypercall(env, hypercall, 16); 492 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 493 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 494 #endif 495 } 496 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 497 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 498 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 499 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 501 502 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 503 } 504 505 static int core99_kvm_type(const char *arg) 506 { 507 /* Always force PR KVM */ 508 return 2; 509 } 510 511 static void core99_machine_class_init(ObjectClass *oc, void *data) 512 { 513 MachineClass *mc = MACHINE_CLASS(oc); 514 515 mc->desc = "Mac99 based PowerMAC"; 516 mc->init = ppc_core99_init; 517 mc->max_cpus = MAX_CPUS; 518 mc->default_boot_order = "cd"; 519 mc->kvm_type = core99_kvm_type; 520 } 521 522 static const TypeInfo core99_machine_info = { 523 .name = MACHINE_TYPE_NAME("mac99"), 524 .parent = TYPE_MACHINE, 525 .class_init = core99_machine_class_init, 526 }; 527 528 static void mac_machine_register_types(void) 529 { 530 type_register_static(&core99_machine_info); 531 } 532 533 type_init(mac_machine_register_types) 534