1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/misc/macio/macio.h" 64 #include "hw/ppc/openpic.h" 65 #include "hw/ide.h" 66 #include "hw/loader.h" 67 #include "elf.h" 68 #include "qemu/error-report.h" 69 #include "sysemu/kvm.h" 70 #include "kvm_ppc.h" 71 #include "hw/usb.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 #include "qemu/cutils.h" 75 #include "trace.h" 76 77 #define MAX_IDE_BUS 2 78 #define CFG_ADDR 0xf0000510 79 #define TBFREQ (100UL * 1000UL * 1000UL) 80 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 81 #define BUSFREQ (100UL * 1000UL * 1000UL) 82 83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 84 85 /* UniN device */ 86 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 87 unsigned size) 88 { 89 trace_mac99_uninorth_write(addr, value); 90 if (addr == 0x0) { 91 *(int*)opaque = value; 92 } 93 } 94 95 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 96 { 97 uint32_t value; 98 99 value = 0; 100 switch (addr) { 101 case 0: 102 value = *(int*)opaque; 103 } 104 105 trace_mac99_uninorth_read(addr, value); 106 107 return value; 108 } 109 110 static const MemoryRegionOps unin_ops = { 111 .read = unin_read, 112 .write = unin_write, 113 .endianness = DEVICE_NATIVE_ENDIAN, 114 }; 115 116 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 117 Error **errp) 118 { 119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 120 } 121 122 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 123 { 124 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 125 } 126 127 static void ppc_core99_reset(void *opaque) 128 { 129 PowerPCCPU *cpu = opaque; 130 131 cpu_reset(CPU(cpu)); 132 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 133 cpu->env.nip = PROM_ADDR + 0x100; 134 } 135 136 /* PowerPC Mac99 hardware initialisation */ 137 static void ppc_core99_init(MachineState *machine) 138 { 139 ram_addr_t ram_size = machine->ram_size; 140 const char *kernel_filename = machine->kernel_filename; 141 const char *kernel_cmdline = machine->kernel_cmdline; 142 const char *initrd_filename = machine->initrd_filename; 143 const char *boot_device = machine->boot_order; 144 PowerPCCPU *cpu = NULL; 145 CPUPPCState *env = NULL; 146 char *filename; 147 qemu_irq *pic, **openpic_irqs; 148 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 149 int linux_boot, i, j, k; 150 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 151 hwaddr kernel_base, initrd_base, cmdline_base = 0; 152 long kernel_size, initrd_size; 153 UNINHostState *uninorth_pci; 154 PCIBus *pci_bus; 155 NewWorldMacIOState *macio; 156 MACIOIDEState *macio_ide; 157 BusState *adb_bus; 158 MacIONVRAMState *nvr; 159 int bios_size, ndrv_size; 160 uint8_t *ndrv_file; 161 int ppc_boot_device; 162 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 163 void *fw_cfg; 164 int machine_arch; 165 SysBusDevice *s; 166 DeviceState *dev, *pic_dev; 167 int *token = g_new(int, 1); 168 hwaddr nvram_addr = 0xFFF04000; 169 uint64_t tbfreq; 170 171 linux_boot = (kernel_filename != NULL); 172 173 /* init CPUs */ 174 for (i = 0; i < smp_cpus; i++) { 175 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 176 env = &cpu->env; 177 178 /* Set time-base frequency to 100 Mhz */ 179 cpu_ppc_tb_init(env, TBFREQ); 180 qemu_register_reset(ppc_core99_reset, cpu); 181 } 182 183 /* allocate RAM */ 184 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 185 memory_region_add_subregion(get_system_memory(), 0, ram); 186 187 /* allocate and load BIOS */ 188 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 189 &error_fatal); 190 191 if (bios_name == NULL) 192 bios_name = PROM_FILENAME; 193 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 194 memory_region_set_readonly(bios, true); 195 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 196 197 /* Load OpenBIOS (ELF) */ 198 if (filename) { 199 bios_size = load_elf(filename, NULL, NULL, NULL, 200 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 201 202 g_free(filename); 203 } else { 204 bios_size = -1; 205 } 206 if (bios_size < 0 || bios_size > BIOS_SIZE) { 207 error_report("could not load PowerPC bios '%s'", bios_name); 208 exit(1); 209 } 210 211 if (linux_boot) { 212 uint64_t lowaddr = 0; 213 int bswap_needed; 214 215 #ifdef BSWAP_NEEDED 216 bswap_needed = 1; 217 #else 218 bswap_needed = 0; 219 #endif 220 kernel_base = KERNEL_LOAD_ADDR; 221 222 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 223 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 224 0, 0); 225 if (kernel_size < 0) 226 kernel_size = load_aout(kernel_filename, kernel_base, 227 ram_size - kernel_base, bswap_needed, 228 TARGET_PAGE_SIZE); 229 if (kernel_size < 0) 230 kernel_size = load_image_targphys(kernel_filename, 231 kernel_base, 232 ram_size - kernel_base); 233 if (kernel_size < 0) { 234 error_report("could not load kernel '%s'", kernel_filename); 235 exit(1); 236 } 237 /* load initrd */ 238 if (initrd_filename) { 239 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 240 initrd_size = load_image_targphys(initrd_filename, initrd_base, 241 ram_size - initrd_base); 242 if (initrd_size < 0) { 243 error_report("could not load initial ram disk '%s'", 244 initrd_filename); 245 exit(1); 246 } 247 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 248 } else { 249 initrd_base = 0; 250 initrd_size = 0; 251 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 252 } 253 ppc_boot_device = 'm'; 254 } else { 255 kernel_base = 0; 256 kernel_size = 0; 257 initrd_base = 0; 258 initrd_size = 0; 259 ppc_boot_device = '\0'; 260 /* We consider that NewWorld PowerMac never have any floppy drive 261 * For now, OHW cannot boot from the network. 262 */ 263 for (i = 0; boot_device[i] != '\0'; i++) { 264 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 265 ppc_boot_device = boot_device[i]; 266 break; 267 } 268 } 269 if (ppc_boot_device == '\0') { 270 error_report("No valid boot device for Mac99 machine"); 271 exit(1); 272 } 273 } 274 275 /* UniN init: XXX should be a real device */ 276 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 277 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 278 279 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 280 openpic_irqs[0] = 281 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 282 for (i = 0; i < smp_cpus; i++) { 283 /* Mac99 IRQ connection between OpenPIC outputs pins 284 * and PowerPC input pins 285 */ 286 switch (PPC_INPUT(env)) { 287 case PPC_FLAGS_INPUT_6xx: 288 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 289 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 290 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 291 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 292 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 293 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 294 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 295 /* Not connected ? */ 296 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 297 /* Check this */ 298 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 299 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 300 break; 301 #if defined(TARGET_PPC64) 302 case PPC_FLAGS_INPUT_970: 303 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 304 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 305 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 306 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 307 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 308 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 309 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 310 /* Not connected ? */ 311 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 312 /* Check this */ 313 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 314 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 315 break; 316 #endif /* defined(TARGET_PPC64) */ 317 default: 318 error_report("Bus model not supported on mac99 machine"); 319 exit(1); 320 } 321 } 322 323 pic = g_new0(qemu_irq, 64); 324 325 pic_dev = qdev_create(NULL, TYPE_OPENPIC); 326 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 327 qdev_init_nofail(pic_dev); 328 s = SYS_BUS_DEVICE(pic_dev); 329 k = 0; 330 for (i = 0; i < smp_cpus; i++) { 331 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 332 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 333 } 334 } 335 336 for (i = 0; i < 64; i++) { 337 pic[i] = qdev_get_gpio_in(pic_dev, i); 338 } 339 340 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 341 /* 970 gets a U3 bus */ 342 /* Uninorth AGP bus */ 343 dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); 344 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 345 &error_abort); 346 qdev_init_nofail(dev); 347 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 348 s = SYS_BUS_DEVICE(dev); 349 /* PCI hole */ 350 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 351 sysbus_mmio_get_region(s, 2)); 352 /* Register 8 MB of ISA IO space */ 353 memory_region_add_subregion(get_system_memory(), 0xf2000000, 354 sysbus_mmio_get_region(s, 3)); 355 sysbus_mmio_map(s, 0, 0xf0800000); 356 sysbus_mmio_map(s, 1, 0xf0c00000); 357 358 machine_arch = ARCH_MAC99_U3; 359 } else { 360 /* Use values found on a real PowerMac */ 361 /* Uninorth AGP bus */ 362 dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 363 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 364 &error_abort); 365 qdev_init_nofail(dev); 366 s = SYS_BUS_DEVICE(dev); 367 sysbus_mmio_map(s, 0, 0xf0800000); 368 sysbus_mmio_map(s, 1, 0xf0c00000); 369 370 /* Uninorth internal bus */ 371 dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 372 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 373 &error_abort); 374 qdev_init_nofail(dev); 375 s = SYS_BUS_DEVICE(dev); 376 sysbus_mmio_map(s, 0, 0xf4800000); 377 sysbus_mmio_map(s, 1, 0xf4c00000); 378 379 /* Uninorth main bus */ 380 dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 381 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 382 &error_abort); 383 qdev_init_nofail(dev); 384 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 385 s = SYS_BUS_DEVICE(dev); 386 /* PCI hole */ 387 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 388 sysbus_mmio_get_region(s, 2)); 389 /* Register 8 MB of ISA IO space */ 390 memory_region_add_subregion(get_system_memory(), 0xf2000000, 391 sysbus_mmio_get_region(s, 3)); 392 sysbus_mmio_map(s, 0, 0xf2800000); 393 sysbus_mmio_map(s, 1, 0xf2c00000); 394 395 machine_arch = ARCH_MAC99; 396 } 397 398 machine->usb |= defaults_enabled() && !machine->usb_disabled; 399 400 /* Timebase Frequency */ 401 if (kvm_enabled()) { 402 tbfreq = kvmppc_get_tbfreq(); 403 } else { 404 tbfreq = TBFREQ; 405 } 406 407 /* init basic PC hardware */ 408 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 409 410 /* MacIO */ 411 macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO)); 412 dev = DEVICE(macio); 413 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 414 qdev_connect_gpio_out(dev, 1, pic[0x24]); /* ESCC-B */ 415 qdev_connect_gpio_out(dev, 2, pic[0x25]); /* ESCC-A */ 416 qdev_connect_gpio_out(dev, 3, pic[0x0d]); /* IDE */ 417 qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE DMA */ 418 qdev_connect_gpio_out(dev, 5, pic[0x0e]); /* IDE */ 419 qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE DMA */ 420 qdev_prop_set_uint64(dev, "frequency", tbfreq); 421 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 422 &error_abort); 423 qdev_init_nofail(dev); 424 425 /* We only emulate 2 out of 3 IDE controllers for now */ 426 ide_drive_get(hd, ARRAY_SIZE(hd)); 427 428 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 429 "ide[0]")); 430 macio_ide_init_drives(macio_ide, hd); 431 432 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 433 "ide[1]")); 434 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 435 436 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 437 adb_bus = qdev_get_child_bus(dev, "adb.0"); 438 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 439 qdev_init_nofail(dev); 440 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 441 qdev_init_nofail(dev); 442 443 if (machine->usb) { 444 pci_create_simple(pci_bus, -1, "pci-ohci"); 445 446 /* U3 needs to use USB for input because Linux doesn't support via-cuda 447 on PPC64 */ 448 if (machine_arch == ARCH_MAC99_U3) { 449 USBBus *usb_bus = usb_bus_find(-1); 450 451 usb_create_simple(usb_bus, "usb-kbd"); 452 usb_create_simple(usb_bus, "usb-mouse"); 453 } 454 } 455 456 pci_vga_init(pci_bus); 457 458 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 459 graphic_depth = 15; 460 } 461 462 for (i = 0; i < nb_nics; i++) { 463 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 464 } 465 466 /* The NewWorld NVRAM is not located in the MacIO device */ 467 #ifdef CONFIG_KVM 468 if (kvm_enabled() && getpagesize() > 4096) { 469 /* We can't combine read-write and read-only in a single page, so 470 move the NVRAM out of ROM again for KVM */ 471 nvram_addr = 0xFFE00000; 472 } 473 #endif 474 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 475 qdev_prop_set_uint32(dev, "size", 0x2000); 476 qdev_prop_set_uint32(dev, "it_shift", 1); 477 qdev_init_nofail(dev); 478 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 479 nvr = MACIO_NVRAM(dev); 480 pmac_format_nvram_partition(nvr, 0x2000); 481 /* No PCI init: the BIOS will do it */ 482 483 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 484 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 485 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 486 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 487 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 488 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 489 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 490 if (kernel_cmdline) { 491 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 492 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 493 } else { 494 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 495 } 496 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 497 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 498 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 499 500 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 501 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 502 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 503 504 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 505 if (kvm_enabled()) { 506 #ifdef CONFIG_KVM 507 uint8_t *hypercall; 508 509 hypercall = g_malloc(16); 510 kvmppc_get_hypercall(env, hypercall, 16); 511 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 512 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 513 #endif 514 } 515 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 516 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 517 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 518 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 519 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 520 521 /* MacOS NDRV VGA driver */ 522 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 523 if (filename) { 524 ndrv_size = get_image_size(filename); 525 if (ndrv_size != -1) { 526 ndrv_file = g_malloc(ndrv_size); 527 ndrv_size = load_image(filename, ndrv_file); 528 529 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 530 } 531 g_free(filename); 532 } 533 534 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 535 } 536 537 static int core99_kvm_type(const char *arg) 538 { 539 /* Always force PR KVM */ 540 return 2; 541 } 542 543 static void core99_machine_class_init(ObjectClass *oc, void *data) 544 { 545 MachineClass *mc = MACHINE_CLASS(oc); 546 547 mc->desc = "Mac99 based PowerMAC"; 548 mc->init = ppc_core99_init; 549 mc->block_default_type = IF_IDE; 550 mc->max_cpus = MAX_CPUS; 551 mc->default_boot_order = "cd"; 552 mc->kvm_type = core99_kvm_type; 553 #ifdef TARGET_PPC64 554 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 555 #else 556 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 557 #endif 558 } 559 560 static const TypeInfo core99_machine_info = { 561 .name = MACHINE_TYPE_NAME("mac99"), 562 .parent = TYPE_MACHINE, 563 .class_init = core99_machine_class_init, 564 }; 565 566 static void mac_machine_register_types(void) 567 { 568 type_register_static(&core99_machine_info); 569 } 570 571 type_init(mac_machine_register_types) 572