1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu/datadir.h" 51 #include "qemu/units.h" 52 #include "qapi/error.h" 53 #include "hw/ppc/ppc.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/nvram/mac_nvram.h" 56 #include "hw/boards.h" 57 #include "hw/pci-host/uninorth.h" 58 #include "hw/input/adb.h" 59 #include "hw/ppc/mac_dbdma.h" 60 #include "hw/pci/pci.h" 61 #include "net/net.h" 62 #include "sysemu/sysemu.h" 63 #include "hw/nvram/fw_cfg.h" 64 #include "hw/char/escc.h" 65 #include "hw/misc/macio/macio.h" 66 #include "hw/ppc/openpic.h" 67 #include "hw/loader.h" 68 #include "hw/fw-path-provider.h" 69 #include "elf.h" 70 #include "qemu/error-report.h" 71 #include "sysemu/kvm.h" 72 #include "sysemu/reset.h" 73 #include "kvm_ppc.h" 74 #include "hw/usb.h" 75 #include "hw/sysbus.h" 76 #include "trace.h" 77 78 #define MAX_IDE_BUS 2 79 #define CFG_ADDR 0xf0000510 80 #define TBFREQ (25UL * 1000UL * 1000UL) 81 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 82 #define BUSFREQ (100UL * 1000UL * 1000UL) 83 84 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 85 86 #define PROM_FILENAME "openbios-ppc" 87 #define PROM_BASE 0xfff00000 88 #define PROM_SIZE (1 * MiB) 89 90 #define KERNEL_LOAD_ADDR 0x01000000 91 #define KERNEL_GAP 0x00100000 92 93 #define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99") 94 typedef struct Core99MachineState Core99MachineState; 95 DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE, 96 TYPE_CORE99_MACHINE) 97 98 typedef enum { 99 CORE99_VIA_CONFIG_CUDA = 0, 100 CORE99_VIA_CONFIG_PMU, 101 CORE99_VIA_CONFIG_PMU_ADB 102 } Core99ViaConfig; 103 104 struct Core99MachineState { 105 /*< private >*/ 106 MachineState parent; 107 108 Core99ViaConfig via_config; 109 }; 110 111 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 112 Error **errp) 113 { 114 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 115 } 116 117 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 118 { 119 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 120 } 121 122 static void ppc_core99_reset(void *opaque) 123 { 124 PowerPCCPU *cpu = opaque; 125 126 cpu_reset(CPU(cpu)); 127 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 128 cpu->env.nip = PROM_BASE + 0x100; 129 } 130 131 /* PowerPC Mac99 hardware initialisation */ 132 static void ppc_core99_init(MachineState *machine) 133 { 134 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 135 MachineClass *mc = MACHINE_GET_CLASS(machine); 136 PowerPCCPU *cpu = NULL; 137 CPUPPCState *env = NULL; 138 char *filename; 139 IrqLines *openpic_irqs; 140 int i, j, k, ppc_boot_device, machine_arch, bios_size = -1; 141 const char *bios_name = machine->firmware ?: PROM_FILENAME; 142 MemoryRegion *bios = g_new(MemoryRegion, 1); 143 hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0; 144 long kernel_size = 0, initrd_size = 0; 145 PCIBus *pci_bus; 146 bool has_pmu, has_adb; 147 Object *macio; 148 MACIOIDEState *macio_ide; 149 BusState *adb_bus; 150 MacIONVRAMState *nvr; 151 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 152 void *fw_cfg; 153 SysBusDevice *s; 154 DeviceState *dev, *pic_dev, *uninorth_pci_dev; 155 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; 156 hwaddr nvram_addr = 0xFFF04000; 157 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 158 159 /* init CPUs */ 160 for (i = 0; i < machine->smp.cpus; i++) { 161 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 162 env = &cpu->env; 163 164 /* Set time-base frequency to 100 Mhz */ 165 cpu_ppc_tb_init(env, TBFREQ); 166 qemu_register_reset(ppc_core99_reset, cpu); 167 } 168 169 /* allocate RAM */ 170 if (machine->ram_size > 2 * GiB) { 171 error_report("RAM size more than 2 GiB is not supported"); 172 exit(1); 173 } 174 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 175 176 /* allocate and load firmware ROM */ 177 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 178 &error_fatal); 179 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 180 181 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 182 if (filename) { 183 /* Load OpenBIOS (ELF) */ 184 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 185 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 186 187 if (bios_size <= 0) { 188 /* or load binary ROM image */ 189 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 190 } 191 g_free(filename); 192 } 193 if (bios_size < 0 || bios_size > PROM_SIZE) { 194 error_report("could not load PowerPC bios '%s'", bios_name); 195 exit(1); 196 } 197 198 if (machine->kernel_filename) { 199 int bswap_needed = 0; 200 201 #ifdef BSWAP_NEEDED 202 bswap_needed = 1; 203 #endif 204 kernel_base = KERNEL_LOAD_ADDR; 205 kernel_size = load_elf(machine->kernel_filename, NULL, 206 translate_kernel_address, NULL, NULL, NULL, 207 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 208 if (kernel_size < 0) { 209 kernel_size = load_aout(machine->kernel_filename, kernel_base, 210 machine->ram_size - kernel_base, 211 bswap_needed, TARGET_PAGE_SIZE); 212 } 213 if (kernel_size < 0) { 214 kernel_size = load_image_targphys(machine->kernel_filename, 215 kernel_base, 216 machine->ram_size - kernel_base); 217 } 218 if (kernel_size < 0) { 219 error_report("could not load kernel '%s'", 220 machine->kernel_filename); 221 exit(1); 222 } 223 /* load initrd */ 224 if (machine->initrd_filename) { 225 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 226 initrd_size = load_image_targphys(machine->initrd_filename, 227 initrd_base, 228 machine->ram_size - initrd_base); 229 if (initrd_size < 0) { 230 error_report("could not load initial ram disk '%s'", 231 machine->initrd_filename); 232 exit(1); 233 } 234 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 235 } else { 236 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 237 } 238 ppc_boot_device = 'm'; 239 } else { 240 ppc_boot_device = '\0'; 241 /* We consider that NewWorld PowerMac never have any floppy drive 242 * For now, OHW cannot boot from the network. 243 */ 244 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 245 if (machine->boot_config.order[i] >= 'c' && 246 machine->boot_config.order[i] <= 'f') { 247 ppc_boot_device = machine->boot_config.order[i]; 248 break; 249 } 250 } 251 if (ppc_boot_device == '\0') { 252 error_report("No valid boot device for Mac99 machine"); 253 exit(1); 254 } 255 } 256 257 openpic_irqs = g_new0(IrqLines, machine->smp.cpus); 258 dev = DEVICE(cpu); 259 for (i = 0; i < machine->smp.cpus; i++) { 260 /* Mac99 IRQ connection between OpenPIC outputs pins 261 * and PowerPC input pins 262 */ 263 switch (PPC_INPUT(env)) { 264 case PPC_FLAGS_INPUT_6xx: 265 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 266 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); 267 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 268 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); 269 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 270 qdev_get_gpio_in(dev, PPC6xx_INPUT_MCP); 271 /* Not connected ? */ 272 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 273 /* Check this */ 274 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 275 qdev_get_gpio_in(dev, PPC6xx_INPUT_HRESET); 276 break; 277 #if defined(TARGET_PPC64) 278 case PPC_FLAGS_INPUT_970: 279 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 280 qdev_get_gpio_in(dev, PPC970_INPUT_INT); 281 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 282 qdev_get_gpio_in(dev, PPC970_INPUT_INT); 283 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 284 qdev_get_gpio_in(dev, PPC970_INPUT_MCP); 285 /* Not connected ? */ 286 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 287 /* Check this */ 288 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 289 qdev_get_gpio_in(dev, PPC970_INPUT_HRESET); 290 break; 291 #endif /* defined(TARGET_PPC64) */ 292 default: 293 error_report("Bus model not supported on mac99 machine"); 294 exit(1); 295 } 296 } 297 298 /* UniN init */ 299 s = SYS_BUS_DEVICE(qdev_new(TYPE_UNI_NORTH)); 300 sysbus_realize_and_unref(s, &error_fatal); 301 memory_region_add_subregion(get_system_memory(), 0xf8000000, 302 sysbus_mmio_get_region(s, 0)); 303 304 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 305 machine_arch = ARCH_MAC99_U3; 306 /* 970 gets a U3 bus */ 307 /* Uninorth AGP bus */ 308 uninorth_pci_dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 309 s = SYS_BUS_DEVICE(uninorth_pci_dev); 310 sysbus_realize_and_unref(s, &error_fatal); 311 sysbus_mmio_map(s, 0, 0xf0800000); 312 sysbus_mmio_map(s, 1, 0xf0c00000); 313 /* PCI hole */ 314 memory_region_add_subregion(get_system_memory(), 0x80000000, 315 sysbus_mmio_get_region(s, 2)); 316 /* Register 8 MB of ISA IO space */ 317 memory_region_add_subregion(get_system_memory(), 0xf2000000, 318 sysbus_mmio_get_region(s, 3)); 319 } else { 320 machine_arch = ARCH_MAC99; 321 /* Use values found on a real PowerMac */ 322 /* Uninorth AGP bus */ 323 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 324 s = SYS_BUS_DEVICE(uninorth_agp_dev); 325 sysbus_realize_and_unref(s, &error_fatal); 326 sysbus_mmio_map(s, 0, 0xf0800000); 327 sysbus_mmio_map(s, 1, 0xf0c00000); 328 329 /* Uninorth internal bus */ 330 uninorth_internal_dev = qdev_new( 331 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 332 s = SYS_BUS_DEVICE(uninorth_internal_dev); 333 sysbus_realize_and_unref(s, &error_fatal); 334 sysbus_mmio_map(s, 0, 0xf4800000); 335 sysbus_mmio_map(s, 1, 0xf4c00000); 336 337 /* Uninorth main bus - this must be last to make it the default */ 338 uninorth_pci_dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 339 qdev_prop_set_uint32(uninorth_pci_dev, "ofw-addr", 0xf2000000); 340 s = SYS_BUS_DEVICE(uninorth_pci_dev); 341 sysbus_realize_and_unref(s, &error_fatal); 342 sysbus_mmio_map(s, 0, 0xf2800000); 343 sysbus_mmio_map(s, 1, 0xf2c00000); 344 /* PCI hole */ 345 memory_region_add_subregion(get_system_memory(), 0x80000000, 346 sysbus_mmio_get_region(s, 2)); 347 /* Register 8 MB of ISA IO space */ 348 memory_region_add_subregion(get_system_memory(), 0xf2000000, 349 sysbus_mmio_get_region(s, 3)); 350 } 351 352 machine->usb |= defaults_enabled() && !machine->usb_disabled; 353 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 354 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 355 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 356 357 /* init basic PC hardware */ 358 pci_bus = PCI_HOST_BRIDGE(uninorth_pci_dev)->bus; 359 360 /* MacIO */ 361 macio = OBJECT(pci_new(-1, TYPE_NEWWORLD_MACIO)); 362 dev = DEVICE(macio); 363 qdev_prop_set_uint64(dev, "frequency", tbfreq); 364 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 365 qdev_prop_set_bit(dev, "has-adb", has_adb); 366 367 dev = DEVICE(object_resolve_path_component(macio, "escc")); 368 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 369 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 370 371 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 372 373 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 374 for (i = 0; i < 4; i++) { 375 qdev_connect_gpio_out(uninorth_pci_dev, i, 376 qdev_get_gpio_in(pic_dev, 0x1b + i)); 377 } 378 379 /* TODO: additional PCI buses only wired up for 32-bit machines */ 380 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { 381 /* Uninorth AGP bus */ 382 for (i = 0; i < 4; i++) { 383 qdev_connect_gpio_out(uninorth_agp_dev, i, 384 qdev_get_gpio_in(pic_dev, 0x1b + i)); 385 } 386 387 /* Uninorth internal bus */ 388 for (i = 0; i < 4; i++) { 389 qdev_connect_gpio_out(uninorth_internal_dev, i, 390 qdev_get_gpio_in(pic_dev, 0x1b + i)); 391 } 392 } 393 394 /* OpenPIC */ 395 s = SYS_BUS_DEVICE(pic_dev); 396 k = 0; 397 for (i = 0; i < machine->smp.cpus; i++) { 398 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 399 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 400 } 401 } 402 g_free(openpic_irqs); 403 404 /* We only emulate 2 out of 3 IDE controllers for now */ 405 ide_drive_get(hd, ARRAY_SIZE(hd)); 406 407 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 408 macio_ide_init_drives(macio_ide, hd); 409 410 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 411 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 412 413 if (has_adb) { 414 if (has_pmu) { 415 dev = DEVICE(object_resolve_path_component(macio, "pmu")); 416 } else { 417 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 418 } 419 420 adb_bus = qdev_get_child_bus(dev, "adb.0"); 421 dev = qdev_new(TYPE_ADB_KEYBOARD); 422 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 423 424 dev = qdev_new(TYPE_ADB_MOUSE); 425 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 426 } 427 428 if (machine->usb) { 429 pci_create_simple(pci_bus, -1, "pci-ohci"); 430 431 /* U3 needs to use USB for input because Linux doesn't support via-cuda 432 on PPC64 */ 433 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 434 USBBus *usb_bus; 435 436 usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS, 437 &error_abort)); 438 usb_create_simple(usb_bus, "usb-kbd"); 439 usb_create_simple(usb_bus, "usb-mouse"); 440 } 441 } 442 443 pci_vga_init(pci_bus); 444 445 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 446 graphic_depth = 15; 447 } 448 449 pci_init_nic_devices(pci_bus, mc->default_nic); 450 451 /* The NewWorld NVRAM is not located in the MacIO device */ 452 if (kvm_enabled() && qemu_real_host_page_size() > 4096) { 453 /* We can't combine read-write and read-only in a single page, so 454 move the NVRAM out of ROM again for KVM */ 455 nvram_addr = 0xFFE00000; 456 } 457 dev = qdev_new(TYPE_MACIO_NVRAM); 458 qdev_prop_set_uint32(dev, "size", MACIO_NVRAM_SIZE); 459 qdev_prop_set_uint32(dev, "it_shift", 1); 460 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 461 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 462 nvr = MACIO_NVRAM(dev); 463 pmac_format_nvram_partition(nvr, MACIO_NVRAM_SIZE); 464 /* No PCI init: the BIOS will do it */ 465 466 dev = qdev_new(TYPE_FW_CFG_MEM); 467 fw_cfg = FW_CFG(dev); 468 qdev_prop_set_uint32(dev, "data_width", 1); 469 qdev_prop_set_bit(dev, "dma_enabled", false); 470 object_property_add_child(OBJECT(machine), TYPE_FW_CFG, OBJECT(fw_cfg)); 471 s = SYS_BUS_DEVICE(dev); 472 sysbus_realize_and_unref(s, &error_fatal); 473 sysbus_mmio_map(s, 0, CFG_ADDR); 474 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 475 476 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 477 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 478 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 479 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 480 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 481 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 482 if (machine->kernel_cmdline) { 483 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 484 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 485 machine->kernel_cmdline); 486 } else { 487 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 488 } 489 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 490 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 491 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 492 493 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 494 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 495 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 496 497 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 498 499 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 500 if (kvm_enabled()) { 501 uint8_t *hypercall; 502 503 hypercall = g_malloc(16); 504 kvmppc_get_hypercall(env, hypercall, 16); 505 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 506 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 507 } 508 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 509 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 510 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 511 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 512 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 513 514 /* MacOS NDRV VGA driver */ 515 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 516 if (filename) { 517 gchar *ndrv_file; 518 gsize ndrv_size; 519 520 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 521 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 522 } 523 g_free(filename); 524 } 525 526 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 527 } 528 529 /* 530 * Implementation of an interface to adjust firmware path 531 * for the bootindex property handling. 532 */ 533 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 534 DeviceState *dev) 535 { 536 PCIDevice *pci; 537 MACIOIDEState *macio_ide; 538 539 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 540 pci = PCI_DEVICE(dev); 541 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 542 } 543 544 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 545 macio_ide = MACIO_IDE(dev); 546 return g_strdup_printf("ata-3@%x", macio_ide->addr); 547 } 548 549 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 550 return g_strdup("disk"); 551 } 552 553 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 554 return g_strdup("cdrom"); 555 } 556 557 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 558 return g_strdup("disk"); 559 } 560 561 return NULL; 562 } 563 static int core99_kvm_type(MachineState *machine, const char *arg) 564 { 565 /* Always force PR KVM */ 566 return 2; 567 } 568 569 static void core99_machine_class_init(ObjectClass *oc, void *data) 570 { 571 MachineClass *mc = MACHINE_CLASS(oc); 572 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 573 574 mc->desc = "Mac99 based PowerMAC"; 575 mc->init = ppc_core99_init; 576 mc->block_default_type = IF_IDE; 577 /* SMP is not supported currently */ 578 mc->max_cpus = 1; 579 mc->default_boot_order = "cd"; 580 mc->default_display = "std"; 581 mc->default_nic = "sungem"; 582 mc->kvm_type = core99_kvm_type; 583 #ifdef TARGET_PPC64 584 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 585 #else 586 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 587 #endif 588 mc->default_ram_id = "ppc_core99.ram"; 589 mc->ignore_boot_device_suffixes = true; 590 fwc->get_dev_path = core99_fw_dev_path; 591 } 592 593 static char *core99_get_via_config(Object *obj, Error **errp) 594 { 595 Core99MachineState *cms = CORE99_MACHINE(obj); 596 597 switch (cms->via_config) { 598 default: 599 case CORE99_VIA_CONFIG_CUDA: 600 return g_strdup("cuda"); 601 602 case CORE99_VIA_CONFIG_PMU: 603 return g_strdup("pmu"); 604 605 case CORE99_VIA_CONFIG_PMU_ADB: 606 return g_strdup("pmu-adb"); 607 } 608 } 609 610 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 611 { 612 Core99MachineState *cms = CORE99_MACHINE(obj); 613 614 if (!strcmp(value, "cuda")) { 615 cms->via_config = CORE99_VIA_CONFIG_CUDA; 616 } else if (!strcmp(value, "pmu")) { 617 cms->via_config = CORE99_VIA_CONFIG_PMU; 618 } else if (!strcmp(value, "pmu-adb")) { 619 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 620 } else { 621 error_setg(errp, "Invalid via value"); 622 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 623 } 624 } 625 626 static void core99_instance_init(Object *obj) 627 { 628 Core99MachineState *cms = CORE99_MACHINE(obj); 629 630 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 631 cms->via_config = CORE99_VIA_CONFIG_CUDA; 632 object_property_add_str(obj, "via", core99_get_via_config, 633 core99_set_via_config); 634 object_property_set_description(obj, "via", 635 "Set VIA configuration. " 636 "Valid values are cuda, pmu and pmu-adb"); 637 638 return; 639 } 640 641 static const TypeInfo core99_machine_info = { 642 .name = MACHINE_TYPE_NAME("mac99"), 643 .parent = TYPE_MACHINE, 644 .class_init = core99_machine_class_init, 645 .instance_init = core99_instance_init, 646 .instance_size = sizeof(Core99MachineState), 647 .interfaces = (InterfaceInfo[]) { 648 { TYPE_FW_PATH_PROVIDER }, 649 { } 650 }, 651 }; 652 653 static void mac_machine_register_types(void) 654 { 655 type_register_static(&core99_machine_info); 656 } 657 658 type_init(mac_machine_register_types) 659