1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu/datadir.h" 51 #include "qemu/units.h" 52 #include "qapi/error.h" 53 #include "hw/ppc/ppc.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/ppc/mac.h" 56 #include "hw/boards.h" 57 #include "hw/pci-host/uninorth.h" 58 #include "hw/input/adb.h" 59 #include "hw/ppc/mac_dbdma.h" 60 #include "hw/pci/pci.h" 61 #include "net/net.h" 62 #include "sysemu/sysemu.h" 63 #include "hw/nvram/fw_cfg.h" 64 #include "hw/char/escc.h" 65 #include "hw/misc/macio/macio.h" 66 #include "hw/ppc/openpic.h" 67 #include "hw/loader.h" 68 #include "hw/fw-path-provider.h" 69 #include "elf.h" 70 #include "qemu/error-report.h" 71 #include "sysemu/kvm.h" 72 #include "sysemu/reset.h" 73 #include "kvm_ppc.h" 74 #include "hw/usb.h" 75 #include "hw/sysbus.h" 76 #include "trace.h" 77 78 #define MAX_IDE_BUS 2 79 #define CFG_ADDR 0xf0000510 80 #define TBFREQ (100UL * 1000UL * 1000UL) 81 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 82 #define BUSFREQ (100UL * 1000UL * 1000UL) 83 84 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 85 86 #define PROM_BASE 0xfff00000 87 #define PROM_SIZE (1 * MiB) 88 89 #define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99") 90 typedef struct Core99MachineState Core99MachineState; 91 DECLARE_INSTANCE_CHECKER(Core99MachineState, CORE99_MACHINE, 92 TYPE_CORE99_MACHINE) 93 94 #define CORE99_VIA_CONFIG_CUDA 0x0 95 #define CORE99_VIA_CONFIG_PMU 0x1 96 #define CORE99_VIA_CONFIG_PMU_ADB 0x2 97 98 struct Core99MachineState { 99 /*< private >*/ 100 MachineState parent; 101 102 uint8_t via_config; 103 }; 104 105 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 106 Error **errp) 107 { 108 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 109 } 110 111 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 112 { 113 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 114 } 115 116 static void ppc_core99_reset(void *opaque) 117 { 118 PowerPCCPU *cpu = opaque; 119 120 cpu_reset(CPU(cpu)); 121 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 122 cpu->env.nip = PROM_BASE + 0x100; 123 } 124 125 /* PowerPC Mac99 hardware initialisation */ 126 static void ppc_core99_init(MachineState *machine) 127 { 128 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 129 PowerPCCPU *cpu = NULL; 130 CPUPPCState *env = NULL; 131 char *filename; 132 IrqLines *openpic_irqs; 133 int i, j, k, ppc_boot_device, machine_arch, bios_size = -1; 134 const char *bios_name = machine->firmware ?: PROM_FILENAME; 135 MemoryRegion *bios = g_new(MemoryRegion, 1); 136 hwaddr kernel_base = 0, initrd_base = 0, cmdline_base = 0; 137 long kernel_size = 0, initrd_size = 0; 138 PCIBus *pci_bus; 139 bool has_pmu, has_adb; 140 Object *macio; 141 MACIOIDEState *macio_ide; 142 BusState *adb_bus; 143 MacIONVRAMState *nvr; 144 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 145 void *fw_cfg; 146 SysBusDevice *s; 147 DeviceState *dev, *pic_dev, *uninorth_pci_dev; 148 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; 149 hwaddr nvram_addr = 0xFFF04000; 150 uint64_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TBFREQ; 151 152 /* init CPUs */ 153 for (i = 0; i < machine->smp.cpus; i++) { 154 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 155 env = &cpu->env; 156 157 /* Set time-base frequency to 100 Mhz */ 158 cpu_ppc_tb_init(env, TBFREQ); 159 qemu_register_reset(ppc_core99_reset, cpu); 160 } 161 162 /* allocate RAM */ 163 if (machine->ram_size > 2 * GiB) { 164 error_report("RAM size more than 2 GiB is not supported"); 165 exit(1); 166 } 167 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 168 169 /* allocate and load firmware ROM */ 170 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 171 &error_fatal); 172 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 173 174 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 175 if (filename) { 176 /* Load OpenBIOS (ELF) */ 177 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 178 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 179 180 if (bios_size <= 0) { 181 /* or load binary ROM image */ 182 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 183 } 184 g_free(filename); 185 } 186 if (bios_size < 0 || bios_size > PROM_SIZE) { 187 error_report("could not load PowerPC bios '%s'", bios_name); 188 exit(1); 189 } 190 191 if (machine->kernel_filename) { 192 int bswap_needed = 0; 193 194 #ifdef BSWAP_NEEDED 195 bswap_needed = 1; 196 #endif 197 kernel_base = KERNEL_LOAD_ADDR; 198 kernel_size = load_elf(machine->kernel_filename, NULL, 199 translate_kernel_address, NULL, NULL, NULL, 200 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 201 if (kernel_size < 0) 202 kernel_size = load_aout(machine->kernel_filename, kernel_base, 203 machine->ram_size - kernel_base, 204 bswap_needed, TARGET_PAGE_SIZE); 205 if (kernel_size < 0) 206 kernel_size = load_image_targphys(machine->kernel_filename, 207 kernel_base, 208 machine->ram_size - kernel_base); 209 if (kernel_size < 0) { 210 error_report("could not load kernel '%s'", 211 machine->kernel_filename); 212 exit(1); 213 } 214 /* load initrd */ 215 if (machine->initrd_filename) { 216 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 217 initrd_size = load_image_targphys(machine->initrd_filename, 218 initrd_base, 219 machine->ram_size - initrd_base); 220 if (initrd_size < 0) { 221 error_report("could not load initial ram disk '%s'", 222 machine->initrd_filename); 223 exit(1); 224 } 225 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 226 } else { 227 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 228 } 229 ppc_boot_device = 'm'; 230 } else { 231 ppc_boot_device = '\0'; 232 /* We consider that NewWorld PowerMac never have any floppy drive 233 * For now, OHW cannot boot from the network. 234 */ 235 for (i = 0; machine->boot_config.order[i] != '\0'; i++) { 236 if (machine->boot_config.order[i] >= 'c' && 237 machine->boot_config.order[i] <= 'f') { 238 ppc_boot_device = machine->boot_config.order[i]; 239 break; 240 } 241 } 242 if (ppc_boot_device == '\0') { 243 error_report("No valid boot device for Mac99 machine"); 244 exit(1); 245 } 246 } 247 248 openpic_irqs = g_new0(IrqLines, machine->smp.cpus); 249 dev = DEVICE(cpu); 250 for (i = 0; i < machine->smp.cpus; i++) { 251 /* Mac99 IRQ connection between OpenPIC outputs pins 252 * and PowerPC input pins 253 */ 254 switch (PPC_INPUT(env)) { 255 case PPC_FLAGS_INPUT_6xx: 256 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 257 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); 258 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 259 qdev_get_gpio_in(dev, PPC6xx_INPUT_INT); 260 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 261 qdev_get_gpio_in(dev, PPC6xx_INPUT_MCP); 262 /* Not connected ? */ 263 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 264 /* Check this */ 265 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 266 qdev_get_gpio_in(dev, PPC6xx_INPUT_HRESET); 267 break; 268 #if defined(TARGET_PPC64) 269 case PPC_FLAGS_INPUT_970: 270 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 271 qdev_get_gpio_in(dev, PPC970_INPUT_INT); 272 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 273 qdev_get_gpio_in(dev, PPC970_INPUT_INT); 274 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 275 qdev_get_gpio_in(dev, PPC970_INPUT_MCP); 276 /* Not connected ? */ 277 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 278 /* Check this */ 279 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 280 qdev_get_gpio_in(dev, PPC970_INPUT_HRESET); 281 break; 282 #endif /* defined(TARGET_PPC64) */ 283 default: 284 error_report("Bus model not supported on mac99 machine"); 285 exit(1); 286 } 287 } 288 289 /* UniN init */ 290 s = SYS_BUS_DEVICE(qdev_new(TYPE_UNI_NORTH)); 291 sysbus_realize_and_unref(s, &error_fatal); 292 memory_region_add_subregion(get_system_memory(), 0xf8000000, 293 sysbus_mmio_get_region(s, 0)); 294 295 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 296 machine_arch = ARCH_MAC99_U3; 297 /* 970 gets a U3 bus */ 298 /* Uninorth AGP bus */ 299 uninorth_pci_dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 300 s = SYS_BUS_DEVICE(uninorth_pci_dev); 301 sysbus_realize_and_unref(s, &error_fatal); 302 sysbus_mmio_map(s, 0, 0xf0800000); 303 sysbus_mmio_map(s, 1, 0xf0c00000); 304 /* PCI hole */ 305 memory_region_add_subregion(get_system_memory(), 0x80000000, 306 sysbus_mmio_get_region(s, 2)); 307 /* Register 8 MB of ISA IO space */ 308 memory_region_add_subregion(get_system_memory(), 0xf2000000, 309 sysbus_mmio_get_region(s, 3)); 310 } else { 311 machine_arch = ARCH_MAC99; 312 /* Use values found on a real PowerMac */ 313 /* Uninorth AGP bus */ 314 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 315 s = SYS_BUS_DEVICE(uninorth_agp_dev); 316 sysbus_realize_and_unref(s, &error_fatal); 317 sysbus_mmio_map(s, 0, 0xf0800000); 318 sysbus_mmio_map(s, 1, 0xf0c00000); 319 320 /* Uninorth internal bus */ 321 uninorth_internal_dev = qdev_new( 322 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 323 s = SYS_BUS_DEVICE(uninorth_internal_dev); 324 sysbus_realize_and_unref(s, &error_fatal); 325 sysbus_mmio_map(s, 0, 0xf4800000); 326 sysbus_mmio_map(s, 1, 0xf4c00000); 327 328 /* Uninorth main bus - this must be last to make it the default */ 329 uninorth_pci_dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 330 qdev_prop_set_uint32(uninorth_pci_dev, "ofw-addr", 0xf2000000); 331 s = SYS_BUS_DEVICE(uninorth_pci_dev); 332 sysbus_realize_and_unref(s, &error_fatal); 333 sysbus_mmio_map(s, 0, 0xf2800000); 334 sysbus_mmio_map(s, 1, 0xf2c00000); 335 /* PCI hole */ 336 memory_region_add_subregion(get_system_memory(), 0x80000000, 337 sysbus_mmio_get_region(s, 2)); 338 /* Register 8 MB of ISA IO space */ 339 memory_region_add_subregion(get_system_memory(), 0xf2000000, 340 sysbus_mmio_get_region(s, 3)); 341 } 342 343 machine->usb |= defaults_enabled() && !machine->usb_disabled; 344 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 345 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 346 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 347 348 /* init basic PC hardware */ 349 pci_bus = PCI_HOST_BRIDGE(uninorth_pci_dev)->bus; 350 351 /* MacIO */ 352 macio = OBJECT(pci_new(-1, TYPE_NEWWORLD_MACIO)); 353 dev = DEVICE(macio); 354 qdev_prop_set_uint64(dev, "frequency", tbfreq); 355 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 356 qdev_prop_set_bit(dev, "has-adb", has_adb); 357 358 dev = DEVICE(object_resolve_path_component(macio, "escc")); 359 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 360 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 361 362 pci_realize_and_unref(PCI_DEVICE(macio), pci_bus, &error_fatal); 363 364 pic_dev = DEVICE(object_resolve_path_component(macio, "pic")); 365 for (i = 0; i < 4; i++) { 366 qdev_connect_gpio_out(uninorth_pci_dev, i, 367 qdev_get_gpio_in(pic_dev, 0x1b + i)); 368 } 369 370 /* TODO: additional PCI buses only wired up for 32-bit machines */ 371 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { 372 /* Uninorth AGP bus */ 373 for (i = 0; i < 4; i++) { 374 qdev_connect_gpio_out(uninorth_agp_dev, i, 375 qdev_get_gpio_in(pic_dev, 0x1b + i)); 376 } 377 378 /* Uninorth internal bus */ 379 for (i = 0; i < 4; i++) { 380 qdev_connect_gpio_out(uninorth_internal_dev, i, 381 qdev_get_gpio_in(pic_dev, 0x1b + i)); 382 } 383 } 384 385 /* OpenPIC */ 386 s = SYS_BUS_DEVICE(pic_dev); 387 k = 0; 388 for (i = 0; i < machine->smp.cpus; i++) { 389 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 390 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 391 } 392 } 393 g_free(openpic_irqs); 394 395 /* We only emulate 2 out of 3 IDE controllers for now */ 396 ide_drive_get(hd, ARRAY_SIZE(hd)); 397 398 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[0]")); 399 macio_ide_init_drives(macio_ide, hd); 400 401 macio_ide = MACIO_IDE(object_resolve_path_component(macio, "ide[1]")); 402 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 403 404 if (has_adb) { 405 if (has_pmu) { 406 dev = DEVICE(object_resolve_path_component(macio, "pmu")); 407 } else { 408 dev = DEVICE(object_resolve_path_component(macio, "cuda")); 409 } 410 411 adb_bus = qdev_get_child_bus(dev, "adb.0"); 412 dev = qdev_new(TYPE_ADB_KEYBOARD); 413 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 414 415 dev = qdev_new(TYPE_ADB_MOUSE); 416 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 417 } 418 419 if (machine->usb) { 420 pci_create_simple(pci_bus, -1, "pci-ohci"); 421 422 /* U3 needs to use USB for input because Linux doesn't support via-cuda 423 on PPC64 */ 424 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 425 USBBus *usb_bus = usb_bus_find(-1); 426 427 usb_create_simple(usb_bus, "usb-kbd"); 428 usb_create_simple(usb_bus, "usb-mouse"); 429 } 430 } 431 432 pci_vga_init(pci_bus); 433 434 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 435 graphic_depth = 15; 436 } 437 438 for (i = 0; i < nb_nics; i++) { 439 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL); 440 } 441 442 /* The NewWorld NVRAM is not located in the MacIO device */ 443 if (kvm_enabled() && qemu_real_host_page_size() > 4096) { 444 /* We can't combine read-write and read-only in a single page, so 445 move the NVRAM out of ROM again for KVM */ 446 nvram_addr = 0xFFE00000; 447 } 448 dev = qdev_new(TYPE_MACIO_NVRAM); 449 qdev_prop_set_uint32(dev, "size", 0x2000); 450 qdev_prop_set_uint32(dev, "it_shift", 1); 451 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 452 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 453 nvr = MACIO_NVRAM(dev); 454 pmac_format_nvram_partition(nvr, 0x2000); 455 /* No PCI init: the BIOS will do it */ 456 457 dev = qdev_new(TYPE_FW_CFG_MEM); 458 fw_cfg = FW_CFG(dev); 459 qdev_prop_set_uint32(dev, "data_width", 1); 460 qdev_prop_set_bit(dev, "dma_enabled", false); 461 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 462 OBJECT(fw_cfg)); 463 s = SYS_BUS_DEVICE(dev); 464 sysbus_realize_and_unref(s, &error_fatal); 465 sysbus_mmio_map(s, 0, CFG_ADDR); 466 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 467 468 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus); 469 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 470 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 471 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 472 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 473 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 474 if (machine->kernel_cmdline) { 475 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 476 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, 477 machine->kernel_cmdline); 478 } else { 479 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 480 } 481 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 482 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 484 485 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 486 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 487 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 488 489 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 490 491 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 492 if (kvm_enabled()) { 493 uint8_t *hypercall; 494 495 hypercall = g_malloc(16); 496 kvmppc_get_hypercall(env, hypercall, 16); 497 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 498 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 499 } 500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 501 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 502 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 503 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 504 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 505 506 /* MacOS NDRV VGA driver */ 507 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 508 if (filename) { 509 gchar *ndrv_file; 510 gsize ndrv_size; 511 512 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 513 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 514 } 515 g_free(filename); 516 } 517 518 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 519 } 520 521 /* 522 * Implementation of an interface to adjust firmware path 523 * for the bootindex property handling. 524 */ 525 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 526 DeviceState *dev) 527 { 528 PCIDevice *pci; 529 MACIOIDEState *macio_ide; 530 531 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 532 pci = PCI_DEVICE(dev); 533 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 534 } 535 536 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 537 macio_ide = MACIO_IDE(dev); 538 return g_strdup_printf("ata-3@%x", macio_ide->addr); 539 } 540 541 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 542 return g_strdup("disk"); 543 } 544 545 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 546 return g_strdup("cdrom"); 547 } 548 549 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 550 return g_strdup("disk"); 551 } 552 553 return NULL; 554 } 555 static int core99_kvm_type(MachineState *machine, const char *arg) 556 { 557 /* Always force PR KVM */ 558 return 2; 559 } 560 561 static void core99_machine_class_init(ObjectClass *oc, void *data) 562 { 563 MachineClass *mc = MACHINE_CLASS(oc); 564 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 565 566 mc->desc = "Mac99 based PowerMAC"; 567 mc->init = ppc_core99_init; 568 mc->block_default_type = IF_IDE; 569 /* SMP is not supported currently */ 570 mc->max_cpus = 1; 571 mc->default_boot_order = "cd"; 572 mc->default_display = "std"; 573 mc->kvm_type = core99_kvm_type; 574 #ifdef TARGET_PPC64 575 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 576 #else 577 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 578 #endif 579 mc->default_ram_id = "ppc_core99.ram"; 580 mc->ignore_boot_device_suffixes = true; 581 fwc->get_dev_path = core99_fw_dev_path; 582 } 583 584 static char *core99_get_via_config(Object *obj, Error **errp) 585 { 586 Core99MachineState *cms = CORE99_MACHINE(obj); 587 588 switch (cms->via_config) { 589 default: 590 case CORE99_VIA_CONFIG_CUDA: 591 return g_strdup("cuda"); 592 593 case CORE99_VIA_CONFIG_PMU: 594 return g_strdup("pmu"); 595 596 case CORE99_VIA_CONFIG_PMU_ADB: 597 return g_strdup("pmu-adb"); 598 } 599 } 600 601 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 602 { 603 Core99MachineState *cms = CORE99_MACHINE(obj); 604 605 if (!strcmp(value, "cuda")) { 606 cms->via_config = CORE99_VIA_CONFIG_CUDA; 607 } else if (!strcmp(value, "pmu")) { 608 cms->via_config = CORE99_VIA_CONFIG_PMU; 609 } else if (!strcmp(value, "pmu-adb")) { 610 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 611 } else { 612 error_setg(errp, "Invalid via value"); 613 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 614 } 615 } 616 617 static void core99_instance_init(Object *obj) 618 { 619 Core99MachineState *cms = CORE99_MACHINE(obj); 620 621 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 622 cms->via_config = CORE99_VIA_CONFIG_CUDA; 623 object_property_add_str(obj, "via", core99_get_via_config, 624 core99_set_via_config); 625 object_property_set_description(obj, "via", 626 "Set VIA configuration. " 627 "Valid values are cuda, pmu and pmu-adb"); 628 629 return; 630 } 631 632 static const TypeInfo core99_machine_info = { 633 .name = MACHINE_TYPE_NAME("mac99"), 634 .parent = TYPE_MACHINE, 635 .class_init = core99_machine_class_init, 636 .instance_init = core99_instance_init, 637 .instance_size = sizeof(Core99MachineState), 638 .interfaces = (InterfaceInfo[]) { 639 { TYPE_FW_PATH_PROVIDER }, 640 { } 641 }, 642 }; 643 644 static void mac_machine_register_types(void) 645 { 646 type_register_static(&core99_machine_info); 647 } 648 649 type_init(mac_machine_register_types) 650