1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu-common.h" 51 #include "qemu/datadir.h" 52 #include "qapi/error.h" 53 #include "hw/ppc/ppc.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/ppc/mac.h" 56 #include "hw/input/adb.h" 57 #include "hw/ppc/mac_dbdma.h" 58 #include "hw/pci/pci.h" 59 #include "net/net.h" 60 #include "sysemu/sysemu.h" 61 #include "hw/boards.h" 62 #include "hw/nvram/fw_cfg.h" 63 #include "hw/char/escc.h" 64 #include "hw/misc/macio/macio.h" 65 #include "hw/ppc/openpic.h" 66 #include "hw/loader.h" 67 #include "hw/fw-path-provider.h" 68 #include "elf.h" 69 #include "qemu/error-report.h" 70 #include "sysemu/kvm.h" 71 #include "sysemu/reset.h" 72 #include "kvm_ppc.h" 73 #include "hw/usb.h" 74 #include "exec/address-spaces.h" 75 #include "hw/sysbus.h" 76 #include "trace.h" 77 78 #define MAX_IDE_BUS 2 79 #define CFG_ADDR 0xf0000510 80 #define TBFREQ (100UL * 1000UL * 1000UL) 81 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 82 #define BUSFREQ (100UL * 1000UL * 1000UL) 83 84 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 85 86 #define PROM_BASE 0xfff00000 87 #define PROM_SIZE (1 * MiB) 88 89 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 90 Error **errp) 91 { 92 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 93 } 94 95 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 96 { 97 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 98 } 99 100 static void ppc_core99_reset(void *opaque) 101 { 102 PowerPCCPU *cpu = opaque; 103 104 cpu_reset(CPU(cpu)); 105 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 106 cpu->env.nip = PROM_BASE + 0x100; 107 } 108 109 /* PowerPC Mac99 hardware initialisation */ 110 static void ppc_core99_init(MachineState *machine) 111 { 112 ram_addr_t ram_size = machine->ram_size; 113 const char *bios_name = machine->firmware ?: PROM_FILENAME; 114 const char *kernel_filename = machine->kernel_filename; 115 const char *kernel_cmdline = machine->kernel_cmdline; 116 const char *initrd_filename = machine->initrd_filename; 117 const char *boot_device = machine->boot_order; 118 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 119 PowerPCCPU *cpu = NULL; 120 CPUPPCState *env = NULL; 121 char *filename; 122 IrqLines *openpic_irqs; 123 int linux_boot, i, j, k; 124 MemoryRegion *bios = g_new(MemoryRegion, 1); 125 hwaddr kernel_base, initrd_base, cmdline_base = 0; 126 long kernel_size, initrd_size; 127 UNINHostState *uninorth_pci; 128 PCIBus *pci_bus; 129 PCIDevice *macio; 130 ESCCState *escc; 131 bool has_pmu, has_adb; 132 MACIOIDEState *macio_ide; 133 BusState *adb_bus; 134 MacIONVRAMState *nvr; 135 int bios_size; 136 int ppc_boot_device; 137 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 138 void *fw_cfg; 139 int machine_arch; 140 SysBusDevice *s; 141 DeviceState *dev, *pic_dev; 142 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; 143 hwaddr nvram_addr = 0xFFF04000; 144 uint64_t tbfreq; 145 unsigned int smp_cpus = machine->smp.cpus; 146 147 linux_boot = (kernel_filename != NULL); 148 149 /* init CPUs */ 150 for (i = 0; i < smp_cpus; i++) { 151 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 152 env = &cpu->env; 153 154 /* Set time-base frequency to 100 Mhz */ 155 cpu_ppc_tb_init(env, TBFREQ); 156 qemu_register_reset(ppc_core99_reset, cpu); 157 } 158 159 /* allocate RAM */ 160 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 161 162 /* allocate and load firmware ROM */ 163 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 164 &error_fatal); 165 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 166 167 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 168 if (filename) { 169 /* Load OpenBIOS (ELF) */ 170 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 171 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 172 173 if (bios_size <= 0) { 174 /* or load binary ROM image */ 175 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 176 } 177 g_free(filename); 178 } else { 179 bios_size = -1; 180 } 181 if (bios_size < 0 || bios_size > PROM_SIZE) { 182 error_report("could not load PowerPC bios '%s'", bios_name); 183 exit(1); 184 } 185 186 if (linux_boot) { 187 int bswap_needed; 188 189 #ifdef BSWAP_NEEDED 190 bswap_needed = 1; 191 #else 192 bswap_needed = 0; 193 #endif 194 kernel_base = KERNEL_LOAD_ADDR; 195 196 kernel_size = load_elf(kernel_filename, NULL, 197 translate_kernel_address, NULL, NULL, NULL, 198 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 199 if (kernel_size < 0) 200 kernel_size = load_aout(kernel_filename, kernel_base, 201 ram_size - kernel_base, bswap_needed, 202 TARGET_PAGE_SIZE); 203 if (kernel_size < 0) 204 kernel_size = load_image_targphys(kernel_filename, 205 kernel_base, 206 ram_size - kernel_base); 207 if (kernel_size < 0) { 208 error_report("could not load kernel '%s'", kernel_filename); 209 exit(1); 210 } 211 /* load initrd */ 212 if (initrd_filename) { 213 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 214 initrd_size = load_image_targphys(initrd_filename, initrd_base, 215 ram_size - initrd_base); 216 if (initrd_size < 0) { 217 error_report("could not load initial ram disk '%s'", 218 initrd_filename); 219 exit(1); 220 } 221 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 222 } else { 223 initrd_base = 0; 224 initrd_size = 0; 225 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 226 } 227 ppc_boot_device = 'm'; 228 } else { 229 kernel_base = 0; 230 kernel_size = 0; 231 initrd_base = 0; 232 initrd_size = 0; 233 ppc_boot_device = '\0'; 234 /* We consider that NewWorld PowerMac never have any floppy drive 235 * For now, OHW cannot boot from the network. 236 */ 237 for (i = 0; boot_device[i] != '\0'; i++) { 238 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 239 ppc_boot_device = boot_device[i]; 240 break; 241 } 242 } 243 if (ppc_boot_device == '\0') { 244 error_report("No valid boot device for Mac99 machine"); 245 exit(1); 246 } 247 } 248 249 /* UniN init */ 250 dev = qdev_new(TYPE_UNI_NORTH); 251 s = SYS_BUS_DEVICE(dev); 252 sysbus_realize_and_unref(s, &error_fatal); 253 memory_region_add_subregion(get_system_memory(), 0xf8000000, 254 sysbus_mmio_get_region(s, 0)); 255 256 openpic_irqs = g_new0(IrqLines, smp_cpus); 257 for (i = 0; i < smp_cpus; i++) { 258 /* Mac99 IRQ connection between OpenPIC outputs pins 259 * and PowerPC input pins 260 */ 261 switch (PPC_INPUT(env)) { 262 case PPC_FLAGS_INPUT_6xx: 263 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 264 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 265 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 266 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 267 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 268 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 269 /* Not connected ? */ 270 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 271 /* Check this */ 272 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 273 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 274 break; 275 #if defined(TARGET_PPC64) 276 case PPC_FLAGS_INPUT_970: 277 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 278 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 279 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 280 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 281 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 282 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 283 /* Not connected ? */ 284 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 285 /* Check this */ 286 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 287 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 288 break; 289 #endif /* defined(TARGET_PPC64) */ 290 default: 291 error_report("Bus model not supported on mac99 machine"); 292 exit(1); 293 } 294 } 295 296 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 297 /* 970 gets a U3 bus */ 298 /* Uninorth AGP bus */ 299 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 300 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 301 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 302 s = SYS_BUS_DEVICE(dev); 303 /* PCI hole */ 304 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 305 sysbus_mmio_get_region(s, 2)); 306 /* Register 8 MB of ISA IO space */ 307 memory_region_add_subregion(get_system_memory(), 0xf2000000, 308 sysbus_mmio_get_region(s, 3)); 309 sysbus_mmio_map(s, 0, 0xf0800000); 310 sysbus_mmio_map(s, 1, 0xf0c00000); 311 312 machine_arch = ARCH_MAC99_U3; 313 } else { 314 /* Use values found on a real PowerMac */ 315 /* Uninorth AGP bus */ 316 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 317 s = SYS_BUS_DEVICE(uninorth_agp_dev); 318 sysbus_realize_and_unref(s, &error_fatal); 319 sysbus_mmio_map(s, 0, 0xf0800000); 320 sysbus_mmio_map(s, 1, 0xf0c00000); 321 322 /* Uninorth internal bus */ 323 uninorth_internal_dev = qdev_new( 324 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 325 s = SYS_BUS_DEVICE(uninorth_internal_dev); 326 sysbus_realize_and_unref(s, &error_fatal); 327 sysbus_mmio_map(s, 0, 0xf4800000); 328 sysbus_mmio_map(s, 1, 0xf4c00000); 329 330 /* Uninorth main bus */ 331 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 332 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 333 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 334 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 335 s = SYS_BUS_DEVICE(dev); 336 /* PCI hole */ 337 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 338 sysbus_mmio_get_region(s, 2)); 339 /* Register 8 MB of ISA IO space */ 340 memory_region_add_subregion(get_system_memory(), 0xf2000000, 341 sysbus_mmio_get_region(s, 3)); 342 sysbus_mmio_map(s, 0, 0xf2800000); 343 sysbus_mmio_map(s, 1, 0xf2c00000); 344 345 machine_arch = ARCH_MAC99; 346 } 347 348 machine->usb |= defaults_enabled() && !machine->usb_disabled; 349 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 350 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 351 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 352 353 /* Timebase Frequency */ 354 if (kvm_enabled()) { 355 tbfreq = kvmppc_get_tbfreq(); 356 } else { 357 tbfreq = TBFREQ; 358 } 359 360 /* init basic PC hardware */ 361 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 362 363 /* MacIO */ 364 macio = pci_new(-1, TYPE_NEWWORLD_MACIO); 365 dev = DEVICE(macio); 366 qdev_prop_set_uint64(dev, "frequency", tbfreq); 367 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 368 qdev_prop_set_bit(dev, "has-adb", has_adb); 369 370 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 371 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 372 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 373 374 pci_realize_and_unref(macio, pci_bus, &error_fatal); 375 376 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic")); 377 for (i = 0; i < 4; i++) { 378 qdev_connect_gpio_out(DEVICE(uninorth_pci), i, 379 qdev_get_gpio_in(pic_dev, 0x1b + i)); 380 } 381 382 /* TODO: additional PCI buses only wired up for 32-bit machines */ 383 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { 384 /* Uninorth AGP bus */ 385 for (i = 0; i < 4; i++) { 386 qdev_connect_gpio_out(uninorth_agp_dev, i, 387 qdev_get_gpio_in(pic_dev, 0x1b + i)); 388 } 389 390 /* Uninorth internal bus */ 391 for (i = 0; i < 4; i++) { 392 qdev_connect_gpio_out(uninorth_internal_dev, i, 393 qdev_get_gpio_in(pic_dev, 0x1b + i)); 394 } 395 } 396 397 /* OpenPIC */ 398 s = SYS_BUS_DEVICE(pic_dev); 399 k = 0; 400 for (i = 0; i < smp_cpus; i++) { 401 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 402 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 403 } 404 } 405 g_free(openpic_irqs); 406 407 /* We only emulate 2 out of 3 IDE controllers for now */ 408 ide_drive_get(hd, ARRAY_SIZE(hd)); 409 410 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 411 "ide[0]")); 412 macio_ide_init_drives(macio_ide, hd); 413 414 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 415 "ide[1]")); 416 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 417 418 if (has_adb) { 419 if (has_pmu) { 420 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu")); 421 } else { 422 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 423 } 424 425 adb_bus = qdev_get_child_bus(dev, "adb.0"); 426 dev = qdev_new(TYPE_ADB_KEYBOARD); 427 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 428 429 dev = qdev_new(TYPE_ADB_MOUSE); 430 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 431 } 432 433 if (machine->usb) { 434 pci_create_simple(pci_bus, -1, "pci-ohci"); 435 436 /* U3 needs to use USB for input because Linux doesn't support via-cuda 437 on PPC64 */ 438 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 439 USBBus *usb_bus = usb_bus_find(-1); 440 441 usb_create_simple(usb_bus, "usb-kbd"); 442 usb_create_simple(usb_bus, "usb-mouse"); 443 } 444 } 445 446 pci_vga_init(pci_bus); 447 448 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 449 graphic_depth = 15; 450 } 451 452 for (i = 0; i < nb_nics; i++) { 453 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL); 454 } 455 456 /* The NewWorld NVRAM is not located in the MacIO device */ 457 if (kvm_enabled() && qemu_real_host_page_size > 4096) { 458 /* We can't combine read-write and read-only in a single page, so 459 move the NVRAM out of ROM again for KVM */ 460 nvram_addr = 0xFFE00000; 461 } 462 dev = qdev_new(TYPE_MACIO_NVRAM); 463 qdev_prop_set_uint32(dev, "size", 0x2000); 464 qdev_prop_set_uint32(dev, "it_shift", 1); 465 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 466 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 467 nvr = MACIO_NVRAM(dev); 468 pmac_format_nvram_partition(nvr, 0x2000); 469 /* No PCI init: the BIOS will do it */ 470 471 dev = qdev_new(TYPE_FW_CFG_MEM); 472 fw_cfg = FW_CFG(dev); 473 qdev_prop_set_uint32(dev, "data_width", 1); 474 qdev_prop_set_bit(dev, "dma_enabled", false); 475 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 476 OBJECT(fw_cfg)); 477 s = SYS_BUS_DEVICE(dev); 478 sysbus_realize_and_unref(s, &error_fatal); 479 sysbus_mmio_map(s, 0, CFG_ADDR); 480 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 481 482 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 484 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 485 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 486 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 487 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 488 if (kernel_cmdline) { 489 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 490 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 491 } else { 492 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 493 } 494 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 495 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 496 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 497 498 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 499 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 500 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 501 502 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 503 504 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 505 if (kvm_enabled()) { 506 uint8_t *hypercall; 507 508 hypercall = g_malloc(16); 509 kvmppc_get_hypercall(env, hypercall, 16); 510 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 511 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 512 } 513 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 514 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 515 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 516 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 517 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 518 519 /* MacOS NDRV VGA driver */ 520 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 521 if (filename) { 522 gchar *ndrv_file; 523 gsize ndrv_size; 524 525 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 526 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 527 } 528 g_free(filename); 529 } 530 531 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 532 } 533 534 /* 535 * Implementation of an interface to adjust firmware path 536 * for the bootindex property handling. 537 */ 538 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 539 DeviceState *dev) 540 { 541 PCIDevice *pci; 542 MACIOIDEState *macio_ide; 543 544 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 545 pci = PCI_DEVICE(dev); 546 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 547 } 548 549 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 550 macio_ide = MACIO_IDE(dev); 551 return g_strdup_printf("ata-3@%x", macio_ide->addr); 552 } 553 554 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 555 return g_strdup("disk"); 556 } 557 558 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 559 return g_strdup("cdrom"); 560 } 561 562 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 563 return g_strdup("disk"); 564 } 565 566 return NULL; 567 } 568 static int core99_kvm_type(MachineState *machine, const char *arg) 569 { 570 /* Always force PR KVM */ 571 return 2; 572 } 573 574 static void core99_machine_class_init(ObjectClass *oc, void *data) 575 { 576 MachineClass *mc = MACHINE_CLASS(oc); 577 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 578 579 mc->desc = "Mac99 based PowerMAC"; 580 mc->init = ppc_core99_init; 581 mc->block_default_type = IF_IDE; 582 mc->max_cpus = MAX_CPUS; 583 mc->default_boot_order = "cd"; 584 mc->default_display = "std"; 585 mc->kvm_type = core99_kvm_type; 586 #ifdef TARGET_PPC64 587 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 588 #else 589 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 590 #endif 591 mc->default_ram_id = "ppc_core99.ram"; 592 mc->ignore_boot_device_suffixes = true; 593 fwc->get_dev_path = core99_fw_dev_path; 594 } 595 596 static char *core99_get_via_config(Object *obj, Error **errp) 597 { 598 Core99MachineState *cms = CORE99_MACHINE(obj); 599 600 switch (cms->via_config) { 601 default: 602 case CORE99_VIA_CONFIG_CUDA: 603 return g_strdup("cuda"); 604 605 case CORE99_VIA_CONFIG_PMU: 606 return g_strdup("pmu"); 607 608 case CORE99_VIA_CONFIG_PMU_ADB: 609 return g_strdup("pmu-adb"); 610 } 611 } 612 613 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 614 { 615 Core99MachineState *cms = CORE99_MACHINE(obj); 616 617 if (!strcmp(value, "cuda")) { 618 cms->via_config = CORE99_VIA_CONFIG_CUDA; 619 } else if (!strcmp(value, "pmu")) { 620 cms->via_config = CORE99_VIA_CONFIG_PMU; 621 } else if (!strcmp(value, "pmu-adb")) { 622 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 623 } else { 624 error_setg(errp, "Invalid via value"); 625 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 626 } 627 } 628 629 static void core99_instance_init(Object *obj) 630 { 631 Core99MachineState *cms = CORE99_MACHINE(obj); 632 633 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 634 cms->via_config = CORE99_VIA_CONFIG_CUDA; 635 object_property_add_str(obj, "via", core99_get_via_config, 636 core99_set_via_config); 637 object_property_set_description(obj, "via", 638 "Set VIA configuration. " 639 "Valid values are cuda, pmu and pmu-adb"); 640 641 return; 642 } 643 644 static const TypeInfo core99_machine_info = { 645 .name = MACHINE_TYPE_NAME("mac99"), 646 .parent = TYPE_MACHINE, 647 .class_init = core99_machine_class_init, 648 .instance_init = core99_instance_init, 649 .instance_size = sizeof(Core99MachineState), 650 .interfaces = (InterfaceInfo[]) { 651 { TYPE_FW_PATH_PROVIDER }, 652 { } 653 }, 654 }; 655 656 static void mac_machine_register_types(void) 657 { 658 type_register_static(&core99_machine_info); 659 } 660 661 type_init(mac_machine_register_types) 662