1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "hw/hw.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/ppc/mac.h" 52 #include "hw/input/adb.h" 53 #include "hw/ppc/mac_dbdma.h" 54 #include "hw/timer/m48t59.h" 55 #include "hw/pci/pci.h" 56 #include "net/net.h" 57 #include "sysemu/sysemu.h" 58 #include "hw/boards.h" 59 #include "hw/nvram/fw_cfg.h" 60 #include "hw/char/escc.h" 61 #include "hw/ppc/openpic.h" 62 #include "hw/ide.h" 63 #include "hw/loader.h" 64 #include "elf.h" 65 #include "sysemu/kvm.h" 66 #include "kvm_ppc.h" 67 #include "hw/usb.h" 68 #include "sysemu/block-backend.h" 69 #include "exec/address-spaces.h" 70 #include "hw/sysbus.h" 71 72 #define MAX_IDE_BUS 2 73 #define CFG_ADDR 0xf0000510 74 #define TBFREQ (100UL * 1000UL * 1000UL) 75 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 76 #define BUSFREQ (100UL * 1000UL * 1000UL) 77 78 /* debug UniNorth */ 79 //#define DEBUG_UNIN 80 81 #ifdef DEBUG_UNIN 82 #define UNIN_DPRINTF(fmt, ...) \ 83 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 84 #else 85 #define UNIN_DPRINTF(fmt, ...) 86 #endif 87 88 /* UniN device */ 89 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 90 unsigned size) 91 { 92 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 93 if (addr == 0x0) { 94 *(int*)opaque = value; 95 } 96 } 97 98 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 99 { 100 uint32_t value; 101 102 value = 0; 103 switch (addr) { 104 case 0: 105 value = *(int*)opaque; 106 } 107 108 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 109 110 return value; 111 } 112 113 static const MemoryRegionOps unin_ops = { 114 .read = unin_read, 115 .write = unin_write, 116 .endianness = DEVICE_NATIVE_ENDIAN, 117 }; 118 119 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 120 { 121 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 122 return 0; 123 } 124 125 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 126 { 127 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 128 } 129 130 static hwaddr round_page(hwaddr addr) 131 { 132 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 133 } 134 135 static void ppc_core99_reset(void *opaque) 136 { 137 PowerPCCPU *cpu = opaque; 138 139 cpu_reset(CPU(cpu)); 140 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 141 cpu->env.nip = PROM_ADDR + 0x100; 142 } 143 144 /* PowerPC Mac99 hardware initialisation */ 145 static void ppc_core99_init(MachineState *machine) 146 { 147 ram_addr_t ram_size = machine->ram_size; 148 const char *cpu_model = machine->cpu_model; 149 const char *kernel_filename = machine->kernel_filename; 150 const char *kernel_cmdline = machine->kernel_cmdline; 151 const char *initrd_filename = machine->initrd_filename; 152 const char *boot_device = machine->boot_order; 153 PowerPCCPU *cpu = NULL; 154 CPUPPCState *env = NULL; 155 char *filename; 156 qemu_irq *pic, **openpic_irqs; 157 MemoryRegion *isa = g_new(MemoryRegion, 1); 158 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 159 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 160 int linux_boot, i, j, k; 161 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 162 hwaddr kernel_base, initrd_base, cmdline_base = 0; 163 long kernel_size, initrd_size; 164 PCIBus *pci_bus; 165 PCIDevice *macio; 166 MACIOIDEState *macio_ide; 167 BusState *adb_bus; 168 MacIONVRAMState *nvr; 169 int bios_size; 170 MemoryRegion *pic_mem, *escc_mem; 171 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 172 int ppc_boot_device; 173 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 174 void *fw_cfg; 175 int machine_arch; 176 SysBusDevice *s; 177 DeviceState *dev; 178 int *token = g_new(int, 1); 179 hwaddr nvram_addr = 0xFFF04000; 180 uint64_t tbfreq; 181 182 linux_boot = (kernel_filename != NULL); 183 184 /* init CPUs */ 185 if (cpu_model == NULL) 186 #ifdef TARGET_PPC64 187 cpu_model = "970fx"; 188 #else 189 cpu_model = "G4"; 190 #endif 191 for (i = 0; i < smp_cpus; i++) { 192 cpu = cpu_ppc_init(cpu_model); 193 if (cpu == NULL) { 194 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 195 exit(1); 196 } 197 env = &cpu->env; 198 199 /* Set time-base frequency to 100 Mhz */ 200 cpu_ppc_tb_init(env, TBFREQ); 201 qemu_register_reset(ppc_core99_reset, cpu); 202 } 203 204 /* allocate RAM */ 205 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 206 memory_region_add_subregion(get_system_memory(), 0, ram); 207 208 /* allocate and load BIOS */ 209 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 210 &error_abort); 211 vmstate_register_ram_global(bios); 212 213 if (bios_name == NULL) 214 bios_name = PROM_FILENAME; 215 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 216 memory_region_set_readonly(bios, true); 217 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 218 219 /* Load OpenBIOS (ELF) */ 220 if (filename) { 221 bios_size = load_elf(filename, NULL, NULL, NULL, 222 NULL, NULL, 1, ELF_MACHINE, 0); 223 224 g_free(filename); 225 } else { 226 bios_size = -1; 227 } 228 if (bios_size < 0 || bios_size > BIOS_SIZE) { 229 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); 230 exit(1); 231 } 232 233 if (linux_boot) { 234 uint64_t lowaddr = 0; 235 int bswap_needed; 236 237 #ifdef BSWAP_NEEDED 238 bswap_needed = 1; 239 #else 240 bswap_needed = 0; 241 #endif 242 kernel_base = KERNEL_LOAD_ADDR; 243 244 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 245 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 246 if (kernel_size < 0) 247 kernel_size = load_aout(kernel_filename, kernel_base, 248 ram_size - kernel_base, bswap_needed, 249 TARGET_PAGE_SIZE); 250 if (kernel_size < 0) 251 kernel_size = load_image_targphys(kernel_filename, 252 kernel_base, 253 ram_size - kernel_base); 254 if (kernel_size < 0) { 255 hw_error("qemu: could not load kernel '%s'\n", kernel_filename); 256 exit(1); 257 } 258 /* load initrd */ 259 if (initrd_filename) { 260 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 261 initrd_size = load_image_targphys(initrd_filename, initrd_base, 262 ram_size - initrd_base); 263 if (initrd_size < 0) { 264 hw_error("qemu: could not load initial ram disk '%s'\n", 265 initrd_filename); 266 exit(1); 267 } 268 cmdline_base = round_page(initrd_base + initrd_size); 269 } else { 270 initrd_base = 0; 271 initrd_size = 0; 272 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 273 } 274 ppc_boot_device = 'm'; 275 } else { 276 kernel_base = 0; 277 kernel_size = 0; 278 initrd_base = 0; 279 initrd_size = 0; 280 ppc_boot_device = '\0'; 281 /* We consider that NewWorld PowerMac never have any floppy drive 282 * For now, OHW cannot boot from the network. 283 */ 284 for (i = 0; boot_device[i] != '\0'; i++) { 285 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 286 ppc_boot_device = boot_device[i]; 287 break; 288 } 289 } 290 if (ppc_boot_device == '\0') { 291 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 292 exit(1); 293 } 294 } 295 296 /* Register 8 MB of ISA IO space */ 297 memory_region_init_alias(isa, NULL, "isa_mmio", 298 get_system_io(), 0, 0x00800000); 299 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 300 301 /* UniN init: XXX should be a real device */ 302 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 303 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 304 305 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 306 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 307 308 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 309 openpic_irqs[0] = 310 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 311 for (i = 0; i < smp_cpus; i++) { 312 /* Mac99 IRQ connection between OpenPIC outputs pins 313 * and PowerPC input pins 314 */ 315 switch (PPC_INPUT(env)) { 316 case PPC_FLAGS_INPUT_6xx: 317 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 318 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 319 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 320 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 321 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 322 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 323 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 324 /* Not connected ? */ 325 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 326 /* Check this */ 327 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 328 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 329 break; 330 #if defined(TARGET_PPC64) 331 case PPC_FLAGS_INPUT_970: 332 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 333 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 334 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 335 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 336 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 337 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 338 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 339 /* Not connected ? */ 340 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 341 /* Check this */ 342 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 343 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 344 break; 345 #endif /* defined(TARGET_PPC64) */ 346 default: 347 hw_error("Bus model not supported on mac99 machine\n"); 348 exit(1); 349 } 350 } 351 352 pic = g_new0(qemu_irq, 64); 353 354 dev = qdev_create(NULL, TYPE_OPENPIC); 355 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 356 qdev_init_nofail(dev); 357 s = SYS_BUS_DEVICE(dev); 358 pic_mem = s->mmio[0].memory; 359 k = 0; 360 for (i = 0; i < smp_cpus; i++) { 361 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 362 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 363 } 364 } 365 366 for (i = 0; i < 64; i++) { 367 pic[i] = qdev_get_gpio_in(dev, i); 368 } 369 370 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 371 /* 970 gets a U3 bus */ 372 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 373 machine_arch = ARCH_MAC99_U3; 374 } else { 375 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 376 machine_arch = ARCH_MAC99; 377 } 378 379 /* Timebase Frequency */ 380 if (kvm_enabled()) { 381 tbfreq = kvmppc_get_tbfreq(); 382 } else { 383 tbfreq = TBFREQ; 384 } 385 386 /* init basic PC hardware */ 387 escc_mem = escc_init(0, pic[0x25], pic[0x24], 388 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 389 memory_region_init_alias(escc_bar, NULL, "escc-bar", 390 escc_mem, 0, memory_region_size(escc_mem)); 391 392 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 393 dev = DEVICE(macio); 394 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 395 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 396 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 397 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 398 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 399 qdev_prop_set_uint64(dev, "frequency", tbfreq); 400 macio_init(macio, pic_mem, escc_bar); 401 402 /* We only emulate 2 out of 3 IDE controllers for now */ 403 ide_drive_get(hd, ARRAY_SIZE(hd)); 404 405 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 406 "ide[0]")); 407 macio_ide_init_drives(macio_ide, hd); 408 409 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 410 "ide[1]")); 411 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 412 413 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 414 adb_bus = qdev_get_child_bus(dev, "adb.0"); 415 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 416 qdev_init_nofail(dev); 417 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 418 qdev_init_nofail(dev); 419 420 if (usb_enabled(machine_arch == ARCH_MAC99_U3)) { 421 pci_create_simple(pci_bus, -1, "pci-ohci"); 422 /* U3 needs to use USB for input because Linux doesn't support via-cuda 423 on PPC64 */ 424 if (machine_arch == ARCH_MAC99_U3) { 425 usbdevice_create("keyboard"); 426 usbdevice_create("mouse"); 427 } 428 } 429 430 pci_vga_init(pci_bus); 431 432 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 433 graphic_depth = 15; 434 } 435 436 for (i = 0; i < nb_nics; i++) { 437 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 438 } 439 440 /* The NewWorld NVRAM is not located in the MacIO device */ 441 #ifdef CONFIG_KVM 442 if (kvm_enabled() && getpagesize() > 4096) { 443 /* We can't combine read-write and read-only in a single page, so 444 move the NVRAM out of ROM again for KVM */ 445 nvram_addr = 0xFFE00000; 446 } 447 #endif 448 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 449 qdev_prop_set_uint32(dev, "size", 0x2000); 450 qdev_prop_set_uint32(dev, "it_shift", 1); 451 qdev_init_nofail(dev); 452 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 453 nvr = MACIO_NVRAM(dev); 454 pmac_format_nvram_partition(nvr, 0x2000); 455 /* No PCI init: the BIOS will do it */ 456 457 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 458 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 459 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 460 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 461 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 462 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 463 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 464 if (kernel_cmdline) { 465 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 466 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 467 } else { 468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 469 } 470 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 471 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 472 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 473 474 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 475 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 476 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 477 478 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 479 if (kvm_enabled()) { 480 #ifdef CONFIG_KVM 481 uint8_t *hypercall; 482 483 hypercall = g_malloc(16); 484 kvmppc_get_hypercall(env, hypercall, 16); 485 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 486 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 487 #endif 488 } 489 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 490 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 491 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 492 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 493 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 494 495 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 496 } 497 498 static int core99_kvm_type(const char *arg) 499 { 500 /* Always force PR KVM */ 501 return 2; 502 } 503 504 static QEMUMachine core99_machine = { 505 .name = "mac99", 506 .desc = "Mac99 based PowerMAC", 507 .init = ppc_core99_init, 508 .max_cpus = MAX_CPUS, 509 .default_boot_order = "cd", 510 .kvm_type = core99_kvm_type, 511 }; 512 513 static void core99_machine_init(void) 514 { 515 qemu_register_machine(&core99_machine); 516 } 517 518 machine_init(core99_machine_init); 519