1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/ppc/openpic.h" 64 #include "hw/ide.h" 65 #include "hw/loader.h" 66 #include "elf.h" 67 #include "qemu/error-report.h" 68 #include "sysemu/kvm.h" 69 #include "kvm_ppc.h" 70 #include "hw/usb.h" 71 #include "sysemu/block-backend.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 #include "qemu/cutils.h" 75 76 #define MAX_IDE_BUS 2 77 #define CFG_ADDR 0xf0000510 78 #define TBFREQ (100UL * 1000UL * 1000UL) 79 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 80 #define BUSFREQ (100UL * 1000UL * 1000UL) 81 82 /* debug UniNorth */ 83 //#define DEBUG_UNIN 84 85 #ifdef DEBUG_UNIN 86 #define UNIN_DPRINTF(fmt, ...) \ 87 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 88 #else 89 #define UNIN_DPRINTF(fmt, ...) 90 #endif 91 92 /* UniN device */ 93 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 94 unsigned size) 95 { 96 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 97 if (addr == 0x0) { 98 *(int*)opaque = value; 99 } 100 } 101 102 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 103 { 104 uint32_t value; 105 106 value = 0; 107 switch (addr) { 108 case 0: 109 value = *(int*)opaque; 110 } 111 112 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 113 114 return value; 115 } 116 117 static const MemoryRegionOps unin_ops = { 118 .read = unin_read, 119 .write = unin_write, 120 .endianness = DEVICE_NATIVE_ENDIAN, 121 }; 122 123 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 124 Error **errp) 125 { 126 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 127 } 128 129 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 130 { 131 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 132 } 133 134 static hwaddr round_page(hwaddr addr) 135 { 136 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 137 } 138 139 static void ppc_core99_reset(void *opaque) 140 { 141 PowerPCCPU *cpu = opaque; 142 143 cpu_reset(CPU(cpu)); 144 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 145 cpu->env.nip = PROM_ADDR + 0x100; 146 } 147 148 /* PowerPC Mac99 hardware initialisation */ 149 static void ppc_core99_init(MachineState *machine) 150 { 151 ram_addr_t ram_size = machine->ram_size; 152 const char *kernel_filename = machine->kernel_filename; 153 const char *kernel_cmdline = machine->kernel_cmdline; 154 const char *initrd_filename = machine->initrd_filename; 155 const char *boot_device = machine->boot_order; 156 PowerPCCPU *cpu = NULL; 157 CPUPPCState *env = NULL; 158 char *filename; 159 qemu_irq *pic, **openpic_irqs; 160 MemoryRegion *isa = g_new(MemoryRegion, 1); 161 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 162 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 163 int linux_boot, i, j, k; 164 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 165 hwaddr kernel_base, initrd_base, cmdline_base = 0; 166 long kernel_size, initrd_size; 167 PCIBus *pci_bus; 168 PCIDevice *macio; 169 MACIOIDEState *macio_ide; 170 BusState *adb_bus; 171 MacIONVRAMState *nvr; 172 int bios_size; 173 MemoryRegion *pic_mem, *escc_mem; 174 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 175 int ppc_boot_device; 176 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 177 void *fw_cfg; 178 int machine_arch; 179 SysBusDevice *s; 180 DeviceState *dev; 181 int *token = g_new(int, 1); 182 hwaddr nvram_addr = 0xFFF04000; 183 uint64_t tbfreq; 184 185 linux_boot = (kernel_filename != NULL); 186 187 /* init CPUs */ 188 if (machine->cpu_model == NULL) { 189 #ifdef TARGET_PPC64 190 machine->cpu_model = "970fx"; 191 #else 192 machine->cpu_model = "G4"; 193 #endif 194 } 195 for (i = 0; i < smp_cpus; i++) { 196 cpu = cpu_ppc_init(machine->cpu_model); 197 if (cpu == NULL) { 198 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 199 exit(1); 200 } 201 env = &cpu->env; 202 203 /* Set time-base frequency to 100 Mhz */ 204 cpu_ppc_tb_init(env, TBFREQ); 205 qemu_register_reset(ppc_core99_reset, cpu); 206 } 207 208 /* allocate RAM */ 209 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 210 memory_region_add_subregion(get_system_memory(), 0, ram); 211 212 /* allocate and load BIOS */ 213 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 214 &error_fatal); 215 vmstate_register_ram_global(bios); 216 217 if (bios_name == NULL) 218 bios_name = PROM_FILENAME; 219 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 220 memory_region_set_readonly(bios, true); 221 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 222 223 /* Load OpenBIOS (ELF) */ 224 if (filename) { 225 bios_size = load_elf(filename, NULL, NULL, NULL, 226 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 227 228 g_free(filename); 229 } else { 230 bios_size = -1; 231 } 232 if (bios_size < 0 || bios_size > BIOS_SIZE) { 233 error_report("could not load PowerPC bios '%s'", bios_name); 234 exit(1); 235 } 236 237 if (linux_boot) { 238 uint64_t lowaddr = 0; 239 int bswap_needed; 240 241 #ifdef BSWAP_NEEDED 242 bswap_needed = 1; 243 #else 244 bswap_needed = 0; 245 #endif 246 kernel_base = KERNEL_LOAD_ADDR; 247 248 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 249 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 250 0, 0); 251 if (kernel_size < 0) 252 kernel_size = load_aout(kernel_filename, kernel_base, 253 ram_size - kernel_base, bswap_needed, 254 TARGET_PAGE_SIZE); 255 if (kernel_size < 0) 256 kernel_size = load_image_targphys(kernel_filename, 257 kernel_base, 258 ram_size - kernel_base); 259 if (kernel_size < 0) { 260 error_report("could not load kernel '%s'", kernel_filename); 261 exit(1); 262 } 263 /* load initrd */ 264 if (initrd_filename) { 265 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 266 initrd_size = load_image_targphys(initrd_filename, initrd_base, 267 ram_size - initrd_base); 268 if (initrd_size < 0) { 269 error_report("could not load initial ram disk '%s'", 270 initrd_filename); 271 exit(1); 272 } 273 cmdline_base = round_page(initrd_base + initrd_size); 274 } else { 275 initrd_base = 0; 276 initrd_size = 0; 277 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 278 } 279 ppc_boot_device = 'm'; 280 } else { 281 kernel_base = 0; 282 kernel_size = 0; 283 initrd_base = 0; 284 initrd_size = 0; 285 ppc_boot_device = '\0'; 286 /* We consider that NewWorld PowerMac never have any floppy drive 287 * For now, OHW cannot boot from the network. 288 */ 289 for (i = 0; boot_device[i] != '\0'; i++) { 290 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 291 ppc_boot_device = boot_device[i]; 292 break; 293 } 294 } 295 if (ppc_boot_device == '\0') { 296 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 297 exit(1); 298 } 299 } 300 301 /* Register 8 MB of ISA IO space */ 302 memory_region_init_alias(isa, NULL, "isa_mmio", 303 get_system_io(), 0, 0x00800000); 304 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 305 306 /* UniN init: XXX should be a real device */ 307 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 308 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 309 310 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 311 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 312 313 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 314 openpic_irqs[0] = 315 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 316 for (i = 0; i < smp_cpus; i++) { 317 /* Mac99 IRQ connection between OpenPIC outputs pins 318 * and PowerPC input pins 319 */ 320 switch (PPC_INPUT(env)) { 321 case PPC_FLAGS_INPUT_6xx: 322 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 323 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 324 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 325 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 326 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 327 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 328 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 329 /* Not connected ? */ 330 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 331 /* Check this */ 332 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 333 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 334 break; 335 #if defined(TARGET_PPC64) 336 case PPC_FLAGS_INPUT_970: 337 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 338 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 339 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 340 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 341 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 342 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 343 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 344 /* Not connected ? */ 345 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 346 /* Check this */ 347 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 348 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 349 break; 350 #endif /* defined(TARGET_PPC64) */ 351 default: 352 error_report("Bus model not supported on mac99 machine"); 353 exit(1); 354 } 355 } 356 357 pic = g_new0(qemu_irq, 64); 358 359 dev = qdev_create(NULL, TYPE_OPENPIC); 360 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 361 qdev_init_nofail(dev); 362 s = SYS_BUS_DEVICE(dev); 363 pic_mem = s->mmio[0].memory; 364 k = 0; 365 for (i = 0; i < smp_cpus; i++) { 366 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 367 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 368 } 369 } 370 371 for (i = 0; i < 64; i++) { 372 pic[i] = qdev_get_gpio_in(dev, i); 373 } 374 375 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 376 /* 970 gets a U3 bus */ 377 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 378 machine_arch = ARCH_MAC99_U3; 379 } else { 380 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 381 machine_arch = ARCH_MAC99; 382 } 383 object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort); 384 385 machine->usb |= defaults_enabled() && !machine->usb_disabled; 386 387 /* Timebase Frequency */ 388 if (kvm_enabled()) { 389 tbfreq = kvmppc_get_tbfreq(); 390 } else { 391 tbfreq = TBFREQ; 392 } 393 394 /* init basic PC hardware */ 395 escc_mem = escc_init(0, pic[0x25], pic[0x24], 396 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 397 memory_region_init_alias(escc_bar, NULL, "escc-bar", 398 escc_mem, 0, memory_region_size(escc_mem)); 399 400 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 401 dev = DEVICE(macio); 402 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 403 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 404 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 405 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 406 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 407 qdev_prop_set_uint64(dev, "frequency", tbfreq); 408 macio_init(macio, pic_mem, escc_bar); 409 410 /* We only emulate 2 out of 3 IDE controllers for now */ 411 ide_drive_get(hd, ARRAY_SIZE(hd)); 412 413 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 414 "ide[0]")); 415 macio_ide_init_drives(macio_ide, hd); 416 417 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 418 "ide[1]")); 419 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 420 421 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 422 adb_bus = qdev_get_child_bus(dev, "adb.0"); 423 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 424 qdev_init_nofail(dev); 425 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 426 qdev_init_nofail(dev); 427 428 if (machine->usb) { 429 pci_create_simple(pci_bus, -1, "pci-ohci"); 430 431 /* U3 needs to use USB for input because Linux doesn't support via-cuda 432 on PPC64 */ 433 if (machine_arch == ARCH_MAC99_U3) { 434 USBBus *usb_bus = usb_bus_find(-1); 435 436 usb_create_simple(usb_bus, "usb-kbd"); 437 usb_create_simple(usb_bus, "usb-mouse"); 438 } 439 } 440 441 pci_vga_init(pci_bus); 442 443 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 444 graphic_depth = 15; 445 } 446 447 for (i = 0; i < nb_nics; i++) { 448 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 449 } 450 451 /* The NewWorld NVRAM is not located in the MacIO device */ 452 #ifdef CONFIG_KVM 453 if (kvm_enabled() && getpagesize() > 4096) { 454 /* We can't combine read-write and read-only in a single page, so 455 move the NVRAM out of ROM again for KVM */ 456 nvram_addr = 0xFFE00000; 457 } 458 #endif 459 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 460 qdev_prop_set_uint32(dev, "size", 0x2000); 461 qdev_prop_set_uint32(dev, "it_shift", 1); 462 qdev_init_nofail(dev); 463 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 464 nvr = MACIO_NVRAM(dev); 465 pmac_format_nvram_partition(nvr, 0x2000); 466 /* No PCI init: the BIOS will do it */ 467 468 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 469 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 470 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 471 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 472 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 473 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 474 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 475 if (kernel_cmdline) { 476 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 477 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 478 } else { 479 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 480 } 481 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 482 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 484 485 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 486 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 487 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 488 489 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 490 if (kvm_enabled()) { 491 #ifdef CONFIG_KVM 492 uint8_t *hypercall; 493 494 hypercall = g_malloc(16); 495 kvmppc_get_hypercall(env, hypercall, 16); 496 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 497 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 498 #endif 499 } 500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 501 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 502 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 503 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 504 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 505 506 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 507 } 508 509 static int core99_kvm_type(const char *arg) 510 { 511 /* Always force PR KVM */ 512 return 2; 513 } 514 515 static void core99_machine_class_init(ObjectClass *oc, void *data) 516 { 517 MachineClass *mc = MACHINE_CLASS(oc); 518 519 mc->desc = "Mac99 based PowerMAC"; 520 mc->init = ppc_core99_init; 521 mc->max_cpus = MAX_CPUS; 522 mc->default_boot_order = "cd"; 523 mc->kvm_type = core99_kvm_type; 524 } 525 526 static const TypeInfo core99_machine_info = { 527 .name = MACHINE_TYPE_NAME("mac99"), 528 .parent = TYPE_MACHINE, 529 .class_init = core99_machine_class_init, 530 }; 531 532 static void mac_machine_register_types(void) 533 { 534 type_register_static(&core99_machine_info); 535 } 536 537 type_init(mac_machine_register_types) 538