1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu-common.h" 51 #include "qapi/error.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/qdev-properties.h" 54 #include "hw/ppc/mac.h" 55 #include "hw/input/adb.h" 56 #include "hw/ppc/mac_dbdma.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/misc/macio/macio.h" 64 #include "hw/ppc/openpic.h" 65 #include "hw/loader.h" 66 #include "hw/fw-path-provider.h" 67 #include "elf.h" 68 #include "qemu/error-report.h" 69 #include "sysemu/kvm.h" 70 #include "sysemu/reset.h" 71 #include "kvm_ppc.h" 72 #include "hw/usb.h" 73 #include "exec/address-spaces.h" 74 #include "hw/sysbus.h" 75 #include "trace.h" 76 77 #define MAX_IDE_BUS 2 78 #define CFG_ADDR 0xf0000510 79 #define TBFREQ (100UL * 1000UL * 1000UL) 80 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 81 #define BUSFREQ (100UL * 1000UL * 1000UL) 82 83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 84 85 #define PROM_BASE 0xfff00000 86 #define PROM_SIZE (1 * MiB) 87 88 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 89 Error **errp) 90 { 91 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 92 } 93 94 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 95 { 96 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 97 } 98 99 static void ppc_core99_reset(void *opaque) 100 { 101 PowerPCCPU *cpu = opaque; 102 103 cpu_reset(CPU(cpu)); 104 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 105 cpu->env.nip = PROM_BASE + 0x100; 106 } 107 108 /* PowerPC Mac99 hardware initialisation */ 109 static void ppc_core99_init(MachineState *machine) 110 { 111 ram_addr_t ram_size = machine->ram_size; 112 const char *bios_name = machine->firmware ?: PROM_FILENAME; 113 const char *kernel_filename = machine->kernel_filename; 114 const char *kernel_cmdline = machine->kernel_cmdline; 115 const char *initrd_filename = machine->initrd_filename; 116 const char *boot_device = machine->boot_order; 117 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 118 PowerPCCPU *cpu = NULL; 119 CPUPPCState *env = NULL; 120 char *filename; 121 IrqLines *openpic_irqs; 122 int linux_boot, i, j, k; 123 MemoryRegion *bios = g_new(MemoryRegion, 1); 124 hwaddr kernel_base, initrd_base, cmdline_base = 0; 125 long kernel_size, initrd_size; 126 UNINHostState *uninorth_pci; 127 PCIBus *pci_bus; 128 PCIDevice *macio; 129 ESCCState *escc; 130 bool has_pmu, has_adb; 131 MACIOIDEState *macio_ide; 132 BusState *adb_bus; 133 MacIONVRAMState *nvr; 134 int bios_size; 135 int ppc_boot_device; 136 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 137 void *fw_cfg; 138 int machine_arch; 139 SysBusDevice *s; 140 DeviceState *dev, *pic_dev; 141 hwaddr nvram_addr = 0xFFF04000; 142 uint64_t tbfreq; 143 unsigned int smp_cpus = machine->smp.cpus; 144 145 linux_boot = (kernel_filename != NULL); 146 147 /* init CPUs */ 148 for (i = 0; i < smp_cpus; i++) { 149 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 150 env = &cpu->env; 151 152 /* Set time-base frequency to 100 Mhz */ 153 cpu_ppc_tb_init(env, TBFREQ); 154 qemu_register_reset(ppc_core99_reset, cpu); 155 } 156 157 /* allocate RAM */ 158 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 159 160 /* allocate and load firmware ROM */ 161 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 162 &error_fatal); 163 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 164 165 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 166 if (filename) { 167 /* Load OpenBIOS (ELF) */ 168 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 169 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 170 171 if (bios_size <= 0) { 172 /* or load binary ROM image */ 173 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 174 } 175 g_free(filename); 176 } else { 177 bios_size = -1; 178 } 179 if (bios_size < 0 || bios_size > PROM_SIZE) { 180 error_report("could not load PowerPC bios '%s'", bios_name); 181 exit(1); 182 } 183 184 if (linux_boot) { 185 int bswap_needed; 186 187 #ifdef BSWAP_NEEDED 188 bswap_needed = 1; 189 #else 190 bswap_needed = 0; 191 #endif 192 kernel_base = KERNEL_LOAD_ADDR; 193 194 kernel_size = load_elf(kernel_filename, NULL, 195 translate_kernel_address, NULL, NULL, NULL, 196 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 197 if (kernel_size < 0) 198 kernel_size = load_aout(kernel_filename, kernel_base, 199 ram_size - kernel_base, bswap_needed, 200 TARGET_PAGE_SIZE); 201 if (kernel_size < 0) 202 kernel_size = load_image_targphys(kernel_filename, 203 kernel_base, 204 ram_size - kernel_base); 205 if (kernel_size < 0) { 206 error_report("could not load kernel '%s'", kernel_filename); 207 exit(1); 208 } 209 /* load initrd */ 210 if (initrd_filename) { 211 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 212 initrd_size = load_image_targphys(initrd_filename, initrd_base, 213 ram_size - initrd_base); 214 if (initrd_size < 0) { 215 error_report("could not load initial ram disk '%s'", 216 initrd_filename); 217 exit(1); 218 } 219 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 220 } else { 221 initrd_base = 0; 222 initrd_size = 0; 223 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 224 } 225 ppc_boot_device = 'm'; 226 } else { 227 kernel_base = 0; 228 kernel_size = 0; 229 initrd_base = 0; 230 initrd_size = 0; 231 ppc_boot_device = '\0'; 232 /* We consider that NewWorld PowerMac never have any floppy drive 233 * For now, OHW cannot boot from the network. 234 */ 235 for (i = 0; boot_device[i] != '\0'; i++) { 236 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 237 ppc_boot_device = boot_device[i]; 238 break; 239 } 240 } 241 if (ppc_boot_device == '\0') { 242 error_report("No valid boot device for Mac99 machine"); 243 exit(1); 244 } 245 } 246 247 /* UniN init */ 248 dev = qdev_new(TYPE_UNI_NORTH); 249 s = SYS_BUS_DEVICE(dev); 250 sysbus_realize_and_unref(s, &error_fatal); 251 memory_region_add_subregion(get_system_memory(), 0xf8000000, 252 sysbus_mmio_get_region(s, 0)); 253 254 openpic_irqs = g_new0(IrqLines, smp_cpus); 255 for (i = 0; i < smp_cpus; i++) { 256 /* Mac99 IRQ connection between OpenPIC outputs pins 257 * and PowerPC input pins 258 */ 259 switch (PPC_INPUT(env)) { 260 case PPC_FLAGS_INPUT_6xx: 261 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 262 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 263 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 264 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 265 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 266 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 267 /* Not connected ? */ 268 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 269 /* Check this */ 270 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 271 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 272 break; 273 #if defined(TARGET_PPC64) 274 case PPC_FLAGS_INPUT_970: 275 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 276 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 277 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 278 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 279 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 280 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 281 /* Not connected ? */ 282 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 283 /* Check this */ 284 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 285 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 286 break; 287 #endif /* defined(TARGET_PPC64) */ 288 default: 289 error_report("Bus model not supported on mac99 machine"); 290 exit(1); 291 } 292 } 293 294 pic_dev = qdev_new(TYPE_OPENPIC); 295 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 296 s = SYS_BUS_DEVICE(pic_dev); 297 sysbus_realize_and_unref(s, &error_fatal); 298 k = 0; 299 for (i = 0; i < smp_cpus; i++) { 300 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 301 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 302 } 303 } 304 g_free(openpic_irqs); 305 306 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 307 /* 970 gets a U3 bus */ 308 /* Uninorth AGP bus */ 309 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 310 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 311 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 312 s = SYS_BUS_DEVICE(dev); 313 /* PCI hole */ 314 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 315 sysbus_mmio_get_region(s, 2)); 316 /* Register 8 MB of ISA IO space */ 317 memory_region_add_subregion(get_system_memory(), 0xf2000000, 318 sysbus_mmio_get_region(s, 3)); 319 sysbus_mmio_map(s, 0, 0xf0800000); 320 sysbus_mmio_map(s, 1, 0xf0c00000); 321 322 for (i = 0; i < 4; i++) { 323 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i)); 324 } 325 326 machine_arch = ARCH_MAC99_U3; 327 } else { 328 /* Use values found on a real PowerMac */ 329 /* Uninorth AGP bus */ 330 dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 331 s = SYS_BUS_DEVICE(dev); 332 sysbus_realize_and_unref(s, &error_fatal); 333 sysbus_mmio_map(s, 0, 0xf0800000); 334 sysbus_mmio_map(s, 1, 0xf0c00000); 335 336 for (i = 0; i < 4; i++) { 337 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i)); 338 } 339 340 /* Uninorth internal bus */ 341 dev = qdev_new(TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 342 s = SYS_BUS_DEVICE(dev); 343 sysbus_realize_and_unref(s, &error_fatal); 344 sysbus_mmio_map(s, 0, 0xf4800000); 345 sysbus_mmio_map(s, 1, 0xf4c00000); 346 347 for (i = 0; i < 4; i++) { 348 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i)); 349 } 350 351 /* Uninorth main bus */ 352 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 353 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 354 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 355 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 356 s = SYS_BUS_DEVICE(dev); 357 /* PCI hole */ 358 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 359 sysbus_mmio_get_region(s, 2)); 360 /* Register 8 MB of ISA IO space */ 361 memory_region_add_subregion(get_system_memory(), 0xf2000000, 362 sysbus_mmio_get_region(s, 3)); 363 sysbus_mmio_map(s, 0, 0xf2800000); 364 sysbus_mmio_map(s, 1, 0xf2c00000); 365 366 for (i = 0; i < 4; i++) { 367 qdev_connect_gpio_out(dev, i, qdev_get_gpio_in(pic_dev, 0x1b + i)); 368 } 369 370 machine_arch = ARCH_MAC99; 371 } 372 373 machine->usb |= defaults_enabled() && !machine->usb_disabled; 374 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 375 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 376 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 377 378 /* Timebase Frequency */ 379 if (kvm_enabled()) { 380 tbfreq = kvmppc_get_tbfreq(); 381 } else { 382 tbfreq = TBFREQ; 383 } 384 385 /* init basic PC hardware */ 386 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 387 388 /* MacIO */ 389 macio = pci_new(-1, TYPE_NEWWORLD_MACIO); 390 dev = DEVICE(macio); 391 qdev_prop_set_uint64(dev, "frequency", tbfreq); 392 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 393 qdev_prop_set_bit(dev, "has-adb", has_adb); 394 object_property_set_link(OBJECT(macio), "pic", OBJECT(pic_dev), 395 &error_abort); 396 397 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 398 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 399 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 400 401 pci_realize_and_unref(macio, pci_bus, &error_fatal); 402 403 /* We only emulate 2 out of 3 IDE controllers for now */ 404 ide_drive_get(hd, ARRAY_SIZE(hd)); 405 406 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 407 "ide[0]")); 408 macio_ide_init_drives(macio_ide, hd); 409 410 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 411 "ide[1]")); 412 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 413 414 if (has_adb) { 415 if (has_pmu) { 416 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu")); 417 } else { 418 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 419 } 420 421 adb_bus = qdev_get_child_bus(dev, "adb.0"); 422 dev = qdev_new(TYPE_ADB_KEYBOARD); 423 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 424 425 dev = qdev_new(TYPE_ADB_MOUSE); 426 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 427 } 428 429 if (machine->usb) { 430 pci_create_simple(pci_bus, -1, "pci-ohci"); 431 432 /* U3 needs to use USB for input because Linux doesn't support via-cuda 433 on PPC64 */ 434 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 435 USBBus *usb_bus = usb_bus_find(-1); 436 437 usb_create_simple(usb_bus, "usb-kbd"); 438 usb_create_simple(usb_bus, "usb-mouse"); 439 } 440 } 441 442 pci_vga_init(pci_bus); 443 444 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 445 graphic_depth = 15; 446 } 447 448 for (i = 0; i < nb_nics; i++) { 449 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL); 450 } 451 452 /* The NewWorld NVRAM is not located in the MacIO device */ 453 if (kvm_enabled() && qemu_real_host_page_size > 4096) { 454 /* We can't combine read-write and read-only in a single page, so 455 move the NVRAM out of ROM again for KVM */ 456 nvram_addr = 0xFFE00000; 457 } 458 dev = qdev_new(TYPE_MACIO_NVRAM); 459 qdev_prop_set_uint32(dev, "size", 0x2000); 460 qdev_prop_set_uint32(dev, "it_shift", 1); 461 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 462 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 463 nvr = MACIO_NVRAM(dev); 464 pmac_format_nvram_partition(nvr, 0x2000); 465 /* No PCI init: the BIOS will do it */ 466 467 dev = qdev_new(TYPE_FW_CFG_MEM); 468 fw_cfg = FW_CFG(dev); 469 qdev_prop_set_uint32(dev, "data_width", 1); 470 qdev_prop_set_bit(dev, "dma_enabled", false); 471 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 472 OBJECT(fw_cfg)); 473 s = SYS_BUS_DEVICE(dev); 474 sysbus_realize_and_unref(s, &error_fatal); 475 sysbus_mmio_map(s, 0, CFG_ADDR); 476 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 477 478 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 479 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 480 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 481 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 482 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 483 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 484 if (kernel_cmdline) { 485 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 486 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 487 } else { 488 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 489 } 490 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 491 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 492 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 493 494 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 495 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 496 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 497 498 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 499 500 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 501 if (kvm_enabled()) { 502 uint8_t *hypercall; 503 504 hypercall = g_malloc(16); 505 kvmppc_get_hypercall(env, hypercall, 16); 506 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 507 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 508 } 509 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 510 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 511 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 512 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 513 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 514 515 /* MacOS NDRV VGA driver */ 516 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 517 if (filename) { 518 gchar *ndrv_file; 519 gsize ndrv_size; 520 521 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 522 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 523 } 524 g_free(filename); 525 } 526 527 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 528 } 529 530 /* 531 * Implementation of an interface to adjust firmware path 532 * for the bootindex property handling. 533 */ 534 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 535 DeviceState *dev) 536 { 537 PCIDevice *pci; 538 IDEBus *ide_bus; 539 IDEState *ide_s; 540 MACIOIDEState *macio_ide; 541 542 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 543 pci = PCI_DEVICE(dev); 544 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 545 } 546 547 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 548 macio_ide = MACIO_IDE(dev); 549 return g_strdup_printf("ata-3@%x", macio_ide->addr); 550 } 551 552 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-drive")) { 553 ide_bus = IDE_BUS(qdev_get_parent_bus(dev)); 554 ide_s = idebus_active_if(ide_bus); 555 556 if (ide_s->drive_kind == IDE_CD) { 557 return g_strdup("cdrom"); 558 } 559 560 return g_strdup("disk"); 561 } 562 563 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 564 return g_strdup("disk"); 565 } 566 567 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 568 return g_strdup("cdrom"); 569 } 570 571 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 572 return g_strdup("disk"); 573 } 574 575 return NULL; 576 } 577 static int core99_kvm_type(MachineState *machine, const char *arg) 578 { 579 /* Always force PR KVM */ 580 return 2; 581 } 582 583 static void core99_machine_class_init(ObjectClass *oc, void *data) 584 { 585 MachineClass *mc = MACHINE_CLASS(oc); 586 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 587 588 mc->desc = "Mac99 based PowerMAC"; 589 mc->init = ppc_core99_init; 590 mc->block_default_type = IF_IDE; 591 mc->max_cpus = MAX_CPUS; 592 mc->default_boot_order = "cd"; 593 mc->default_display = "std"; 594 mc->kvm_type = core99_kvm_type; 595 #ifdef TARGET_PPC64 596 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 597 #else 598 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 599 #endif 600 mc->default_ram_id = "ppc_core99.ram"; 601 mc->ignore_boot_device_suffixes = true; 602 fwc->get_dev_path = core99_fw_dev_path; 603 } 604 605 static char *core99_get_via_config(Object *obj, Error **errp) 606 { 607 Core99MachineState *cms = CORE99_MACHINE(obj); 608 609 switch (cms->via_config) { 610 default: 611 case CORE99_VIA_CONFIG_CUDA: 612 return g_strdup("cuda"); 613 614 case CORE99_VIA_CONFIG_PMU: 615 return g_strdup("pmu"); 616 617 case CORE99_VIA_CONFIG_PMU_ADB: 618 return g_strdup("pmu-adb"); 619 } 620 } 621 622 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 623 { 624 Core99MachineState *cms = CORE99_MACHINE(obj); 625 626 if (!strcmp(value, "cuda")) { 627 cms->via_config = CORE99_VIA_CONFIG_CUDA; 628 } else if (!strcmp(value, "pmu")) { 629 cms->via_config = CORE99_VIA_CONFIG_PMU; 630 } else if (!strcmp(value, "pmu-adb")) { 631 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 632 } else { 633 error_setg(errp, "Invalid via value"); 634 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 635 } 636 } 637 638 static void core99_instance_init(Object *obj) 639 { 640 Core99MachineState *cms = CORE99_MACHINE(obj); 641 642 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 643 cms->via_config = CORE99_VIA_CONFIG_CUDA; 644 object_property_add_str(obj, "via", core99_get_via_config, 645 core99_set_via_config); 646 object_property_set_description(obj, "via", 647 "Set VIA configuration. " 648 "Valid values are cuda, pmu and pmu-adb"); 649 650 return; 651 } 652 653 static const TypeInfo core99_machine_info = { 654 .name = MACHINE_TYPE_NAME("mac99"), 655 .parent = TYPE_MACHINE, 656 .class_init = core99_machine_class_init, 657 .instance_init = core99_instance_init, 658 .instance_size = sizeof(Core99MachineState), 659 .interfaces = (InterfaceInfo[]) { 660 { TYPE_FW_PATH_PROVIDER }, 661 { } 662 }, 663 }; 664 665 static void mac_machine_register_types(void) 666 { 667 type_register_static(&core99_machine_info); 668 } 669 670 type_init(mac_machine_register_types) 671