1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 */ 48 49 #include "qemu/osdep.h" 50 #include "qemu-common.h" 51 #include "qemu/datadir.h" 52 #include "qapi/error.h" 53 #include "hw/ppc/ppc.h" 54 #include "hw/qdev-properties.h" 55 #include "hw/ppc/mac.h" 56 #include "hw/input/adb.h" 57 #include "hw/ppc/mac_dbdma.h" 58 #include "hw/pci/pci.h" 59 #include "net/net.h" 60 #include "sysemu/sysemu.h" 61 #include "hw/boards.h" 62 #include "hw/nvram/fw_cfg.h" 63 #include "hw/char/escc.h" 64 #include "hw/misc/macio/macio.h" 65 #include "hw/ppc/openpic.h" 66 #include "hw/loader.h" 67 #include "hw/fw-path-provider.h" 68 #include "elf.h" 69 #include "qemu/error-report.h" 70 #include "sysemu/kvm.h" 71 #include "sysemu/reset.h" 72 #include "kvm_ppc.h" 73 #include "hw/usb.h" 74 #include "exec/address-spaces.h" 75 #include "hw/sysbus.h" 76 #include "trace.h" 77 78 #define MAX_IDE_BUS 2 79 #define CFG_ADDR 0xf0000510 80 #define TBFREQ (100UL * 1000UL * 1000UL) 81 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 82 #define BUSFREQ (100UL * 1000UL * 1000UL) 83 84 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 85 86 #define PROM_BASE 0xfff00000 87 #define PROM_SIZE (1 * MiB) 88 89 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 90 Error **errp) 91 { 92 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 93 } 94 95 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 96 { 97 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 98 } 99 100 static void ppc_core99_reset(void *opaque) 101 { 102 PowerPCCPU *cpu = opaque; 103 104 cpu_reset(CPU(cpu)); 105 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 106 cpu->env.nip = PROM_BASE + 0x100; 107 } 108 109 /* PowerPC Mac99 hardware initialisation */ 110 static void ppc_core99_init(MachineState *machine) 111 { 112 ram_addr_t ram_size = machine->ram_size; 113 const char *bios_name = machine->firmware ?: PROM_FILENAME; 114 const char *kernel_filename = machine->kernel_filename; 115 const char *kernel_cmdline = machine->kernel_cmdline; 116 const char *initrd_filename = machine->initrd_filename; 117 const char *boot_device = machine->boot_order; 118 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 119 PowerPCCPU *cpu = NULL; 120 CPUPPCState *env = NULL; 121 char *filename; 122 IrqLines *openpic_irqs; 123 int linux_boot, i, j, k; 124 MemoryRegion *bios = g_new(MemoryRegion, 1); 125 hwaddr kernel_base, initrd_base, cmdline_base = 0; 126 long kernel_size, initrd_size; 127 UNINHostState *uninorth_pci; 128 PCIBus *pci_bus; 129 PCIDevice *macio; 130 ESCCState *escc; 131 bool has_pmu, has_adb; 132 MACIOIDEState *macio_ide; 133 BusState *adb_bus; 134 MacIONVRAMState *nvr; 135 int bios_size; 136 int ppc_boot_device; 137 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 138 void *fw_cfg; 139 int machine_arch; 140 SysBusDevice *s; 141 DeviceState *dev, *pic_dev; 142 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL; 143 hwaddr nvram_addr = 0xFFF04000; 144 uint64_t tbfreq; 145 unsigned int smp_cpus = machine->smp.cpus; 146 147 linux_boot = (kernel_filename != NULL); 148 149 /* init CPUs */ 150 for (i = 0; i < smp_cpus; i++) { 151 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 152 env = &cpu->env; 153 154 /* Set time-base frequency to 100 Mhz */ 155 cpu_ppc_tb_init(env, TBFREQ); 156 qemu_register_reset(ppc_core99_reset, cpu); 157 } 158 159 /* allocate RAM */ 160 if (machine->ram_size > 2 * GiB) { 161 error_report("RAM size more than 2 GiB is not supported"); 162 exit(1); 163 } 164 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 165 166 /* allocate and load firmware ROM */ 167 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE, 168 &error_fatal); 169 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios); 170 171 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 172 if (filename) { 173 /* Load OpenBIOS (ELF) */ 174 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, 175 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 176 177 if (bios_size <= 0) { 178 /* or load binary ROM image */ 179 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE); 180 } 181 g_free(filename); 182 } else { 183 bios_size = -1; 184 } 185 if (bios_size < 0 || bios_size > PROM_SIZE) { 186 error_report("could not load PowerPC bios '%s'", bios_name); 187 exit(1); 188 } 189 190 if (linux_boot) { 191 int bswap_needed; 192 193 #ifdef BSWAP_NEEDED 194 bswap_needed = 1; 195 #else 196 bswap_needed = 0; 197 #endif 198 kernel_base = KERNEL_LOAD_ADDR; 199 200 kernel_size = load_elf(kernel_filename, NULL, 201 translate_kernel_address, NULL, NULL, NULL, 202 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 203 if (kernel_size < 0) 204 kernel_size = load_aout(kernel_filename, kernel_base, 205 ram_size - kernel_base, bswap_needed, 206 TARGET_PAGE_SIZE); 207 if (kernel_size < 0) 208 kernel_size = load_image_targphys(kernel_filename, 209 kernel_base, 210 ram_size - kernel_base); 211 if (kernel_size < 0) { 212 error_report("could not load kernel '%s'", kernel_filename); 213 exit(1); 214 } 215 /* load initrd */ 216 if (initrd_filename) { 217 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 218 initrd_size = load_image_targphys(initrd_filename, initrd_base, 219 ram_size - initrd_base); 220 if (initrd_size < 0) { 221 error_report("could not load initial ram disk '%s'", 222 initrd_filename); 223 exit(1); 224 } 225 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 226 } else { 227 initrd_base = 0; 228 initrd_size = 0; 229 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 230 } 231 ppc_boot_device = 'm'; 232 } else { 233 kernel_base = 0; 234 kernel_size = 0; 235 initrd_base = 0; 236 initrd_size = 0; 237 ppc_boot_device = '\0'; 238 /* We consider that NewWorld PowerMac never have any floppy drive 239 * For now, OHW cannot boot from the network. 240 */ 241 for (i = 0; boot_device[i] != '\0'; i++) { 242 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 243 ppc_boot_device = boot_device[i]; 244 break; 245 } 246 } 247 if (ppc_boot_device == '\0') { 248 error_report("No valid boot device for Mac99 machine"); 249 exit(1); 250 } 251 } 252 253 /* UniN init */ 254 dev = qdev_new(TYPE_UNI_NORTH); 255 s = SYS_BUS_DEVICE(dev); 256 sysbus_realize_and_unref(s, &error_fatal); 257 memory_region_add_subregion(get_system_memory(), 0xf8000000, 258 sysbus_mmio_get_region(s, 0)); 259 260 openpic_irqs = g_new0(IrqLines, smp_cpus); 261 for (i = 0; i < smp_cpus; i++) { 262 /* Mac99 IRQ connection between OpenPIC outputs pins 263 * and PowerPC input pins 264 */ 265 switch (PPC_INPUT(env)) { 266 case PPC_FLAGS_INPUT_6xx: 267 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 268 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 269 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 270 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 271 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 272 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 273 /* Not connected ? */ 274 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 275 /* Check this */ 276 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 277 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 278 break; 279 #if defined(TARGET_PPC64) 280 case PPC_FLAGS_INPUT_970: 281 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] = 282 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 283 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] = 284 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 285 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] = 286 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 287 /* Not connected ? */ 288 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL; 289 /* Check this */ 290 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] = 291 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 292 break; 293 #endif /* defined(TARGET_PPC64) */ 294 default: 295 error_report("Bus model not supported on mac99 machine"); 296 exit(1); 297 } 298 } 299 300 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 301 /* 970 gets a U3 bus */ 302 /* Uninorth AGP bus */ 303 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE); 304 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 305 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 306 s = SYS_BUS_DEVICE(dev); 307 /* PCI hole */ 308 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 309 sysbus_mmio_get_region(s, 2)); 310 /* Register 8 MB of ISA IO space */ 311 memory_region_add_subregion(get_system_memory(), 0xf2000000, 312 sysbus_mmio_get_region(s, 3)); 313 sysbus_mmio_map(s, 0, 0xf0800000); 314 sysbus_mmio_map(s, 1, 0xf0c00000); 315 316 machine_arch = ARCH_MAC99_U3; 317 } else { 318 /* Use values found on a real PowerMac */ 319 /* Uninorth AGP bus */ 320 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 321 s = SYS_BUS_DEVICE(uninorth_agp_dev); 322 sysbus_realize_and_unref(s, &error_fatal); 323 sysbus_mmio_map(s, 0, 0xf0800000); 324 sysbus_mmio_map(s, 1, 0xf0c00000); 325 326 /* Uninorth internal bus */ 327 uninorth_internal_dev = qdev_new( 328 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 329 s = SYS_BUS_DEVICE(uninorth_internal_dev); 330 sysbus_realize_and_unref(s, &error_fatal); 331 sysbus_mmio_map(s, 0, 0xf4800000); 332 sysbus_mmio_map(s, 1, 0xf4c00000); 333 334 /* Uninorth main bus */ 335 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 336 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 337 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 338 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 339 s = SYS_BUS_DEVICE(dev); 340 /* PCI hole */ 341 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 342 sysbus_mmio_get_region(s, 2)); 343 /* Register 8 MB of ISA IO space */ 344 memory_region_add_subregion(get_system_memory(), 0xf2000000, 345 sysbus_mmio_get_region(s, 3)); 346 sysbus_mmio_map(s, 0, 0xf2800000); 347 sysbus_mmio_map(s, 1, 0xf2c00000); 348 349 machine_arch = ARCH_MAC99; 350 } 351 352 machine->usb |= defaults_enabled() && !machine->usb_disabled; 353 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 354 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 355 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 356 357 /* Timebase Frequency */ 358 if (kvm_enabled()) { 359 tbfreq = kvmppc_get_tbfreq(); 360 } else { 361 tbfreq = TBFREQ; 362 } 363 364 /* init basic PC hardware */ 365 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 366 367 /* MacIO */ 368 macio = pci_new(-1, TYPE_NEWWORLD_MACIO); 369 dev = DEVICE(macio); 370 qdev_prop_set_uint64(dev, "frequency", tbfreq); 371 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 372 qdev_prop_set_bit(dev, "has-adb", has_adb); 373 374 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc")); 375 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0)); 376 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1)); 377 378 pci_realize_and_unref(macio, pci_bus, &error_fatal); 379 380 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic")); 381 for (i = 0; i < 4; i++) { 382 qdev_connect_gpio_out(DEVICE(uninorth_pci), i, 383 qdev_get_gpio_in(pic_dev, 0x1b + i)); 384 } 385 386 /* TODO: additional PCI buses only wired up for 32-bit machines */ 387 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) { 388 /* Uninorth AGP bus */ 389 for (i = 0; i < 4; i++) { 390 qdev_connect_gpio_out(uninorth_agp_dev, i, 391 qdev_get_gpio_in(pic_dev, 0x1b + i)); 392 } 393 394 /* Uninorth internal bus */ 395 for (i = 0; i < 4; i++) { 396 qdev_connect_gpio_out(uninorth_internal_dev, i, 397 qdev_get_gpio_in(pic_dev, 0x1b + i)); 398 } 399 } 400 401 /* OpenPIC */ 402 s = SYS_BUS_DEVICE(pic_dev); 403 k = 0; 404 for (i = 0; i < smp_cpus; i++) { 405 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 406 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]); 407 } 408 } 409 g_free(openpic_irqs); 410 411 /* We only emulate 2 out of 3 IDE controllers for now */ 412 ide_drive_get(hd, ARRAY_SIZE(hd)); 413 414 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 415 "ide[0]")); 416 macio_ide_init_drives(macio_ide, hd); 417 418 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 419 "ide[1]")); 420 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 421 422 if (has_adb) { 423 if (has_pmu) { 424 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu")); 425 } else { 426 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 427 } 428 429 adb_bus = qdev_get_child_bus(dev, "adb.0"); 430 dev = qdev_new(TYPE_ADB_KEYBOARD); 431 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 432 433 dev = qdev_new(TYPE_ADB_MOUSE); 434 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 435 } 436 437 if (machine->usb) { 438 pci_create_simple(pci_bus, -1, "pci-ohci"); 439 440 /* U3 needs to use USB for input because Linux doesn't support via-cuda 441 on PPC64 */ 442 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 443 USBBus *usb_bus = usb_bus_find(-1); 444 445 usb_create_simple(usb_bus, "usb-kbd"); 446 usb_create_simple(usb_bus, "usb-mouse"); 447 } 448 } 449 450 pci_vga_init(pci_bus); 451 452 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 453 graphic_depth = 15; 454 } 455 456 for (i = 0; i < nb_nics; i++) { 457 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL); 458 } 459 460 /* The NewWorld NVRAM is not located in the MacIO device */ 461 if (kvm_enabled() && qemu_real_host_page_size > 4096) { 462 /* We can't combine read-write and read-only in a single page, so 463 move the NVRAM out of ROM again for KVM */ 464 nvram_addr = 0xFFE00000; 465 } 466 dev = qdev_new(TYPE_MACIO_NVRAM); 467 qdev_prop_set_uint32(dev, "size", 0x2000); 468 qdev_prop_set_uint32(dev, "it_shift", 1); 469 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 470 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 471 nvr = MACIO_NVRAM(dev); 472 pmac_format_nvram_partition(nvr, 0x2000); 473 /* No PCI init: the BIOS will do it */ 474 475 dev = qdev_new(TYPE_FW_CFG_MEM); 476 fw_cfg = FW_CFG(dev); 477 qdev_prop_set_uint32(dev, "data_width", 1); 478 qdev_prop_set_bit(dev, "dma_enabled", false); 479 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 480 OBJECT(fw_cfg)); 481 s = SYS_BUS_DEVICE(dev); 482 sysbus_realize_and_unref(s, &error_fatal); 483 sysbus_mmio_map(s, 0, CFG_ADDR); 484 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 485 486 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 487 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus); 488 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 489 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 490 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 491 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 492 if (kernel_cmdline) { 493 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 494 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 495 } else { 496 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 497 } 498 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 499 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 500 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 501 502 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 503 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 504 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 505 506 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 507 508 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 509 if (kvm_enabled()) { 510 uint8_t *hypercall; 511 512 hypercall = g_malloc(16); 513 kvmppc_get_hypercall(env, hypercall, 16); 514 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 515 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 516 } 517 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 518 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 519 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 520 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 521 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 522 523 /* MacOS NDRV VGA driver */ 524 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 525 if (filename) { 526 gchar *ndrv_file; 527 gsize ndrv_size; 528 529 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) { 530 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 531 } 532 g_free(filename); 533 } 534 535 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 536 } 537 538 /* 539 * Implementation of an interface to adjust firmware path 540 * for the bootindex property handling. 541 */ 542 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, 543 DeviceState *dev) 544 { 545 PCIDevice *pci; 546 MACIOIDEState *macio_ide; 547 548 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) { 549 pci = PCI_DEVICE(dev); 550 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn)); 551 } 552 553 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) { 554 macio_ide = MACIO_IDE(dev); 555 return g_strdup_printf("ata-3@%x", macio_ide->addr); 556 } 557 558 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) { 559 return g_strdup("disk"); 560 } 561 562 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) { 563 return g_strdup("cdrom"); 564 } 565 566 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) { 567 return g_strdup("disk"); 568 } 569 570 return NULL; 571 } 572 static int core99_kvm_type(MachineState *machine, const char *arg) 573 { 574 /* Always force PR KVM */ 575 return 2; 576 } 577 578 static void core99_machine_class_init(ObjectClass *oc, void *data) 579 { 580 MachineClass *mc = MACHINE_CLASS(oc); 581 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 582 583 mc->desc = "Mac99 based PowerMAC"; 584 mc->init = ppc_core99_init; 585 mc->block_default_type = IF_IDE; 586 mc->max_cpus = MAX_CPUS; 587 mc->default_boot_order = "cd"; 588 mc->default_display = "std"; 589 mc->kvm_type = core99_kvm_type; 590 #ifdef TARGET_PPC64 591 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 592 #else 593 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 594 #endif 595 mc->default_ram_id = "ppc_core99.ram"; 596 mc->ignore_boot_device_suffixes = true; 597 fwc->get_dev_path = core99_fw_dev_path; 598 } 599 600 static char *core99_get_via_config(Object *obj, Error **errp) 601 { 602 Core99MachineState *cms = CORE99_MACHINE(obj); 603 604 switch (cms->via_config) { 605 default: 606 case CORE99_VIA_CONFIG_CUDA: 607 return g_strdup("cuda"); 608 609 case CORE99_VIA_CONFIG_PMU: 610 return g_strdup("pmu"); 611 612 case CORE99_VIA_CONFIG_PMU_ADB: 613 return g_strdup("pmu-adb"); 614 } 615 } 616 617 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 618 { 619 Core99MachineState *cms = CORE99_MACHINE(obj); 620 621 if (!strcmp(value, "cuda")) { 622 cms->via_config = CORE99_VIA_CONFIG_CUDA; 623 } else if (!strcmp(value, "pmu")) { 624 cms->via_config = CORE99_VIA_CONFIG_PMU; 625 } else if (!strcmp(value, "pmu-adb")) { 626 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 627 } else { 628 error_setg(errp, "Invalid via value"); 629 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 630 } 631 } 632 633 static void core99_instance_init(Object *obj) 634 { 635 Core99MachineState *cms = CORE99_MACHINE(obj); 636 637 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 638 cms->via_config = CORE99_VIA_CONFIG_CUDA; 639 object_property_add_str(obj, "via", core99_get_via_config, 640 core99_set_via_config); 641 object_property_set_description(obj, "via", 642 "Set VIA configuration. " 643 "Valid values are cuda, pmu and pmu-adb"); 644 645 return; 646 } 647 648 static const TypeInfo core99_machine_info = { 649 .name = MACHINE_TYPE_NAME("mac99"), 650 .parent = TYPE_MACHINE, 651 .class_init = core99_machine_class_init, 652 .instance_init = core99_instance_init, 653 .instance_size = sizeof(Core99MachineState), 654 .interfaces = (InterfaceInfo[]) { 655 { TYPE_FW_PATH_PROVIDER }, 656 { } 657 }, 658 }; 659 660 static void mac_machine_register_types(void) 661 { 662 type_register_static(&core99_machine_info); 663 } 664 665 type_init(mac_machine_register_types) 666