1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "hw/hw.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/ppc/mac.h" 52 #include "hw/input/adb.h" 53 #include "hw/ppc/mac_dbdma.h" 54 #include "hw/timer/m48t59.h" 55 #include "hw/pci/pci.h" 56 #include "net/net.h" 57 #include "sysemu/sysemu.h" 58 #include "hw/boards.h" 59 #include "hw/nvram/fw_cfg.h" 60 #include "hw/char/escc.h" 61 #include "hw/ppc/openpic.h" 62 #include "hw/ide.h" 63 #include "hw/loader.h" 64 #include "elf.h" 65 #include "qemu/error-report.h" 66 #include "sysemu/kvm.h" 67 #include "kvm_ppc.h" 68 #include "hw/usb.h" 69 #include "sysemu/block-backend.h" 70 #include "exec/address-spaces.h" 71 #include "hw/sysbus.h" 72 73 #define MAX_IDE_BUS 2 74 #define CFG_ADDR 0xf0000510 75 #define TBFREQ (100UL * 1000UL * 1000UL) 76 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 77 #define BUSFREQ (100UL * 1000UL * 1000UL) 78 79 /* debug UniNorth */ 80 //#define DEBUG_UNIN 81 82 #ifdef DEBUG_UNIN 83 #define UNIN_DPRINTF(fmt, ...) \ 84 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 85 #else 86 #define UNIN_DPRINTF(fmt, ...) 87 #endif 88 89 /* UniN device */ 90 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 91 unsigned size) 92 { 93 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 94 if (addr == 0x0) { 95 *(int*)opaque = value; 96 } 97 } 98 99 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 100 { 101 uint32_t value; 102 103 value = 0; 104 switch (addr) { 105 case 0: 106 value = *(int*)opaque; 107 } 108 109 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 110 111 return value; 112 } 113 114 static const MemoryRegionOps unin_ops = { 115 .read = unin_read, 116 .write = unin_write, 117 .endianness = DEVICE_NATIVE_ENDIAN, 118 }; 119 120 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 121 Error **errp) 122 { 123 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 124 } 125 126 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 127 { 128 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 129 } 130 131 static hwaddr round_page(hwaddr addr) 132 { 133 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 134 } 135 136 static void ppc_core99_reset(void *opaque) 137 { 138 PowerPCCPU *cpu = opaque; 139 140 cpu_reset(CPU(cpu)); 141 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 142 cpu->env.nip = PROM_ADDR + 0x100; 143 } 144 145 /* PowerPC Mac99 hardware initialisation */ 146 static void ppc_core99_init(MachineState *machine) 147 { 148 ram_addr_t ram_size = machine->ram_size; 149 const char *kernel_filename = machine->kernel_filename; 150 const char *kernel_cmdline = machine->kernel_cmdline; 151 const char *initrd_filename = machine->initrd_filename; 152 const char *boot_device = machine->boot_order; 153 PowerPCCPU *cpu = NULL; 154 CPUPPCState *env = NULL; 155 char *filename; 156 qemu_irq *pic, **openpic_irqs; 157 MemoryRegion *isa = g_new(MemoryRegion, 1); 158 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 159 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 160 int linux_boot, i, j, k; 161 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 162 hwaddr kernel_base, initrd_base, cmdline_base = 0; 163 long kernel_size, initrd_size; 164 PCIBus *pci_bus; 165 PCIDevice *macio; 166 MACIOIDEState *macio_ide; 167 BusState *adb_bus; 168 MacIONVRAMState *nvr; 169 int bios_size; 170 MemoryRegion *pic_mem, *escc_mem; 171 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 172 int ppc_boot_device; 173 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 174 void *fw_cfg; 175 int machine_arch; 176 SysBusDevice *s; 177 DeviceState *dev; 178 int *token = g_new(int, 1); 179 hwaddr nvram_addr = 0xFFF04000; 180 uint64_t tbfreq; 181 182 linux_boot = (kernel_filename != NULL); 183 184 /* init CPUs */ 185 if (machine->cpu_model == NULL) { 186 #ifdef TARGET_PPC64 187 machine->cpu_model = "970fx"; 188 #else 189 machine->cpu_model = "G4"; 190 #endif 191 } 192 for (i = 0; i < smp_cpus; i++) { 193 cpu = cpu_ppc_init(machine->cpu_model); 194 if (cpu == NULL) { 195 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 196 exit(1); 197 } 198 env = &cpu->env; 199 200 /* Set time-base frequency to 100 Mhz */ 201 cpu_ppc_tb_init(env, TBFREQ); 202 qemu_register_reset(ppc_core99_reset, cpu); 203 } 204 205 /* allocate RAM */ 206 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 207 memory_region_add_subregion(get_system_memory(), 0, ram); 208 209 /* allocate and load BIOS */ 210 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 211 &error_fatal); 212 vmstate_register_ram_global(bios); 213 214 if (bios_name == NULL) 215 bios_name = PROM_FILENAME; 216 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 217 memory_region_set_readonly(bios, true); 218 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 219 220 /* Load OpenBIOS (ELF) */ 221 if (filename) { 222 bios_size = load_elf(filename, NULL, NULL, NULL, 223 NULL, NULL, 1, PPC_ELF_MACHINE, 0); 224 225 g_free(filename); 226 } else { 227 bios_size = -1; 228 } 229 if (bios_size < 0 || bios_size > BIOS_SIZE) { 230 error_report("could not load PowerPC bios '%s'", bios_name); 231 exit(1); 232 } 233 234 if (linux_boot) { 235 uint64_t lowaddr = 0; 236 int bswap_needed; 237 238 #ifdef BSWAP_NEEDED 239 bswap_needed = 1; 240 #else 241 bswap_needed = 0; 242 #endif 243 kernel_base = KERNEL_LOAD_ADDR; 244 245 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 246 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0); 247 if (kernel_size < 0) 248 kernel_size = load_aout(kernel_filename, kernel_base, 249 ram_size - kernel_base, bswap_needed, 250 TARGET_PAGE_SIZE); 251 if (kernel_size < 0) 252 kernel_size = load_image_targphys(kernel_filename, 253 kernel_base, 254 ram_size - kernel_base); 255 if (kernel_size < 0) { 256 error_report("could not load kernel '%s'", kernel_filename); 257 exit(1); 258 } 259 /* load initrd */ 260 if (initrd_filename) { 261 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 262 initrd_size = load_image_targphys(initrd_filename, initrd_base, 263 ram_size - initrd_base); 264 if (initrd_size < 0) { 265 error_report("could not load initial ram disk '%s'", 266 initrd_filename); 267 exit(1); 268 } 269 cmdline_base = round_page(initrd_base + initrd_size); 270 } else { 271 initrd_base = 0; 272 initrd_size = 0; 273 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 274 } 275 ppc_boot_device = 'm'; 276 } else { 277 kernel_base = 0; 278 kernel_size = 0; 279 initrd_base = 0; 280 initrd_size = 0; 281 ppc_boot_device = '\0'; 282 /* We consider that NewWorld PowerMac never have any floppy drive 283 * For now, OHW cannot boot from the network. 284 */ 285 for (i = 0; boot_device[i] != '\0'; i++) { 286 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 287 ppc_boot_device = boot_device[i]; 288 break; 289 } 290 } 291 if (ppc_boot_device == '\0') { 292 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 293 exit(1); 294 } 295 } 296 297 /* Register 8 MB of ISA IO space */ 298 memory_region_init_alias(isa, NULL, "isa_mmio", 299 get_system_io(), 0, 0x00800000); 300 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 301 302 /* UniN init: XXX should be a real device */ 303 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 304 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 305 306 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 307 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 308 309 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 310 openpic_irqs[0] = 311 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 312 for (i = 0; i < smp_cpus; i++) { 313 /* Mac99 IRQ connection between OpenPIC outputs pins 314 * and PowerPC input pins 315 */ 316 switch (PPC_INPUT(env)) { 317 case PPC_FLAGS_INPUT_6xx: 318 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 319 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 320 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 321 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 322 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 323 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 324 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 325 /* Not connected ? */ 326 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 327 /* Check this */ 328 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 329 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 330 break; 331 #if defined(TARGET_PPC64) 332 case PPC_FLAGS_INPUT_970: 333 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 334 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 335 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 336 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 337 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 338 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 339 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 340 /* Not connected ? */ 341 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 342 /* Check this */ 343 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 344 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 345 break; 346 #endif /* defined(TARGET_PPC64) */ 347 default: 348 error_report("Bus model not supported on mac99 machine"); 349 exit(1); 350 } 351 } 352 353 pic = g_new0(qemu_irq, 64); 354 355 dev = qdev_create(NULL, TYPE_OPENPIC); 356 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 357 qdev_init_nofail(dev); 358 s = SYS_BUS_DEVICE(dev); 359 pic_mem = s->mmio[0].memory; 360 k = 0; 361 for (i = 0; i < smp_cpus; i++) { 362 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 363 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 364 } 365 } 366 367 for (i = 0; i < 64; i++) { 368 pic[i] = qdev_get_gpio_in(dev, i); 369 } 370 371 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 372 /* 970 gets a U3 bus */ 373 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 374 machine_arch = ARCH_MAC99_U3; 375 } else { 376 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 377 machine_arch = ARCH_MAC99; 378 } 379 380 machine->usb |= defaults_enabled() && !machine->usb_disabled; 381 382 /* Timebase Frequency */ 383 if (kvm_enabled()) { 384 tbfreq = kvmppc_get_tbfreq(); 385 } else { 386 tbfreq = TBFREQ; 387 } 388 389 /* init basic PC hardware */ 390 escc_mem = escc_init(0, pic[0x25], pic[0x24], 391 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 392 memory_region_init_alias(escc_bar, NULL, "escc-bar", 393 escc_mem, 0, memory_region_size(escc_mem)); 394 395 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 396 dev = DEVICE(macio); 397 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 398 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 399 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 400 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 401 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 402 qdev_prop_set_uint64(dev, "frequency", tbfreq); 403 macio_init(macio, pic_mem, escc_bar); 404 405 /* We only emulate 2 out of 3 IDE controllers for now */ 406 ide_drive_get(hd, ARRAY_SIZE(hd)); 407 408 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 409 "ide[0]")); 410 macio_ide_init_drives(macio_ide, hd); 411 412 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 413 "ide[1]")); 414 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 415 416 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 417 adb_bus = qdev_get_child_bus(dev, "adb.0"); 418 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 419 qdev_init_nofail(dev); 420 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 421 qdev_init_nofail(dev); 422 423 if (machine->usb) { 424 pci_create_simple(pci_bus, -1, "pci-ohci"); 425 426 /* U3 needs to use USB for input because Linux doesn't support via-cuda 427 on PPC64 */ 428 if (machine_arch == ARCH_MAC99_U3) { 429 USBBus *usb_bus = usb_bus_find(-1); 430 431 usb_create_simple(usb_bus, "usb-kbd"); 432 usb_create_simple(usb_bus, "usb-mouse"); 433 } 434 } 435 436 pci_vga_init(pci_bus); 437 438 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 439 graphic_depth = 15; 440 } 441 442 for (i = 0; i < nb_nics; i++) { 443 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 444 } 445 446 /* The NewWorld NVRAM is not located in the MacIO device */ 447 #ifdef CONFIG_KVM 448 if (kvm_enabled() && getpagesize() > 4096) { 449 /* We can't combine read-write and read-only in a single page, so 450 move the NVRAM out of ROM again for KVM */ 451 nvram_addr = 0xFFE00000; 452 } 453 #endif 454 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 455 qdev_prop_set_uint32(dev, "size", 0x2000); 456 qdev_prop_set_uint32(dev, "it_shift", 1); 457 qdev_init_nofail(dev); 458 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 459 nvr = MACIO_NVRAM(dev); 460 pmac_format_nvram_partition(nvr, 0x2000); 461 /* No PCI init: the BIOS will do it */ 462 463 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 464 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 465 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 466 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 469 if (kernel_cmdline) { 470 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 471 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 472 } else { 473 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 474 } 475 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 476 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 477 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 478 479 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 480 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 481 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 482 483 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 484 if (kvm_enabled()) { 485 #ifdef CONFIG_KVM 486 uint8_t *hypercall; 487 488 hypercall = g_malloc(16); 489 kvmppc_get_hypercall(env, hypercall, 16); 490 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 491 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 492 #endif 493 } 494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 495 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 496 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 497 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 498 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 499 500 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 501 } 502 503 static int core99_kvm_type(const char *arg) 504 { 505 /* Always force PR KVM */ 506 return 2; 507 } 508 509 static void core99_machine_class_init(ObjectClass *oc, void *data) 510 { 511 MachineClass *mc = MACHINE_CLASS(oc); 512 513 mc->desc = "Mac99 based PowerMAC"; 514 mc->init = ppc_core99_init; 515 mc->max_cpus = MAX_CPUS; 516 mc->default_boot_order = "cd"; 517 mc->kvm_type = core99_kvm_type; 518 } 519 520 static const TypeInfo core99_machine_info = { 521 .name = MACHINE_TYPE_NAME("mac99"), 522 .parent = TYPE_MACHINE, 523 .class_init = core99_machine_class_init, 524 }; 525 526 static void mac_machine_register_types(void) 527 { 528 type_register_static(&core99_machine_info); 529 } 530 531 type_init(mac_machine_register_types) 532