1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/ppc/openpic.h" 64 #include "hw/ide.h" 65 #include "hw/loader.h" 66 #include "elf.h" 67 #include "qemu/error-report.h" 68 #include "sysemu/kvm.h" 69 #include "kvm_ppc.h" 70 #include "hw/usb.h" 71 #include "sysemu/block-backend.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 #include "qemu/cutils.h" 75 #include "trace.h" 76 77 #define MAX_IDE_BUS 2 78 #define CFG_ADDR 0xf0000510 79 #define TBFREQ (100UL * 1000UL * 1000UL) 80 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 81 #define BUSFREQ (100UL * 1000UL * 1000UL) 82 83 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 84 85 /* UniN device */ 86 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 87 unsigned size) 88 { 89 trace_mac99_uninorth_write(addr, value); 90 if (addr == 0x0) { 91 *(int*)opaque = value; 92 } 93 } 94 95 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 96 { 97 uint32_t value; 98 99 value = 0; 100 switch (addr) { 101 case 0: 102 value = *(int*)opaque; 103 } 104 105 trace_mac99_uninorth_read(addr, value); 106 107 return value; 108 } 109 110 static const MemoryRegionOps unin_ops = { 111 .read = unin_read, 112 .write = unin_write, 113 .endianness = DEVICE_NATIVE_ENDIAN, 114 }; 115 116 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 117 Error **errp) 118 { 119 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 120 } 121 122 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 123 { 124 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 125 } 126 127 static hwaddr round_page(hwaddr addr) 128 { 129 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 130 } 131 132 static void ppc_core99_reset(void *opaque) 133 { 134 PowerPCCPU *cpu = opaque; 135 136 cpu_reset(CPU(cpu)); 137 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 138 cpu->env.nip = PROM_ADDR + 0x100; 139 } 140 141 /* PowerPC Mac99 hardware initialisation */ 142 static void ppc_core99_init(MachineState *machine) 143 { 144 ram_addr_t ram_size = machine->ram_size; 145 const char *kernel_filename = machine->kernel_filename; 146 const char *kernel_cmdline = machine->kernel_cmdline; 147 const char *initrd_filename = machine->initrd_filename; 148 const char *boot_device = machine->boot_order; 149 PowerPCCPU *cpu = NULL; 150 CPUPPCState *env = NULL; 151 char *filename; 152 qemu_irq *pic, **openpic_irqs; 153 MemoryRegion *isa = g_new(MemoryRegion, 1); 154 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 155 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 156 int linux_boot, i, j, k; 157 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 158 hwaddr kernel_base, initrd_base, cmdline_base = 0; 159 long kernel_size, initrd_size; 160 PCIBus *pci_bus; 161 PCIDevice *macio; 162 MACIOIDEState *macio_ide; 163 BusState *adb_bus; 164 MacIONVRAMState *nvr; 165 int bios_size, ndrv_size; 166 uint8_t *ndrv_file; 167 MemoryRegion *pic_mem, *escc_mem; 168 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 169 int ppc_boot_device; 170 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 171 void *fw_cfg; 172 int machine_arch; 173 SysBusDevice *s; 174 DeviceState *dev; 175 int *token = g_new(int, 1); 176 hwaddr nvram_addr = 0xFFF04000; 177 uint64_t tbfreq; 178 179 linux_boot = (kernel_filename != NULL); 180 181 /* init CPUs */ 182 if (machine->cpu_model == NULL) { 183 #ifdef TARGET_PPC64 184 machine->cpu_model = "970fx"; 185 #else 186 machine->cpu_model = "G4"; 187 #endif 188 } 189 for (i = 0; i < smp_cpus; i++) { 190 cpu = POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, 191 machine->cpu_model)); 192 env = &cpu->env; 193 194 /* Set time-base frequency to 100 Mhz */ 195 cpu_ppc_tb_init(env, TBFREQ); 196 qemu_register_reset(ppc_core99_reset, cpu); 197 } 198 199 /* allocate RAM */ 200 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 201 memory_region_add_subregion(get_system_memory(), 0, ram); 202 203 /* allocate and load BIOS */ 204 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 205 &error_fatal); 206 207 if (bios_name == NULL) 208 bios_name = PROM_FILENAME; 209 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 210 memory_region_set_readonly(bios, true); 211 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 212 213 /* Load OpenBIOS (ELF) */ 214 if (filename) { 215 bios_size = load_elf(filename, NULL, NULL, NULL, 216 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 217 218 g_free(filename); 219 } else { 220 bios_size = -1; 221 } 222 if (bios_size < 0 || bios_size > BIOS_SIZE) { 223 error_report("could not load PowerPC bios '%s'", bios_name); 224 exit(1); 225 } 226 227 if (linux_boot) { 228 uint64_t lowaddr = 0; 229 int bswap_needed; 230 231 #ifdef BSWAP_NEEDED 232 bswap_needed = 1; 233 #else 234 bswap_needed = 0; 235 #endif 236 kernel_base = KERNEL_LOAD_ADDR; 237 238 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 239 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 240 0, 0); 241 if (kernel_size < 0) 242 kernel_size = load_aout(kernel_filename, kernel_base, 243 ram_size - kernel_base, bswap_needed, 244 TARGET_PAGE_SIZE); 245 if (kernel_size < 0) 246 kernel_size = load_image_targphys(kernel_filename, 247 kernel_base, 248 ram_size - kernel_base); 249 if (kernel_size < 0) { 250 error_report("could not load kernel '%s'", kernel_filename); 251 exit(1); 252 } 253 /* load initrd */ 254 if (initrd_filename) { 255 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 256 initrd_size = load_image_targphys(initrd_filename, initrd_base, 257 ram_size - initrd_base); 258 if (initrd_size < 0) { 259 error_report("could not load initial ram disk '%s'", 260 initrd_filename); 261 exit(1); 262 } 263 cmdline_base = round_page(initrd_base + initrd_size); 264 } else { 265 initrd_base = 0; 266 initrd_size = 0; 267 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 268 } 269 ppc_boot_device = 'm'; 270 } else { 271 kernel_base = 0; 272 kernel_size = 0; 273 initrd_base = 0; 274 initrd_size = 0; 275 ppc_boot_device = '\0'; 276 /* We consider that NewWorld PowerMac never have any floppy drive 277 * For now, OHW cannot boot from the network. 278 */ 279 for (i = 0; boot_device[i] != '\0'; i++) { 280 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 281 ppc_boot_device = boot_device[i]; 282 break; 283 } 284 } 285 if (ppc_boot_device == '\0') { 286 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 287 exit(1); 288 } 289 } 290 291 /* Register 8 MB of ISA IO space */ 292 memory_region_init_alias(isa, NULL, "isa_mmio", 293 get_system_io(), 0, 0x00800000); 294 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 295 296 /* UniN init: XXX should be a real device */ 297 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 298 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 299 300 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 301 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 302 303 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 304 openpic_irqs[0] = 305 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 306 for (i = 0; i < smp_cpus; i++) { 307 /* Mac99 IRQ connection between OpenPIC outputs pins 308 * and PowerPC input pins 309 */ 310 switch (PPC_INPUT(env)) { 311 case PPC_FLAGS_INPUT_6xx: 312 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 313 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 314 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 315 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 316 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 317 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 318 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 319 /* Not connected ? */ 320 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 321 /* Check this */ 322 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 323 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 324 break; 325 #if defined(TARGET_PPC64) 326 case PPC_FLAGS_INPUT_970: 327 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 328 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 329 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 330 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 331 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 332 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 333 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 334 /* Not connected ? */ 335 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 336 /* Check this */ 337 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 338 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 339 break; 340 #endif /* defined(TARGET_PPC64) */ 341 default: 342 error_report("Bus model not supported on mac99 machine"); 343 exit(1); 344 } 345 } 346 347 pic = g_new0(qemu_irq, 64); 348 349 dev = qdev_create(NULL, TYPE_OPENPIC); 350 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 351 qdev_init_nofail(dev); 352 s = SYS_BUS_DEVICE(dev); 353 pic_mem = s->mmio[0].memory; 354 k = 0; 355 for (i = 0; i < smp_cpus; i++) { 356 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 357 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 358 } 359 } 360 361 for (i = 0; i < 64; i++) { 362 pic[i] = qdev_get_gpio_in(dev, i); 363 } 364 365 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 366 /* 970 gets a U3 bus */ 367 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 368 machine_arch = ARCH_MAC99_U3; 369 } else { 370 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 371 machine_arch = ARCH_MAC99; 372 } 373 object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort); 374 375 machine->usb |= defaults_enabled() && !machine->usb_disabled; 376 377 /* Timebase Frequency */ 378 if (kvm_enabled()) { 379 tbfreq = kvmppc_get_tbfreq(); 380 } else { 381 tbfreq = TBFREQ; 382 } 383 384 /* init basic PC hardware */ 385 escc_mem = escc_init(0, pic[0x25], pic[0x24], 386 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 387 memory_region_init_alias(escc_bar, NULL, "escc-bar", 388 escc_mem, 0, memory_region_size(escc_mem)); 389 390 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 391 dev = DEVICE(macio); 392 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 393 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 394 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 395 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 396 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 397 qdev_prop_set_uint64(dev, "frequency", tbfreq); 398 macio_init(macio, pic_mem, escc_bar); 399 400 /* We only emulate 2 out of 3 IDE controllers for now */ 401 ide_drive_get(hd, ARRAY_SIZE(hd)); 402 403 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 404 "ide[0]")); 405 macio_ide_init_drives(macio_ide, hd); 406 407 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 408 "ide[1]")); 409 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 410 411 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 412 adb_bus = qdev_get_child_bus(dev, "adb.0"); 413 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 414 qdev_init_nofail(dev); 415 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 416 qdev_init_nofail(dev); 417 418 if (machine->usb) { 419 pci_create_simple(pci_bus, -1, "pci-ohci"); 420 421 /* U3 needs to use USB for input because Linux doesn't support via-cuda 422 on PPC64 */ 423 if (machine_arch == ARCH_MAC99_U3) { 424 USBBus *usb_bus = usb_bus_find(-1); 425 426 usb_create_simple(usb_bus, "usb-kbd"); 427 usb_create_simple(usb_bus, "usb-mouse"); 428 } 429 } 430 431 pci_vga_init(pci_bus); 432 433 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 434 graphic_depth = 15; 435 } 436 437 for (i = 0; i < nb_nics; i++) { 438 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 439 } 440 441 /* The NewWorld NVRAM is not located in the MacIO device */ 442 #ifdef CONFIG_KVM 443 if (kvm_enabled() && getpagesize() > 4096) { 444 /* We can't combine read-write and read-only in a single page, so 445 move the NVRAM out of ROM again for KVM */ 446 nvram_addr = 0xFFE00000; 447 } 448 #endif 449 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 450 qdev_prop_set_uint32(dev, "size", 0x2000); 451 qdev_prop_set_uint32(dev, "it_shift", 1); 452 qdev_init_nofail(dev); 453 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 454 nvr = MACIO_NVRAM(dev); 455 pmac_format_nvram_partition(nvr, 0x2000); 456 /* No PCI init: the BIOS will do it */ 457 458 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 459 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 460 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 461 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 462 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 463 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 464 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 465 if (kernel_cmdline) { 466 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 467 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 468 } else { 469 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 470 } 471 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 472 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 473 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 474 475 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 476 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 477 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 478 479 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 480 if (kvm_enabled()) { 481 #ifdef CONFIG_KVM 482 uint8_t *hypercall; 483 484 hypercall = g_malloc(16); 485 kvmppc_get_hypercall(env, hypercall, 16); 486 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 487 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 488 #endif 489 } 490 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 491 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 492 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 493 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 494 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 495 496 /* MacOS NDRV VGA driver */ 497 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 498 if (filename) { 499 ndrv_size = get_image_size(filename); 500 if (ndrv_size != -1) { 501 ndrv_file = g_malloc(ndrv_size); 502 ndrv_size = load_image(filename, ndrv_file); 503 504 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 505 } 506 g_free(filename); 507 } 508 509 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 510 } 511 512 static int core99_kvm_type(const char *arg) 513 { 514 /* Always force PR KVM */ 515 return 2; 516 } 517 518 static void core99_machine_class_init(ObjectClass *oc, void *data) 519 { 520 MachineClass *mc = MACHINE_CLASS(oc); 521 522 mc->desc = "Mac99 based PowerMAC"; 523 mc->init = ppc_core99_init; 524 mc->block_default_type = IF_IDE; 525 mc->max_cpus = MAX_CPUS; 526 mc->default_boot_order = "cd"; 527 mc->kvm_type = core99_kvm_type; 528 } 529 530 static const TypeInfo core99_machine_info = { 531 .name = MACHINE_TYPE_NAME("mac99"), 532 .parent = TYPE_MACHINE, 533 .class_init = core99_machine_class_init, 534 }; 535 536 static void mac_machine_register_types(void) 537 { 538 type_register_static(&core99_machine_info); 539 } 540 541 type_init(mac_machine_register_types) 542