1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "qemu/osdep.h" 50 #include "qapi/error.h" 51 #include "hw/hw.h" 52 #include "hw/ppc/ppc.h" 53 #include "hw/ppc/mac.h" 54 #include "hw/input/adb.h" 55 #include "hw/ppc/mac_dbdma.h" 56 #include "hw/timer/m48t59.h" 57 #include "hw/pci/pci.h" 58 #include "net/net.h" 59 #include "sysemu/sysemu.h" 60 #include "hw/boards.h" 61 #include "hw/nvram/fw_cfg.h" 62 #include "hw/char/escc.h" 63 #include "hw/misc/macio/macio.h" 64 #include "hw/ppc/openpic.h" 65 #include "hw/ide.h" 66 #include "hw/loader.h" 67 #include "elf.h" 68 #include "qemu/error-report.h" 69 #include "sysemu/kvm.h" 70 #include "kvm_ppc.h" 71 #include "hw/usb.h" 72 #include "exec/address-spaces.h" 73 #include "hw/sysbus.h" 74 #include "trace.h" 75 76 #define MAX_IDE_BUS 2 77 #define CFG_ADDR 0xf0000510 78 #define TBFREQ (100UL * 1000UL * 1000UL) 79 #define CLOCKFREQ (900UL * 1000UL * 1000UL) 80 #define BUSFREQ (100UL * 1000UL * 1000UL) 81 82 #define NDRV_VGA_FILENAME "qemu_vga.ndrv" 83 84 85 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 86 Error **errp) 87 { 88 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 89 } 90 91 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 92 { 93 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 94 } 95 96 static void ppc_core99_reset(void *opaque) 97 { 98 PowerPCCPU *cpu = opaque; 99 100 cpu_reset(CPU(cpu)); 101 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 102 cpu->env.nip = PROM_ADDR + 0x100; 103 } 104 105 /* PowerPC Mac99 hardware initialisation */ 106 static void ppc_core99_init(MachineState *machine) 107 { 108 ram_addr_t ram_size = machine->ram_size; 109 const char *kernel_filename = machine->kernel_filename; 110 const char *kernel_cmdline = machine->kernel_cmdline; 111 const char *initrd_filename = machine->initrd_filename; 112 const char *boot_device = machine->boot_order; 113 Core99MachineState *core99_machine = CORE99_MACHINE(machine); 114 PowerPCCPU *cpu = NULL; 115 CPUPPCState *env = NULL; 116 char *filename; 117 qemu_irq **openpic_irqs; 118 int linux_boot, i, j, k; 119 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 120 hwaddr kernel_base, initrd_base, cmdline_base = 0; 121 long kernel_size, initrd_size; 122 UNINHostState *uninorth_pci; 123 PCIBus *pci_bus; 124 NewWorldMacIOState *macio; 125 bool has_pmu, has_adb; 126 MACIOIDEState *macio_ide; 127 BusState *adb_bus; 128 MacIONVRAMState *nvr; 129 int bios_size, ndrv_size; 130 uint8_t *ndrv_file; 131 int ppc_boot_device; 132 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 133 void *fw_cfg; 134 int machine_arch; 135 SysBusDevice *s; 136 DeviceState *dev, *pic_dev; 137 hwaddr nvram_addr = 0xFFF04000; 138 uint64_t tbfreq; 139 140 linux_boot = (kernel_filename != NULL); 141 142 /* init CPUs */ 143 for (i = 0; i < smp_cpus; i++) { 144 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 145 env = &cpu->env; 146 147 /* Set time-base frequency to 100 Mhz */ 148 cpu_ppc_tb_init(env, TBFREQ); 149 qemu_register_reset(ppc_core99_reset, cpu); 150 } 151 152 /* allocate RAM */ 153 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 154 memory_region_add_subregion(get_system_memory(), 0, ram); 155 156 /* allocate and load BIOS */ 157 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, 158 &error_fatal); 159 160 if (bios_name == NULL) 161 bios_name = PROM_FILENAME; 162 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 163 memory_region_set_readonly(bios, true); 164 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 165 166 /* Load OpenBIOS (ELF) */ 167 if (filename) { 168 bios_size = load_elf(filename, NULL, NULL, NULL, 169 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0); 170 171 g_free(filename); 172 } else { 173 bios_size = -1; 174 } 175 if (bios_size < 0 || bios_size > BIOS_SIZE) { 176 error_report("could not load PowerPC bios '%s'", bios_name); 177 exit(1); 178 } 179 180 if (linux_boot) { 181 uint64_t lowaddr = 0; 182 int bswap_needed; 183 184 #ifdef BSWAP_NEEDED 185 bswap_needed = 1; 186 #else 187 bswap_needed = 0; 188 #endif 189 kernel_base = KERNEL_LOAD_ADDR; 190 191 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 192 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 193 0, 0); 194 if (kernel_size < 0) 195 kernel_size = load_aout(kernel_filename, kernel_base, 196 ram_size - kernel_base, bswap_needed, 197 TARGET_PAGE_SIZE); 198 if (kernel_size < 0) 199 kernel_size = load_image_targphys(kernel_filename, 200 kernel_base, 201 ram_size - kernel_base); 202 if (kernel_size < 0) { 203 error_report("could not load kernel '%s'", kernel_filename); 204 exit(1); 205 } 206 /* load initrd */ 207 if (initrd_filename) { 208 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 209 initrd_size = load_image_targphys(initrd_filename, initrd_base, 210 ram_size - initrd_base); 211 if (initrd_size < 0) { 212 error_report("could not load initial ram disk '%s'", 213 initrd_filename); 214 exit(1); 215 } 216 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size); 217 } else { 218 initrd_base = 0; 219 initrd_size = 0; 220 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP); 221 } 222 ppc_boot_device = 'm'; 223 } else { 224 kernel_base = 0; 225 kernel_size = 0; 226 initrd_base = 0; 227 initrd_size = 0; 228 ppc_boot_device = '\0'; 229 /* We consider that NewWorld PowerMac never have any floppy drive 230 * For now, OHW cannot boot from the network. 231 */ 232 for (i = 0; boot_device[i] != '\0'; i++) { 233 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 234 ppc_boot_device = boot_device[i]; 235 break; 236 } 237 } 238 if (ppc_boot_device == '\0') { 239 error_report("No valid boot device for Mac99 machine"); 240 exit(1); 241 } 242 } 243 244 /* UniN init */ 245 dev = qdev_create(NULL, TYPE_UNI_NORTH); 246 qdev_init_nofail(dev); 247 s = SYS_BUS_DEVICE(dev); 248 memory_region_add_subregion(get_system_memory(), 0xf8000000, 249 sysbus_mmio_get_region(s, 0)); 250 251 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 252 openpic_irqs[0] = 253 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 254 for (i = 0; i < smp_cpus; i++) { 255 /* Mac99 IRQ connection between OpenPIC outputs pins 256 * and PowerPC input pins 257 */ 258 switch (PPC_INPUT(env)) { 259 case PPC_FLAGS_INPUT_6xx: 260 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 261 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 262 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 263 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 264 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 265 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 266 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 267 /* Not connected ? */ 268 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 269 /* Check this */ 270 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 271 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 272 break; 273 #if defined(TARGET_PPC64) 274 case PPC_FLAGS_INPUT_970: 275 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 276 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 277 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 278 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 279 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 280 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 281 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 282 /* Not connected ? */ 283 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 284 /* Check this */ 285 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 286 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 287 break; 288 #endif /* defined(TARGET_PPC64) */ 289 default: 290 error_report("Bus model not supported on mac99 machine"); 291 exit(1); 292 } 293 } 294 295 pic_dev = qdev_create(NULL, TYPE_OPENPIC); 296 qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO); 297 qdev_init_nofail(pic_dev); 298 s = SYS_BUS_DEVICE(pic_dev); 299 k = 0; 300 for (i = 0; i < smp_cpus; i++) { 301 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 302 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 303 } 304 } 305 306 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 307 /* 970 gets a U3 bus */ 308 /* Uninorth AGP bus */ 309 dev = qdev_create(NULL, TYPE_U3_AGP_HOST_BRIDGE); 310 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 311 &error_abort); 312 qdev_init_nofail(dev); 313 uninorth_pci = U3_AGP_HOST_BRIDGE(dev); 314 s = SYS_BUS_DEVICE(dev); 315 /* PCI hole */ 316 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 317 sysbus_mmio_get_region(s, 2)); 318 /* Register 8 MB of ISA IO space */ 319 memory_region_add_subregion(get_system_memory(), 0xf2000000, 320 sysbus_mmio_get_region(s, 3)); 321 sysbus_mmio_map(s, 0, 0xf0800000); 322 sysbus_mmio_map(s, 1, 0xf0c00000); 323 324 machine_arch = ARCH_MAC99_U3; 325 } else { 326 /* Use values found on a real PowerMac */ 327 /* Uninorth AGP bus */ 328 dev = qdev_create(NULL, TYPE_UNI_NORTH_AGP_HOST_BRIDGE); 329 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 330 &error_abort); 331 qdev_init_nofail(dev); 332 s = SYS_BUS_DEVICE(dev); 333 sysbus_mmio_map(s, 0, 0xf0800000); 334 sysbus_mmio_map(s, 1, 0xf0c00000); 335 336 /* Uninorth internal bus */ 337 dev = qdev_create(NULL, TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE); 338 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 339 &error_abort); 340 qdev_init_nofail(dev); 341 s = SYS_BUS_DEVICE(dev); 342 sysbus_mmio_map(s, 0, 0xf4800000); 343 sysbus_mmio_map(s, 1, 0xf4c00000); 344 345 /* Uninorth main bus */ 346 dev = qdev_create(NULL, TYPE_UNI_NORTH_PCI_HOST_BRIDGE); 347 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000); 348 object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic", 349 &error_abort); 350 qdev_init_nofail(dev); 351 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev); 352 s = SYS_BUS_DEVICE(dev); 353 /* PCI hole */ 354 memory_region_add_subregion(get_system_memory(), 0x80000000ULL, 355 sysbus_mmio_get_region(s, 2)); 356 /* Register 8 MB of ISA IO space */ 357 memory_region_add_subregion(get_system_memory(), 0xf2000000, 358 sysbus_mmio_get_region(s, 3)); 359 sysbus_mmio_map(s, 0, 0xf2800000); 360 sysbus_mmio_map(s, 1, 0xf2c00000); 361 362 machine_arch = ARCH_MAC99; 363 } 364 365 machine->usb |= defaults_enabled() && !machine->usb_disabled; 366 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA); 367 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA || 368 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB); 369 370 /* Timebase Frequency */ 371 if (kvm_enabled()) { 372 tbfreq = kvmppc_get_tbfreq(); 373 } else { 374 tbfreq = TBFREQ; 375 } 376 377 /* init basic PC hardware */ 378 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus; 379 380 /* MacIO */ 381 macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO)); 382 dev = DEVICE(macio); 383 qdev_prop_set_uint64(dev, "frequency", tbfreq); 384 qdev_prop_set_bit(dev, "has-pmu", has_pmu); 385 qdev_prop_set_bit(dev, "has-adb", has_adb); 386 object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic", 387 &error_abort); 388 qdev_init_nofail(dev); 389 390 /* We only emulate 2 out of 3 IDE controllers for now */ 391 ide_drive_get(hd, ARRAY_SIZE(hd)); 392 393 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 394 "ide[0]")); 395 macio_ide_init_drives(macio_ide, hd); 396 397 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 398 "ide[1]")); 399 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 400 401 if (has_adb) { 402 if (has_pmu) { 403 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu")); 404 } else { 405 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 406 } 407 408 adb_bus = qdev_get_child_bus(dev, "adb.0"); 409 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 410 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true); 411 qdev_init_nofail(dev); 412 413 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 414 qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true); 415 qdev_init_nofail(dev); 416 } 417 418 if (machine->usb) { 419 pci_create_simple(pci_bus, -1, "pci-ohci"); 420 421 /* U3 needs to use USB for input because Linux doesn't support via-cuda 422 on PPC64 */ 423 if (!has_adb || machine_arch == ARCH_MAC99_U3) { 424 USBBus *usb_bus = usb_bus_find(-1); 425 426 usb_create_simple(usb_bus, "usb-kbd"); 427 usb_create_simple(usb_bus, "usb-mouse"); 428 } 429 } 430 431 pci_vga_init(pci_bus); 432 433 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 434 graphic_depth = 15; 435 } 436 437 for (i = 0; i < nb_nics; i++) { 438 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 439 } 440 441 /* The NewWorld NVRAM is not located in the MacIO device */ 442 #ifdef CONFIG_KVM 443 if (kvm_enabled() && getpagesize() > 4096) { 444 /* We can't combine read-write and read-only in a single page, so 445 move the NVRAM out of ROM again for KVM */ 446 nvram_addr = 0xFFE00000; 447 } 448 #endif 449 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 450 qdev_prop_set_uint32(dev, "size", 0x2000); 451 qdev_prop_set_uint32(dev, "it_shift", 1); 452 qdev_init_nofail(dev); 453 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr); 454 nvr = MACIO_NVRAM(dev); 455 pmac_format_nvram_partition(nvr, 0x2000); 456 /* No PCI init: the BIOS will do it */ 457 458 dev = qdev_create(NULL, TYPE_FW_CFG_MEM); 459 fw_cfg = FW_CFG(dev); 460 qdev_prop_set_uint32(dev, "data_width", 1); 461 qdev_prop_set_bit(dev, "dma_enabled", false); 462 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 463 OBJECT(fw_cfg), NULL); 464 qdev_init_nofail(dev); 465 s = SYS_BUS_DEVICE(dev); 466 sysbus_mmio_map(s, 0, CFG_ADDR); 467 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 468 469 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 470 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 471 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 472 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 473 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 474 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 475 if (kernel_cmdline) { 476 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 477 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 478 } else { 479 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 480 } 481 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 482 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 483 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 484 485 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 486 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 487 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 488 489 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config); 490 491 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 492 if (kvm_enabled()) { 493 #ifdef CONFIG_KVM 494 uint8_t *hypercall; 495 496 hypercall = g_malloc(16); 497 kvmppc_get_hypercall(env, hypercall, 16); 498 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 499 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 500 #endif 501 } 502 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq); 503 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 504 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 505 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 506 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr); 507 508 /* MacOS NDRV VGA driver */ 509 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME); 510 if (filename) { 511 ndrv_size = get_image_size(filename); 512 if (ndrv_size != -1) { 513 ndrv_file = g_malloc(ndrv_size); 514 ndrv_size = load_image(filename, ndrv_file); 515 516 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size); 517 } 518 g_free(filename); 519 } 520 521 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 522 } 523 524 static int core99_kvm_type(const char *arg) 525 { 526 /* Always force PR KVM */ 527 return 2; 528 } 529 530 static void core99_machine_class_init(ObjectClass *oc, void *data) 531 { 532 MachineClass *mc = MACHINE_CLASS(oc); 533 534 mc->desc = "Mac99 based PowerMAC"; 535 mc->init = ppc_core99_init; 536 mc->block_default_type = IF_IDE; 537 mc->max_cpus = MAX_CPUS; 538 mc->default_boot_order = "cd"; 539 mc->default_display = "std"; 540 mc->kvm_type = core99_kvm_type; 541 #ifdef TARGET_PPC64 542 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1"); 543 #else 544 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); 545 #endif 546 } 547 548 static char *core99_get_via_config(Object *obj, Error **errp) 549 { 550 Core99MachineState *cms = CORE99_MACHINE(obj); 551 552 switch (cms->via_config) { 553 default: 554 case CORE99_VIA_CONFIG_CUDA: 555 return g_strdup("cuda"); 556 557 case CORE99_VIA_CONFIG_PMU: 558 return g_strdup("pmu"); 559 560 case CORE99_VIA_CONFIG_PMU_ADB: 561 return g_strdup("pmu-adb"); 562 } 563 } 564 565 static void core99_set_via_config(Object *obj, const char *value, Error **errp) 566 { 567 Core99MachineState *cms = CORE99_MACHINE(obj); 568 569 if (!strcmp(value, "cuda")) { 570 cms->via_config = CORE99_VIA_CONFIG_CUDA; 571 } else if (!strcmp(value, "pmu")) { 572 cms->via_config = CORE99_VIA_CONFIG_PMU; 573 } else if (!strcmp(value, "pmu-adb")) { 574 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB; 575 } else { 576 error_setg(errp, "Invalid via value"); 577 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n"); 578 } 579 } 580 581 static void core99_instance_init(Object *obj) 582 { 583 Core99MachineState *cms = CORE99_MACHINE(obj); 584 585 /* Default via_config is CORE99_VIA_CONFIG_CUDA */ 586 cms->via_config = CORE99_VIA_CONFIG_CUDA; 587 object_property_add_str(obj, "via", core99_get_via_config, 588 core99_set_via_config, NULL); 589 object_property_set_description(obj, "via", 590 "Set VIA configuration. " 591 "Valid values are cuda, pmu and pmu-adb", 592 NULL); 593 594 return; 595 } 596 597 static const TypeInfo core99_machine_info = { 598 .name = MACHINE_TYPE_NAME("mac99"), 599 .parent = TYPE_MACHINE, 600 .class_init = core99_machine_class_init, 601 .instance_init = core99_instance_init, 602 .instance_size = sizeof(Core99MachineState) 603 }; 604 605 static void mac_machine_register_types(void) 606 { 607 type_register_static(&core99_machine_info); 608 } 609 610 type_init(mac_machine_register_types) 611