1 /* 2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * 25 * PCI bus layout on a real G5 (U3 based): 26 * 27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b] 28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150] 29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a] 30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12) 32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045] 33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046] 34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047] 35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048] 36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049] 37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20) 38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040] 40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43) 42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04) 43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043] 44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042] 45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c] 46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240] 47 * 48 */ 49 #include "hw/hw.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/ppc/mac.h" 52 #include "hw/input/adb.h" 53 #include "hw/ppc/mac_dbdma.h" 54 #include "hw/timer/m48t59.h" 55 #include "hw/pci/pci.h" 56 #include "net/net.h" 57 #include "sysemu/sysemu.h" 58 #include "hw/boards.h" 59 #include "hw/nvram/fw_cfg.h" 60 #include "hw/char/escc.h" 61 #include "hw/ppc/openpic.h" 62 #include "hw/ide.h" 63 #include "hw/loader.h" 64 #include "elf.h" 65 #include "sysemu/kvm.h" 66 #include "kvm_ppc.h" 67 #include "hw/usb.h" 68 #include "sysemu/blockdev.h" 69 #include "exec/address-spaces.h" 70 #include "hw/sysbus.h" 71 72 #define MAX_IDE_BUS 2 73 #define CFG_ADDR 0xf0000510 74 #define TBFREQ (100UL * 1000UL * 1000UL) 75 #define CLOCKFREQ (266UL * 1000UL * 1000UL) 76 #define BUSFREQ (100UL * 1000UL * 1000UL) 77 78 /* debug UniNorth */ 79 //#define DEBUG_UNIN 80 81 #ifdef DEBUG_UNIN 82 #define UNIN_DPRINTF(fmt, ...) \ 83 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0) 84 #else 85 #define UNIN_DPRINTF(fmt, ...) 86 #endif 87 88 /* UniN device */ 89 static void unin_write(void *opaque, hwaddr addr, uint64_t value, 90 unsigned size) 91 { 92 UNIN_DPRINTF("write addr " TARGET_FMT_plx " val %"PRIx64"\n", addr, value); 93 if (addr == 0x0) { 94 *(int*)opaque = value; 95 } 96 } 97 98 static uint64_t unin_read(void *opaque, hwaddr addr, unsigned size) 99 { 100 uint32_t value; 101 102 value = 0; 103 switch (addr) { 104 case 0: 105 value = *(int*)opaque; 106 } 107 108 UNIN_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n", addr, value); 109 110 return value; 111 } 112 113 static const MemoryRegionOps unin_ops = { 114 .read = unin_read, 115 .write = unin_write, 116 .endianness = DEVICE_NATIVE_ENDIAN, 117 }; 118 119 static int fw_cfg_boot_set(void *opaque, const char *boot_device) 120 { 121 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 122 return 0; 123 } 124 125 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 126 { 127 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 128 } 129 130 static hwaddr round_page(hwaddr addr) 131 { 132 return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; 133 } 134 135 static void ppc_core99_reset(void *opaque) 136 { 137 PowerPCCPU *cpu = opaque; 138 139 cpu_reset(CPU(cpu)); 140 /* 970 CPUs want to get their initial IP as part of their boot protocol */ 141 cpu->env.nip = PROM_ADDR + 0x100; 142 } 143 144 /* PowerPC Mac99 hardware initialisation */ 145 static void ppc_core99_init(MachineState *machine) 146 { 147 ram_addr_t ram_size = machine->ram_size; 148 const char *cpu_model = machine->cpu_model; 149 const char *kernel_filename = machine->kernel_filename; 150 const char *kernel_cmdline = machine->kernel_cmdline; 151 const char *initrd_filename = machine->initrd_filename; 152 const char *boot_device = machine->boot_order; 153 PowerPCCPU *cpu = NULL; 154 CPUPPCState *env = NULL; 155 char *filename; 156 qemu_irq *pic, **openpic_irqs; 157 MemoryRegion *isa = g_new(MemoryRegion, 1); 158 MemoryRegion *unin_memory = g_new(MemoryRegion, 1); 159 MemoryRegion *unin2_memory = g_new(MemoryRegion, 1); 160 int linux_boot, i, j, k; 161 MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); 162 hwaddr kernel_base, initrd_base, cmdline_base = 0; 163 long kernel_size, initrd_size; 164 PCIBus *pci_bus; 165 PCIDevice *macio; 166 MACIOIDEState *macio_ide; 167 BusState *adb_bus; 168 MacIONVRAMState *nvr; 169 int bios_size; 170 MemoryRegion *pic_mem, *escc_mem; 171 MemoryRegion *escc_bar = g_new(MemoryRegion, 1); 172 int ppc_boot_device; 173 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 174 void *fw_cfg; 175 int machine_arch; 176 SysBusDevice *s; 177 DeviceState *dev; 178 int *token = g_new(int, 1); 179 180 linux_boot = (kernel_filename != NULL); 181 182 /* init CPUs */ 183 if (cpu_model == NULL) 184 #ifdef TARGET_PPC64 185 cpu_model = "970fx"; 186 #else 187 cpu_model = "G4"; 188 #endif 189 for (i = 0; i < smp_cpus; i++) { 190 cpu = cpu_ppc_init(cpu_model); 191 if (cpu == NULL) { 192 fprintf(stderr, "Unable to find PowerPC CPU definition\n"); 193 exit(1); 194 } 195 env = &cpu->env; 196 197 /* Set time-base frequency to 100 Mhz */ 198 cpu_ppc_tb_init(env, TBFREQ); 199 qemu_register_reset(ppc_core99_reset, cpu); 200 } 201 202 /* allocate RAM */ 203 memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); 204 memory_region_add_subregion(get_system_memory(), 0, ram); 205 206 /* allocate and load BIOS */ 207 memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE); 208 vmstate_register_ram_global(bios); 209 210 if (bios_name == NULL) 211 bios_name = PROM_FILENAME; 212 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 213 memory_region_set_readonly(bios, true); 214 memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios); 215 216 /* Load OpenBIOS (ELF) */ 217 if (filename) { 218 bios_size = load_elf(filename, NULL, NULL, NULL, 219 NULL, NULL, 1, ELF_MACHINE, 0); 220 221 g_free(filename); 222 } else { 223 bios_size = -1; 224 } 225 if (bios_size < 0 || bios_size > BIOS_SIZE) { 226 hw_error("qemu: could not load PowerPC bios '%s'\n", bios_name); 227 exit(1); 228 } 229 230 if (linux_boot) { 231 uint64_t lowaddr = 0; 232 int bswap_needed; 233 234 #ifdef BSWAP_NEEDED 235 bswap_needed = 1; 236 #else 237 bswap_needed = 0; 238 #endif 239 kernel_base = KERNEL_LOAD_ADDR; 240 241 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 242 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); 243 if (kernel_size < 0) 244 kernel_size = load_aout(kernel_filename, kernel_base, 245 ram_size - kernel_base, bswap_needed, 246 TARGET_PAGE_SIZE); 247 if (kernel_size < 0) 248 kernel_size = load_image_targphys(kernel_filename, 249 kernel_base, 250 ram_size - kernel_base); 251 if (kernel_size < 0) { 252 hw_error("qemu: could not load kernel '%s'\n", kernel_filename); 253 exit(1); 254 } 255 /* load initrd */ 256 if (initrd_filename) { 257 initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 258 initrd_size = load_image_targphys(initrd_filename, initrd_base, 259 ram_size - initrd_base); 260 if (initrd_size < 0) { 261 hw_error("qemu: could not load initial ram disk '%s'\n", 262 initrd_filename); 263 exit(1); 264 } 265 cmdline_base = round_page(initrd_base + initrd_size); 266 } else { 267 initrd_base = 0; 268 initrd_size = 0; 269 cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP); 270 } 271 ppc_boot_device = 'm'; 272 } else { 273 kernel_base = 0; 274 kernel_size = 0; 275 initrd_base = 0; 276 initrd_size = 0; 277 ppc_boot_device = '\0'; 278 /* We consider that NewWorld PowerMac never have any floppy drive 279 * For now, OHW cannot boot from the network. 280 */ 281 for (i = 0; boot_device[i] != '\0'; i++) { 282 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') { 283 ppc_boot_device = boot_device[i]; 284 break; 285 } 286 } 287 if (ppc_boot_device == '\0') { 288 fprintf(stderr, "No valid boot device for Mac99 machine\n"); 289 exit(1); 290 } 291 } 292 293 /* Register 8 MB of ISA IO space */ 294 memory_region_init_alias(isa, NULL, "isa_mmio", 295 get_system_io(), 0, 0x00800000); 296 memory_region_add_subregion(get_system_memory(), 0xf2000000, isa); 297 298 /* UniN init: XXX should be a real device */ 299 memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000); 300 memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory); 301 302 memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000); 303 memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory); 304 305 openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 306 openpic_irqs[0] = 307 g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 308 for (i = 0; i < smp_cpus; i++) { 309 /* Mac99 IRQ connection between OpenPIC outputs pins 310 * and PowerPC input pins 311 */ 312 switch (PPC_INPUT(env)) { 313 case PPC_FLAGS_INPUT_6xx: 314 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 315 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 316 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 317 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 318 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]; 319 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 320 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP]; 321 /* Not connected ? */ 322 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 323 /* Check this */ 324 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 325 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET]; 326 break; 327 #if defined(TARGET_PPC64) 328 case PPC_FLAGS_INPUT_970: 329 openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB); 330 openpic_irqs[i][OPENPIC_OUTPUT_INT] = 331 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 332 openpic_irqs[i][OPENPIC_OUTPUT_CINT] = 333 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT]; 334 openpic_irqs[i][OPENPIC_OUTPUT_MCK] = 335 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP]; 336 /* Not connected ? */ 337 openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL; 338 /* Check this */ 339 openpic_irqs[i][OPENPIC_OUTPUT_RESET] = 340 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET]; 341 break; 342 #endif /* defined(TARGET_PPC64) */ 343 default: 344 hw_error("Bus model not supported on mac99 machine\n"); 345 exit(1); 346 } 347 } 348 349 pic = g_new(qemu_irq, 64); 350 351 dev = qdev_create(NULL, TYPE_OPENPIC); 352 qdev_prop_set_uint32(dev, "model", OPENPIC_MODEL_RAVEN); 353 qdev_init_nofail(dev); 354 s = SYS_BUS_DEVICE(dev); 355 pic_mem = s->mmio[0].memory; 356 k = 0; 357 for (i = 0; i < smp_cpus; i++) { 358 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 359 sysbus_connect_irq(s, k++, openpic_irqs[i][j]); 360 } 361 } 362 363 for (i = 0; i < 64; i++) { 364 pic[i] = qdev_get_gpio_in(dev, i); 365 } 366 367 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { 368 /* 970 gets a U3 bus */ 369 pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io()); 370 machine_arch = ARCH_MAC99_U3; 371 } else { 372 pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io()); 373 machine_arch = ARCH_MAC99; 374 } 375 /* init basic PC hardware */ 376 escc_mem = escc_init(0, pic[0x25], pic[0x24], 377 serial_hds[0], serial_hds[1], ESCC_CLOCK, 4); 378 memory_region_init_alias(escc_bar, NULL, "escc-bar", 379 escc_mem, 0, memory_region_size(escc_mem)); 380 381 macio = pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO); 382 dev = DEVICE(macio); 383 qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */ 384 qdev_connect_gpio_out(dev, 1, pic[0x0d]); /* IDE */ 385 qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE DMA */ 386 qdev_connect_gpio_out(dev, 3, pic[0x0e]); /* IDE */ 387 qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE DMA */ 388 macio_init(macio, pic_mem, escc_bar); 389 390 /* We only emulate 2 out of 3 IDE controllers for now */ 391 ide_drive_get(hd, MAX_IDE_BUS); 392 393 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 394 "ide[0]")); 395 macio_ide_init_drives(macio_ide, hd); 396 397 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio), 398 "ide[1]")); 399 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]); 400 401 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda")); 402 adb_bus = qdev_get_child_bus(dev, "adb.0"); 403 dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD); 404 qdev_init_nofail(dev); 405 dev = qdev_create(adb_bus, TYPE_ADB_MOUSE); 406 qdev_init_nofail(dev); 407 408 if (usb_enabled(machine_arch == ARCH_MAC99_U3)) { 409 pci_create_simple(pci_bus, -1, "pci-ohci"); 410 /* U3 needs to use USB for input because Linux doesn't support via-cuda 411 on PPC64 */ 412 if (machine_arch == ARCH_MAC99_U3) { 413 usbdevice_create("keyboard"); 414 usbdevice_create("mouse"); 415 } 416 } 417 418 pci_vga_init(pci_bus); 419 420 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) { 421 graphic_depth = 15; 422 } 423 424 for (i = 0; i < nb_nics; i++) { 425 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 426 } 427 428 /* The NewWorld NVRAM is not located in the MacIO device */ 429 dev = qdev_create(NULL, TYPE_MACIO_NVRAM); 430 qdev_prop_set_uint32(dev, "size", 0x2000); 431 qdev_prop_set_uint32(dev, "it_shift", 1); 432 qdev_init_nofail(dev); 433 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xFFF04000); 434 nvr = MACIO_NVRAM(dev); 435 pmac_format_nvram_partition(nvr, 0x2000); 436 /* No PCI init: the BIOS will do it */ 437 438 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); 439 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 440 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); 441 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 442 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); 443 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 444 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 445 if (kernel_cmdline) { 446 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base); 447 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline); 448 } else { 449 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 450 } 451 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 452 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 453 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device); 454 455 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 456 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 457 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 458 459 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 460 if (kvm_enabled()) { 461 #ifdef CONFIG_KVM 462 uint8_t *hypercall; 463 464 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 465 hypercall = g_malloc(16); 466 kvmppc_get_hypercall(env, hypercall, 16); 467 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 468 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 469 #endif 470 } else { 471 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, TBFREQ); 472 } 473 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */ 474 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ); 475 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ); 476 477 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 478 } 479 480 static QEMUMachine core99_machine = { 481 .name = "mac99", 482 .desc = "Mac99 based PowerMAC", 483 .init = ppc_core99_init, 484 .max_cpus = MAX_CPUS, 485 .default_boot_order = "cd", 486 }; 487 488 static void core99_machine_init(void) 489 { 490 qemu_register_machine(&core99_machine); 491 } 492 493 machine_init(core99_machine_init); 494