1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "hw/sysbus.h" 36 #include "exec/address-spaces.h" 37 #include "qemu/host-utils.h" 38 #include "hw/pci-host/ppce500.h" 39 40 #define EPAPR_MAGIC (0x45504150) 41 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 42 #define DTC_LOAD_PAD 0x1800000 43 #define DTC_PAD_MASK 0xFFFFF 44 #define DTB_MAX_SIZE (8 * 1024 * 1024) 45 #define INITRD_LOAD_PAD 0x2000000 46 #define INITRD_PAD_MASK 0xFFFFFF 47 48 #define RAM_SIZES_ALIGN (64UL << 20) 49 50 /* TODO: parameterize */ 51 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 52 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 53 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 54 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 55 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 56 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 57 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 58 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ 59 MPC8544_PCI_REGS_OFFSET) 60 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 61 #define MPC8544_PCI_IO 0xE1000000ULL 62 #define MPC8544_UTIL_OFFSET 0xe0000ULL 63 #define MPC8544_SPIN_BASE 0xEF000000ULL 64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 65 #define MPC8XXX_GPIO_IRQ 43 66 67 struct boot_info 68 { 69 uint32_t dt_base; 70 uint32_t dt_size; 71 uint32_t entry; 72 }; 73 74 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 75 int nr_slots, int *len) 76 { 77 int i = 0; 78 int slot; 79 int pci_irq; 80 int host_irq; 81 int last_slot = first_slot + nr_slots; 82 uint32_t *pci_map; 83 84 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 85 pci_map = g_malloc(*len); 86 87 for (slot = first_slot; slot < last_slot; slot++) { 88 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 89 pci_map[i++] = cpu_to_be32(slot << 11); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(0x0); 92 pci_map[i++] = cpu_to_be32(pci_irq + 1); 93 pci_map[i++] = cpu_to_be32(mpic); 94 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 95 pci_map[i++] = cpu_to_be32(host_irq + 1); 96 pci_map[i++] = cpu_to_be32(0x1); 97 } 98 } 99 100 assert((i * sizeof(uint32_t)) == *len); 101 102 return pci_map; 103 } 104 105 static void dt_serial_create(void *fdt, unsigned long long offset, 106 const char *soc, const char *mpic, 107 const char *alias, int idx, bool defcon) 108 { 109 char ser[128]; 110 111 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 112 qemu_fdt_add_subnode(fdt, ser); 113 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 114 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 115 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 116 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 117 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 118 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 119 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 120 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 121 122 if (defcon) { 123 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 124 } 125 } 126 127 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 128 { 129 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 130 int irq0 = MPC8XXX_GPIO_IRQ; 131 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 132 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 133 int gpio_ph; 134 135 qemu_fdt_add_subnode(fdt, node); 136 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 137 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 138 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 139 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 140 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 141 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 142 gpio_ph = qemu_fdt_alloc_phandle(fdt); 143 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 144 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 145 146 /* Power Off Pin */ 147 qemu_fdt_add_subnode(fdt, poweroff); 148 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 149 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 150 151 g_free(node); 152 g_free(poweroff); 153 } 154 155 static int ppce500_load_device_tree(MachineState *machine, 156 PPCE500Params *params, 157 hwaddr addr, 158 hwaddr initrd_base, 159 hwaddr initrd_size, 160 hwaddr kernel_base, 161 hwaddr kernel_size, 162 bool dry_run) 163 { 164 CPUPPCState *env = first_cpu->env_ptr; 165 int ret = -1; 166 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 167 int fdt_size; 168 void *fdt; 169 uint8_t hypercall[16]; 170 uint32_t clock_freq = 400000000; 171 uint32_t tb_freq = 400000000; 172 int i; 173 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 174 char soc[128]; 175 char mpic[128]; 176 uint32_t mpic_ph; 177 uint32_t msi_ph; 178 char gutil[128]; 179 char pci[128]; 180 char msi[128]; 181 uint32_t *pci_map = NULL; 182 int len; 183 uint32_t pci_ranges[14] = 184 { 185 0x2000000, 0x0, 0xc0000000, 186 0x0, 0xc0000000, 187 0x0, 0x20000000, 188 189 0x1000000, 0x0, 0x0, 190 0x0, 0xe1000000, 191 0x0, 0x10000, 192 }; 193 QemuOpts *machine_opts = qemu_get_machine_opts(); 194 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 195 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 196 197 if (dtb_file) { 198 char *filename; 199 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 200 if (!filename) { 201 goto out; 202 } 203 204 fdt = load_device_tree(filename, &fdt_size); 205 if (!fdt) { 206 goto out; 207 } 208 goto done; 209 } 210 211 fdt = create_device_tree(&fdt_size); 212 if (fdt == NULL) { 213 goto out; 214 } 215 216 /* Manipulate device tree in memory. */ 217 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 218 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 219 220 qemu_fdt_add_subnode(fdt, "/memory"); 221 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 222 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 223 sizeof(mem_reg_property)); 224 225 qemu_fdt_add_subnode(fdt, "/chosen"); 226 if (initrd_size) { 227 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 228 initrd_base); 229 if (ret < 0) { 230 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 231 } 232 233 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 234 (initrd_base + initrd_size)); 235 if (ret < 0) { 236 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 237 } 238 239 } 240 241 if (kernel_base != -1ULL) { 242 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 243 kernel_base >> 32, kernel_base, 244 kernel_size >> 32, kernel_size); 245 } 246 247 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 248 machine->kernel_cmdline); 249 if (ret < 0) 250 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 251 252 if (kvm_enabled()) { 253 /* Read out host's frequencies */ 254 clock_freq = kvmppc_get_clockfreq(); 255 tb_freq = kvmppc_get_tbfreq(); 256 257 /* indicate KVM hypercall interface */ 258 qemu_fdt_add_subnode(fdt, "/hypervisor"); 259 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 260 "linux,kvm"); 261 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 262 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 263 hypercall, sizeof(hypercall)); 264 /* if KVM supports the idle hcall, set property indicating this */ 265 if (kvmppc_get_hasidle(env)) { 266 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 267 } 268 } 269 270 /* Create CPU nodes */ 271 qemu_fdt_add_subnode(fdt, "/cpus"); 272 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 273 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 274 275 /* We need to generate the cpu nodes in reverse order, so Linux can pick 276 the first node as boot node and be happy */ 277 for (i = smp_cpus - 1; i >= 0; i--) { 278 CPUState *cpu; 279 PowerPCCPU *pcpu; 280 char cpu_name[128]; 281 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 282 283 cpu = qemu_get_cpu(i); 284 if (cpu == NULL) { 285 continue; 286 } 287 env = cpu->env_ptr; 288 pcpu = POWERPC_CPU(cpu); 289 290 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 291 ppc_get_vcpu_dt_id(pcpu)); 292 qemu_fdt_add_subnode(fdt, cpu_name); 293 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 294 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 295 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 296 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 297 ppc_get_vcpu_dt_id(pcpu)); 298 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 299 env->dcache_line_size); 300 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 301 env->icache_line_size); 302 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 303 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 304 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 305 if (cpu->cpu_index) { 306 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 307 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 308 "spin-table"); 309 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 310 cpu_release_addr); 311 } else { 312 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 313 } 314 } 315 316 qemu_fdt_add_subnode(fdt, "/aliases"); 317 /* XXX These should go into their respective devices' code */ 318 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 319 qemu_fdt_add_subnode(fdt, soc); 320 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 321 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 322 sizeof(compatible_sb)); 323 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 324 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 325 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 326 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 327 MPC8544_CCSRBAR_SIZE); 328 /* XXX should contain a reasonable value */ 329 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 330 331 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 332 qemu_fdt_add_subnode(fdt, mpic); 333 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 334 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 335 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 336 0x40000); 337 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 338 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 339 mpic_ph = qemu_fdt_alloc_phandle(fdt); 340 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 341 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 342 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 343 344 /* 345 * We have to generate ser1 first, because Linux takes the first 346 * device it finds in the dt as serial output device. And we generate 347 * devices in reverse order to the dt. 348 */ 349 if (serial_hds[1]) { 350 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 351 soc, mpic, "serial1", 1, false); 352 } 353 354 if (serial_hds[0]) { 355 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 356 soc, mpic, "serial0", 0, true); 357 } 358 359 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 360 MPC8544_UTIL_OFFSET); 361 qemu_fdt_add_subnode(fdt, gutil); 362 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 363 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 364 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 365 366 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 367 qemu_fdt_add_subnode(fdt, msi); 368 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 369 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 370 msi_ph = qemu_fdt_alloc_phandle(fdt); 371 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 372 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 373 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 374 0xe0, 0x0, 375 0xe1, 0x0, 376 0xe2, 0x0, 377 0xe3, 0x0, 378 0xe4, 0x0, 379 0xe5, 0x0, 380 0xe6, 0x0, 381 0xe7, 0x0); 382 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 383 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 384 385 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 386 qemu_fdt_add_subnode(fdt, pci); 387 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 388 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 389 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 390 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 391 0x0, 0x7); 392 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 393 params->pci_first_slot, params->pci_nr_slots, 394 &len); 395 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 396 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 397 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 398 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 399 for (i = 0; i < 14; i++) { 400 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 401 } 402 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 403 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 404 qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 405 MPC8544_PCI_REGS_BASE, 0, 0x1000); 406 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 407 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 408 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 409 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 410 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 411 412 if (params->has_mpc8xxx_gpio) { 413 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 414 } 415 416 params->fixup_devtree(params, fdt); 417 418 if (toplevel_compat) { 419 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 420 strlen(toplevel_compat) + 1); 421 } 422 423 done: 424 if (!dry_run) { 425 qemu_fdt_dumpdtb(fdt, fdt_size); 426 cpu_physical_memory_write(addr, fdt, fdt_size); 427 } 428 ret = fdt_size; 429 430 out: 431 g_free(pci_map); 432 433 return ret; 434 } 435 436 typedef struct DeviceTreeParams { 437 MachineState *machine; 438 PPCE500Params params; 439 hwaddr addr; 440 hwaddr initrd_base; 441 hwaddr initrd_size; 442 hwaddr kernel_base; 443 hwaddr kernel_size; 444 } DeviceTreeParams; 445 446 static void ppce500_reset_device_tree(void *opaque) 447 { 448 DeviceTreeParams *p = opaque; 449 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base, 450 p->initrd_size, p->kernel_base, p->kernel_size, 451 false); 452 } 453 454 static int ppce500_prep_device_tree(MachineState *machine, 455 PPCE500Params *params, 456 hwaddr addr, 457 hwaddr initrd_base, 458 hwaddr initrd_size, 459 hwaddr kernel_base, 460 hwaddr kernel_size) 461 { 462 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 463 p->machine = machine; 464 p->params = *params; 465 p->addr = addr; 466 p->initrd_base = initrd_base; 467 p->initrd_size = initrd_size; 468 p->kernel_base = kernel_base; 469 p->kernel_size = kernel_size; 470 471 qemu_register_reset(ppce500_reset_device_tree, p); 472 473 /* Issue the device tree loader once, so that we get the size of the blob */ 474 return ppce500_load_device_tree(machine, params, addr, initrd_base, 475 initrd_size, kernel_base, kernel_size, 476 true); 477 } 478 479 /* Create -kernel TLB entries for BookE. */ 480 static inline hwaddr booke206_page_size_to_tlb(uint64_t size) 481 { 482 return 63 - clz64(size >> 10); 483 } 484 485 static int booke206_initial_map_tsize(CPUPPCState *env) 486 { 487 struct boot_info *bi = env->load_info; 488 hwaddr dt_end; 489 int ps; 490 491 /* Our initial TLB entry needs to cover everything from 0 to 492 the device tree top */ 493 dt_end = bi->dt_base + bi->dt_size; 494 ps = booke206_page_size_to_tlb(dt_end) + 1; 495 if (ps & 1) { 496 /* e500v2 can only do even TLB size bits */ 497 ps++; 498 } 499 return ps; 500 } 501 502 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 503 { 504 int tsize; 505 506 tsize = booke206_initial_map_tsize(env); 507 return (1ULL << 10 << tsize); 508 } 509 510 static void mmubooke_create_initial_mapping(CPUPPCState *env) 511 { 512 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 513 hwaddr size; 514 int ps; 515 516 ps = booke206_initial_map_tsize(env); 517 size = (ps << MAS1_TSIZE_SHIFT); 518 tlb->mas1 = MAS1_VALID | size; 519 tlb->mas2 = 0; 520 tlb->mas7_3 = 0; 521 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 522 523 env->tlb_dirty = true; 524 } 525 526 static void ppce500_cpu_reset_sec(void *opaque) 527 { 528 PowerPCCPU *cpu = opaque; 529 CPUState *cs = CPU(cpu); 530 531 cpu_reset(cs); 532 533 /* Secondary CPU starts in halted state for now. Needs to change when 534 implementing non-kernel boot. */ 535 cs->halted = 1; 536 cs->exception_index = EXCP_HLT; 537 } 538 539 static void ppce500_cpu_reset(void *opaque) 540 { 541 PowerPCCPU *cpu = opaque; 542 CPUState *cs = CPU(cpu); 543 CPUPPCState *env = &cpu->env; 544 struct boot_info *bi = env->load_info; 545 546 cpu_reset(cs); 547 548 /* Set initial guest state. */ 549 cs->halted = 0; 550 env->gpr[1] = (16<<20) - 8; 551 env->gpr[3] = bi->dt_base; 552 env->gpr[4] = 0; 553 env->gpr[5] = 0; 554 env->gpr[6] = EPAPR_MAGIC; 555 env->gpr[7] = mmubooke_initial_mapsize(env); 556 env->gpr[8] = 0; 557 env->gpr[9] = 0; 558 env->nip = bi->entry; 559 mmubooke_create_initial_mapping(env); 560 } 561 562 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 563 qemu_irq **irqs) 564 { 565 DeviceState *dev; 566 SysBusDevice *s; 567 int i, j, k; 568 569 dev = qdev_create(NULL, TYPE_OPENPIC); 570 qdev_prop_set_uint32(dev, "model", params->mpic_version); 571 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 572 573 qdev_init_nofail(dev); 574 s = SYS_BUS_DEVICE(dev); 575 576 k = 0; 577 for (i = 0; i < smp_cpus; i++) { 578 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 579 sysbus_connect_irq(s, k++, irqs[i][j]); 580 } 581 } 582 583 return dev; 584 } 585 586 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 587 qemu_irq **irqs) 588 { 589 DeviceState *dev; 590 CPUState *cs; 591 int r; 592 593 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 594 qdev_prop_set_uint32(dev, "model", params->mpic_version); 595 596 r = qdev_init(dev); 597 if (r) { 598 return NULL; 599 } 600 601 CPU_FOREACH(cs) { 602 if (kvm_openpic_connect_vcpu(dev, cs)) { 603 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 604 __func__); 605 abort(); 606 } 607 } 608 609 return dev; 610 } 611 612 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr, 613 qemu_irq **irqs) 614 { 615 qemu_irq *mpic; 616 DeviceState *dev = NULL; 617 SysBusDevice *s; 618 int i; 619 620 mpic = g_new0(qemu_irq, 256); 621 622 if (kvm_enabled()) { 623 QemuOpts *machine_opts = qemu_get_machine_opts(); 624 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 625 "kernel_irqchip", true); 626 bool irqchip_required = qemu_opt_get_bool(machine_opts, 627 "kernel_irqchip", false); 628 629 if (irqchip_allowed) { 630 dev = ppce500_init_mpic_kvm(params, irqs); 631 } 632 633 if (irqchip_required && !dev) { 634 fprintf(stderr, "%s: irqchip requested but unavailable\n", 635 __func__); 636 abort(); 637 } 638 } 639 640 if (!dev) { 641 dev = ppce500_init_mpic_qemu(params, irqs); 642 } 643 644 for (i = 0; i < 256; i++) { 645 mpic[i] = qdev_get_gpio_in(dev, i); 646 } 647 648 s = SYS_BUS_DEVICE(dev); 649 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 650 s->mmio[0].memory); 651 652 return mpic; 653 } 654 655 static void ppce500_power_off(void *opaque, int line, int on) 656 { 657 if (on) { 658 qemu_system_shutdown_request(); 659 } 660 } 661 662 void ppce500_init(MachineState *machine, PPCE500Params *params) 663 { 664 MemoryRegion *address_space_mem = get_system_memory(); 665 MemoryRegion *ram = g_new(MemoryRegion, 1); 666 PCIBus *pci_bus; 667 CPUPPCState *env = NULL; 668 uint64_t loadaddr; 669 hwaddr kernel_base = -1LL; 670 int kernel_size = 0; 671 hwaddr dt_base = 0; 672 hwaddr initrd_base = 0; 673 int initrd_size = 0; 674 hwaddr cur_base = 0; 675 char *filename; 676 hwaddr bios_entry = 0; 677 target_long bios_size; 678 struct boot_info *boot_info; 679 int dt_size; 680 int i; 681 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 682 * 4 respectively */ 683 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 684 qemu_irq **irqs, *mpic; 685 DeviceState *dev; 686 CPUPPCState *firstenv = NULL; 687 MemoryRegion *ccsr_addr_space; 688 SysBusDevice *s; 689 PPCE500CCSRState *ccsr; 690 691 /* Setup CPUs */ 692 if (machine->cpu_model == NULL) { 693 machine->cpu_model = "e500v2_v30"; 694 } 695 696 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 697 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 698 for (i = 0; i < smp_cpus; i++) { 699 PowerPCCPU *cpu; 700 CPUState *cs; 701 qemu_irq *input; 702 703 cpu = cpu_ppc_init(machine->cpu_model); 704 if (cpu == NULL) { 705 fprintf(stderr, "Unable to initialize CPU!\n"); 706 exit(1); 707 } 708 env = &cpu->env; 709 cs = CPU(cpu); 710 711 if (!firstenv) { 712 firstenv = env; 713 } 714 715 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 716 input = (qemu_irq *)env->irq_inputs; 717 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 718 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 719 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 720 env->mpic_iack = MPC8544_CCSRBAR_BASE + 721 MPC8544_MPIC_REGS_OFFSET + 0xa0; 722 723 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 724 725 /* Register reset handler */ 726 if (!i) { 727 /* Primary CPU */ 728 struct boot_info *boot_info; 729 boot_info = g_malloc0(sizeof(struct boot_info)); 730 qemu_register_reset(ppce500_cpu_reset, cpu); 731 env->load_info = boot_info; 732 } else { 733 /* Secondary CPUs */ 734 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 735 } 736 } 737 738 env = firstenv; 739 740 /* Fixup Memory size on a alignment boundary */ 741 ram_size &= ~(RAM_SIZES_ALIGN - 1); 742 machine->ram_size = ram_size; 743 744 /* Register Memory */ 745 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 746 memory_region_add_subregion(address_space_mem, 0, ram); 747 748 dev = qdev_create(NULL, "e500-ccsr"); 749 object_property_add_child(qdev_get_machine(), "e500-ccsr", 750 OBJECT(dev), NULL); 751 qdev_init_nofail(dev); 752 ccsr = CCSR(dev); 753 ccsr_addr_space = &ccsr->ccsr_space; 754 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, 755 ccsr_addr_space); 756 757 mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); 758 759 /* Serial */ 760 if (serial_hds[0]) { 761 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 762 0, mpic[42], 399193, 763 serial_hds[0], DEVICE_BIG_ENDIAN); 764 } 765 766 if (serial_hds[1]) { 767 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 768 0, mpic[42], 399193, 769 serial_hds[1], DEVICE_BIG_ENDIAN); 770 } 771 772 /* General Utility device */ 773 dev = qdev_create(NULL, "mpc8544-guts"); 774 qdev_init_nofail(dev); 775 s = SYS_BUS_DEVICE(dev); 776 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 777 sysbus_mmio_get_region(s, 0)); 778 779 /* PCI */ 780 dev = qdev_create(NULL, "e500-pcihost"); 781 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 782 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 783 qdev_init_nofail(dev); 784 s = SYS_BUS_DEVICE(dev); 785 for (i = 0; i < PCI_NUM_PINS; i++) { 786 sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]); 787 } 788 789 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 790 sysbus_mmio_get_region(s, 0)); 791 792 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 793 if (!pci_bus) 794 printf("couldn't create PCI controller!\n"); 795 796 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); 797 798 if (pci_bus) { 799 /* Register network interfaces. */ 800 for (i = 0; i < nb_nics; i++) { 801 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 802 } 803 } 804 805 /* Register spinning region */ 806 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 807 808 if (cur_base < (32 * 1024 * 1024)) { 809 /* u-boot occupies memory up to 32MB, so load blobs above */ 810 cur_base = (32 * 1024 * 1024); 811 } 812 813 if (params->has_mpc8xxx_gpio) { 814 qemu_irq poweroff_irq; 815 816 dev = qdev_create(NULL, "mpc8xxx_gpio"); 817 s = SYS_BUS_DEVICE(dev); 818 qdev_init_nofail(dev); 819 sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]); 820 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 821 sysbus_mmio_get_region(s, 0)); 822 823 /* Power Off GPIO at Pin 0 */ 824 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 825 qdev_connect_gpio_out(dev, 0, poweroff_irq); 826 } 827 828 /* Load kernel. */ 829 if (machine->kernel_filename) { 830 kernel_base = cur_base; 831 kernel_size = load_image_targphys(machine->kernel_filename, 832 cur_base, 833 ram_size - cur_base); 834 if (kernel_size < 0) { 835 fprintf(stderr, "qemu: could not load kernel '%s'\n", 836 machine->kernel_filename); 837 exit(1); 838 } 839 840 cur_base += kernel_size; 841 } 842 843 /* Load initrd. */ 844 if (machine->initrd_filename) { 845 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 846 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 847 ram_size - initrd_base); 848 849 if (initrd_size < 0) { 850 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 851 machine->initrd_filename); 852 exit(1); 853 } 854 855 cur_base = initrd_base + initrd_size; 856 } 857 858 /* 859 * Smart firmware defaults ahead! 860 * 861 * We follow the following table to select which payload we execute. 862 * 863 * -kernel | -bios | payload 864 * ---------+-------+--------- 865 * N | Y | u-boot 866 * N | N | u-boot 867 * Y | Y | u-boot 868 * Y | N | kernel 869 * 870 * This ensures backwards compatibility with how we used to expose 871 * -kernel to users but allows them to run through u-boot as well. 872 */ 873 if (bios_name == NULL) { 874 if (machine->kernel_filename) { 875 bios_name = machine->kernel_filename; 876 } else { 877 bios_name = "u-boot.e500"; 878 } 879 } 880 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 881 882 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 883 1, ELF_MACHINE, 0); 884 if (bios_size < 0) { 885 /* 886 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 887 * ePAPR compliant kernel 888 */ 889 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 890 NULL, NULL); 891 if (kernel_size < 0) { 892 fprintf(stderr, "qemu: could not load firmware '%s'\n", filename); 893 exit(1); 894 } 895 } 896 897 /* Reserve space for dtb */ 898 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 899 900 dt_size = ppce500_prep_device_tree(machine, params, dt_base, 901 initrd_base, initrd_size, 902 kernel_base, kernel_size); 903 if (dt_size < 0) { 904 fprintf(stderr, "couldn't load device tree\n"); 905 exit(1); 906 } 907 assert(dt_size < DTB_MAX_SIZE); 908 909 boot_info = env->load_info; 910 boot_info->entry = bios_entry; 911 boot_info->dt_base = dt_base; 912 boot_info->dt_size = dt_size; 913 914 if (kvm_enabled()) { 915 kvmppc_init(); 916 } 917 } 918 919 static int e500_ccsr_initfn(SysBusDevice *dev) 920 { 921 PPCE500CCSRState *ccsr; 922 923 ccsr = CCSR(dev); 924 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 925 MPC8544_CCSRBAR_SIZE); 926 return 0; 927 } 928 929 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 930 { 931 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 932 k->init = e500_ccsr_initfn; 933 } 934 935 static const TypeInfo e500_ccsr_info = { 936 .name = TYPE_CCSR, 937 .parent = TYPE_SYS_BUS_DEVICE, 938 .instance_size = sizeof(PPCE500CCSRState), 939 .class_init = e500_ccsr_class_init, 940 }; 941 942 static void e500_register_types(void) 943 { 944 type_register_static(&e500_ccsr_info); 945 } 946 947 type_init(e500_register_types) 948