1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "net.h" 21 #include "hw/hw.h" 22 #include "hw/pc.h" 23 #include "hw/pci.h" 24 #include "hw/boards.h" 25 #include "sysemu.h" 26 #include "kvm.h" 27 #include "kvm_ppc.h" 28 #include "device_tree.h" 29 #include "hw/openpic.h" 30 #include "hw/ppc.h" 31 #include "hw/loader.h" 32 #include "elf.h" 33 #include "hw/sysbus.h" 34 #include "exec-memory.h" 35 #include "host-utils.h" 36 37 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 38 #define UIMAGE_LOAD_BASE 0 39 #define DTC_LOAD_PAD 0x500000 40 #define DTC_PAD_MASK 0xFFFFF 41 #define INITRD_LOAD_PAD 0x2000000 42 #define INITRD_PAD_MASK 0xFFFFFF 43 44 #define RAM_SIZES_ALIGN (64UL << 20) 45 46 /* TODO: parameterize */ 47 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 48 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 49 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000ULL) 50 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500ULL) 51 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600ULL) 52 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL) 53 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 54 #define MPC8544_PCI_IO 0xE1000000ULL 55 #define MPC8544_PCI_IOLEN 0x10000ULL 56 #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL) 57 #define MPC8544_SPIN_BASE 0xEF000000ULL 58 59 struct boot_info 60 { 61 uint32_t dt_base; 62 uint32_t dt_size; 63 uint32_t entry; 64 }; 65 66 static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic) 67 { 68 int i; 69 const uint32_t tmp[] = { 70 /* IDSEL 0x11 J17 Slot 1 */ 71 0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1, 72 0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1, 73 0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1, 74 0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 75 76 /* IDSEL 0x12 J16 Slot 2 */ 77 0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1, 78 0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1, 79 0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1, 80 0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 81 }; 82 for (i = 0; i < (7 * 8); i++) { 83 pci_map[i] = cpu_to_be32(tmp[i]); 84 } 85 } 86 87 static void dt_serial_create(void *fdt, unsigned long long offset, 88 const char *soc, const char *mpic, 89 const char *alias, int idx, bool defcon) 90 { 91 char ser[128]; 92 93 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 94 qemu_devtree_add_subnode(fdt, ser); 95 qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); 96 qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); 97 qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); 98 qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); 99 qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); 100 qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); 101 qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 102 qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); 103 104 if (defcon) { 105 qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 106 } 107 } 108 109 static int ppce500_load_device_tree(CPUPPCState *env, 110 PPCE500Params *params, 111 target_phys_addr_t addr, 112 target_phys_addr_t initrd_base, 113 target_phys_addr_t initrd_size) 114 { 115 int ret = -1; 116 uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; 117 int fdt_size; 118 void *fdt; 119 uint8_t hypercall[16]; 120 uint32_t clock_freq = 400000000; 121 uint32_t tb_freq = 400000000; 122 int i; 123 const char *toplevel_compat = NULL; /* user override */ 124 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 125 char soc[128]; 126 char mpic[128]; 127 uint32_t mpic_ph; 128 char gutil[128]; 129 char pci[128]; 130 uint32_t pci_map[7 * 8]; 131 uint32_t pci_ranges[14] = 132 { 133 0x2000000, 0x0, 0xc0000000, 134 0x0, 0xc0000000, 135 0x0, 0x20000000, 136 137 0x1000000, 0x0, 0x0, 138 0x0, 0xe1000000, 139 0x0, 0x10000, 140 }; 141 QemuOpts *machine_opts; 142 const char *dumpdtb = NULL; 143 const char *dtb_file = NULL; 144 145 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); 146 if (machine_opts) { 147 dumpdtb = qemu_opt_get(machine_opts, "dumpdtb"); 148 dtb_file = qemu_opt_get(machine_opts, "dtb"); 149 toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 150 } 151 152 if (dtb_file) { 153 char *filename; 154 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 155 if (!filename) { 156 goto out; 157 } 158 159 fdt = load_device_tree(filename, &fdt_size); 160 if (!fdt) { 161 goto out; 162 } 163 goto done; 164 } 165 166 fdt = create_device_tree(&fdt_size); 167 if (fdt == NULL) { 168 goto out; 169 } 170 171 /* Manipulate device tree in memory. */ 172 qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); 173 qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); 174 175 qemu_devtree_add_subnode(fdt, "/memory"); 176 qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); 177 qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, 178 sizeof(mem_reg_property)); 179 180 qemu_devtree_add_subnode(fdt, "/chosen"); 181 if (initrd_size) { 182 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", 183 initrd_base); 184 if (ret < 0) { 185 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 186 } 187 188 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", 189 (initrd_base + initrd_size)); 190 if (ret < 0) { 191 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 192 } 193 } 194 195 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", 196 params->kernel_cmdline); 197 if (ret < 0) 198 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 199 200 if (kvm_enabled()) { 201 /* Read out host's frequencies */ 202 clock_freq = kvmppc_get_clockfreq(); 203 tb_freq = kvmppc_get_tbfreq(); 204 205 /* indicate KVM hypercall interface */ 206 qemu_devtree_add_subnode(fdt, "/hypervisor"); 207 qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", 208 "linux,kvm"); 209 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 210 qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", 211 hypercall, sizeof(hypercall)); 212 } 213 214 /* Create CPU nodes */ 215 qemu_devtree_add_subnode(fdt, "/cpus"); 216 qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); 217 qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); 218 219 /* We need to generate the cpu nodes in reverse order, so Linux can pick 220 the first node as boot node and be happy */ 221 for (i = smp_cpus - 1; i >= 0; i--) { 222 char cpu_name[128]; 223 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 224 225 for (env = first_cpu; env != NULL; env = env->next_cpu) { 226 if (env->cpu_index == i) { 227 break; 228 } 229 } 230 231 if (!env) { 232 continue; 233 } 234 235 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); 236 qemu_devtree_add_subnode(fdt, cpu_name); 237 qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 238 qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 239 qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); 240 qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); 241 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", 242 env->dcache_line_size); 243 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", 244 env->icache_line_size); 245 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 246 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 247 qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 248 if (env->cpu_index) { 249 qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); 250 qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); 251 qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", 252 cpu_release_addr); 253 } else { 254 qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); 255 } 256 } 257 258 qemu_devtree_add_subnode(fdt, "/aliases"); 259 /* XXX These should go into their respective devices' code */ 260 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 261 qemu_devtree_add_subnode(fdt, soc); 262 qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); 263 qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, 264 sizeof(compatible_sb)); 265 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); 266 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); 267 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, 268 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 269 MPC8544_CCSRBAR_SIZE); 270 /* XXX should contain a reasonable value */ 271 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); 272 273 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, 274 MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE); 275 qemu_devtree_add_subnode(fdt, mpic); 276 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); 277 qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic"); 278 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE - 279 MPC8544_CCSRBAR_BASE, 0x40000); 280 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); 281 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 282 mpic_ph = qemu_devtree_alloc_phandle(fdt); 283 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); 284 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 285 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 286 287 /* 288 * We have to generate ser1 first, because Linux takes the first 289 * device it finds in the dt as serial output device. And we generate 290 * devices in reverse order to the dt. 291 */ 292 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE, 293 soc, mpic, "serial1", 1, false); 294 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE, 295 soc, mpic, "serial0", 0, true); 296 297 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 298 MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE); 299 qemu_devtree_add_subnode(fdt, gutil); 300 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 301 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE - 302 MPC8544_CCSRBAR_BASE, 0x1000); 303 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 304 305 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 306 qemu_devtree_add_subnode(fdt, pci); 307 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); 308 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 309 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); 310 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 311 0x0, 0x7); 312 pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic)); 313 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map)); 314 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 315 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); 316 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); 317 for (i = 0; i < 14; i++) { 318 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 319 } 320 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 321 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 322 MPC8544_PCI_REGS_BASE, 0, 0x1000); 323 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); 324 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); 325 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); 326 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); 327 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); 328 329 params->fixup_devtree(params, fdt); 330 331 if (toplevel_compat) { 332 qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, 333 strlen(toplevel_compat) + 1); 334 } 335 336 done: 337 if (dumpdtb) { 338 /* Dump the dtb to a file and quit */ 339 FILE *f = fopen(dumpdtb, "wb"); 340 size_t len; 341 len = fwrite(fdt, fdt_size, 1, f); 342 fclose(f); 343 if (len != fdt_size) { 344 exit(1); 345 } 346 exit(0); 347 } 348 349 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 350 if (ret < 0) { 351 goto out; 352 } 353 g_free(fdt); 354 ret = fdt_size; 355 356 out: 357 358 return ret; 359 } 360 361 /* Create -kernel TLB entries for BookE. */ 362 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) 363 { 364 return 63 - clz64(size >> 10); 365 } 366 367 static void mmubooke_create_initial_mapping(CPUPPCState *env) 368 { 369 struct boot_info *bi = env->load_info; 370 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 371 target_phys_addr_t size, dt_end; 372 int ps; 373 374 /* Our initial TLB entry needs to cover everything from 0 to 375 the device tree top */ 376 dt_end = bi->dt_base + bi->dt_size; 377 ps = booke206_page_size_to_tlb(dt_end) + 1; 378 size = (ps << MAS1_TSIZE_SHIFT); 379 tlb->mas1 = MAS1_VALID | size; 380 tlb->mas2 = 0; 381 tlb->mas7_3 = 0; 382 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 383 384 env->tlb_dirty = true; 385 } 386 387 static void ppce500_cpu_reset_sec(void *opaque) 388 { 389 PowerPCCPU *cpu = opaque; 390 CPUPPCState *env = &cpu->env; 391 392 cpu_reset(CPU(cpu)); 393 394 /* Secondary CPU starts in halted state for now. Needs to change when 395 implementing non-kernel boot. */ 396 env->halted = 1; 397 env->exception_index = EXCP_HLT; 398 } 399 400 static void ppce500_cpu_reset(void *opaque) 401 { 402 PowerPCCPU *cpu = opaque; 403 CPUPPCState *env = &cpu->env; 404 struct boot_info *bi = env->load_info; 405 406 cpu_reset(CPU(cpu)); 407 408 /* Set initial guest state. */ 409 env->halted = 0; 410 env->gpr[1] = (16<<20) - 8; 411 env->gpr[3] = bi->dt_base; 412 env->nip = bi->entry; 413 mmubooke_create_initial_mapping(env); 414 } 415 416 void ppce500_init(PPCE500Params *params) 417 { 418 MemoryRegion *address_space_mem = get_system_memory(); 419 MemoryRegion *ram = g_new(MemoryRegion, 1); 420 PCIBus *pci_bus; 421 CPUPPCState *env = NULL; 422 uint64_t elf_entry; 423 uint64_t elf_lowaddr; 424 target_phys_addr_t entry=0; 425 target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; 426 target_long kernel_size=0; 427 target_ulong dt_base = 0; 428 target_ulong initrd_base = 0; 429 target_long initrd_size=0; 430 int i=0; 431 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; 432 qemu_irq **irqs, *mpic; 433 DeviceState *dev; 434 CPUPPCState *firstenv = NULL; 435 436 /* Setup CPUs */ 437 if (params->cpu_model == NULL) { 438 params->cpu_model = "e500v2_v30"; 439 } 440 441 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 442 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 443 for (i = 0; i < smp_cpus; i++) { 444 PowerPCCPU *cpu; 445 qemu_irq *input; 446 447 cpu = cpu_ppc_init(params->cpu_model); 448 if (cpu == NULL) { 449 fprintf(stderr, "Unable to initialize CPU!\n"); 450 exit(1); 451 } 452 env = &cpu->env; 453 454 if (!firstenv) { 455 firstenv = env; 456 } 457 458 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 459 input = (qemu_irq *)env->irq_inputs; 460 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 461 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 462 env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; 463 env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000; 464 465 ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); 466 467 /* Register reset handler */ 468 if (!i) { 469 /* Primary CPU */ 470 struct boot_info *boot_info; 471 boot_info = g_malloc0(sizeof(struct boot_info)); 472 qemu_register_reset(ppce500_cpu_reset, cpu); 473 env->load_info = boot_info; 474 } else { 475 /* Secondary CPUs */ 476 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 477 } 478 } 479 480 env = firstenv; 481 482 /* Fixup Memory size on a alignment boundary */ 483 ram_size &= ~(RAM_SIZES_ALIGN - 1); 484 485 /* Register Memory */ 486 memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); 487 vmstate_register_ram_global(ram); 488 memory_region_add_subregion(address_space_mem, 0, ram); 489 490 /* MPIC */ 491 mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 492 smp_cpus, irqs, NULL); 493 494 if (!mpic) { 495 cpu_abort(env, "MPIC failed to initialize\n"); 496 } 497 498 /* Serial */ 499 if (serial_hds[0]) { 500 serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, 501 0, mpic[12+26], 399193, 502 serial_hds[0], DEVICE_BIG_ENDIAN); 503 } 504 505 if (serial_hds[1]) { 506 serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, 507 0, mpic[12+26], 399193, 508 serial_hds[0], DEVICE_BIG_ENDIAN); 509 } 510 511 /* General Utility device */ 512 sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); 513 514 /* PCI */ 515 dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, 516 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], 517 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], 518 NULL); 519 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 520 if (!pci_bus) 521 printf("couldn't create PCI controller!\n"); 522 523 isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); 524 525 if (pci_bus) { 526 /* Register network interfaces. */ 527 for (i = 0; i < nb_nics; i++) { 528 pci_nic_init_nofail(&nd_table[i], "virtio", NULL); 529 } 530 } 531 532 /* Register spinning region */ 533 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 534 535 /* Load kernel. */ 536 if (params->kernel_filename) { 537 kernel_size = load_uimage(params->kernel_filename, &entry, 538 &loadaddr, NULL); 539 if (kernel_size < 0) { 540 kernel_size = load_elf(params->kernel_filename, NULL, NULL, 541 &elf_entry, &elf_lowaddr, NULL, 1, 542 ELF_MACHINE, 0); 543 entry = elf_entry; 544 loadaddr = elf_lowaddr; 545 } 546 /* XXX try again as binary */ 547 if (kernel_size < 0) { 548 fprintf(stderr, "qemu: could not load kernel '%s'\n", 549 params->kernel_filename); 550 exit(1); 551 } 552 } 553 554 /* Load initrd. */ 555 if (params->initrd_filename) { 556 initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 557 initrd_size = load_image_targphys(params->initrd_filename, initrd_base, 558 ram_size - initrd_base); 559 560 if (initrd_size < 0) { 561 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 562 params->initrd_filename); 563 exit(1); 564 } 565 } 566 567 /* If we're loading a kernel directly, we must load the device tree too. */ 568 if (params->kernel_filename) { 569 struct boot_info *boot_info; 570 int dt_size; 571 572 dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 573 dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, 574 initrd_size); 575 if (dt_size < 0) { 576 fprintf(stderr, "couldn't load device tree\n"); 577 exit(1); 578 } 579 580 boot_info = env->load_info; 581 boot_info->entry = entry; 582 boot_info->dt_base = dt_base; 583 boot_info->dt_size = dt_size; 584 } 585 586 if (kvm_enabled()) { 587 kvmppc_init(); 588 } 589 } 590