1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "hw/sysbus.h" 36 #include "exec/address-spaces.h" 37 #include "qemu/host-utils.h" 38 #include "hw/pci-host/ppce500.h" 39 40 #define EPAPR_MAGIC (0x45504150) 41 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 42 #define UIMAGE_LOAD_BASE 0 43 #define DTC_LOAD_PAD 0x1800000 44 #define DTC_PAD_MASK 0xFFFFF 45 #define DTB_MAX_SIZE (8 * 1024 * 1024) 46 #define INITRD_LOAD_PAD 0x2000000 47 #define INITRD_PAD_MASK 0xFFFFFF 48 49 #define RAM_SIZES_ALIGN (64UL << 20) 50 51 /* TODO: parameterize */ 52 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 53 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 54 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 55 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 56 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 57 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 58 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 59 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ 60 MPC8544_PCI_REGS_OFFSET) 61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 62 #define MPC8544_PCI_IO 0xE1000000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8544_SPIN_BASE 0xEF000000ULL 65 66 struct boot_info 67 { 68 uint32_t dt_base; 69 uint32_t dt_size; 70 uint32_t entry; 71 }; 72 73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 74 int nr_slots, int *len) 75 { 76 int i = 0; 77 int slot; 78 int pci_irq; 79 int host_irq; 80 int last_slot = first_slot + nr_slots; 81 uint32_t *pci_map; 82 83 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 84 pci_map = g_malloc(*len); 85 86 for (slot = first_slot; slot < last_slot; slot++) { 87 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 88 pci_map[i++] = cpu_to_be32(slot << 11); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(pci_irq + 1); 92 pci_map[i++] = cpu_to_be32(mpic); 93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 94 pci_map[i++] = cpu_to_be32(host_irq + 1); 95 pci_map[i++] = cpu_to_be32(0x1); 96 } 97 } 98 99 assert((i * sizeof(uint32_t)) == *len); 100 101 return pci_map; 102 } 103 104 static void dt_serial_create(void *fdt, unsigned long long offset, 105 const char *soc, const char *mpic, 106 const char *alias, int idx, bool defcon) 107 { 108 char ser[128]; 109 110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 111 qemu_devtree_add_subnode(fdt, ser); 112 qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); 113 qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); 114 qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); 115 qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); 116 qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); 117 qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); 118 qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 119 qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); 120 121 if (defcon) { 122 qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 123 } 124 } 125 126 static int ppce500_load_device_tree(CPUPPCState *env, 127 PPCE500Params *params, 128 hwaddr addr, 129 hwaddr initrd_base, 130 hwaddr initrd_size) 131 { 132 int ret = -1; 133 uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; 134 int fdt_size; 135 void *fdt; 136 uint8_t hypercall[16]; 137 uint32_t clock_freq = 400000000; 138 uint32_t tb_freq = 400000000; 139 int i; 140 const char *toplevel_compat = NULL; /* user override */ 141 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 142 char soc[128]; 143 char mpic[128]; 144 uint32_t mpic_ph; 145 uint32_t msi_ph; 146 char gutil[128]; 147 char pci[128]; 148 char msi[128]; 149 uint32_t *pci_map = NULL; 150 int len; 151 uint32_t pci_ranges[14] = 152 { 153 0x2000000, 0x0, 0xc0000000, 154 0x0, 0xc0000000, 155 0x0, 0x20000000, 156 157 0x1000000, 0x0, 0x0, 158 0x0, 0xe1000000, 159 0x0, 0x10000, 160 }; 161 QemuOpts *machine_opts; 162 const char *dtb_file = NULL; 163 164 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); 165 if (machine_opts) { 166 dtb_file = qemu_opt_get(machine_opts, "dtb"); 167 toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 168 } 169 170 if (dtb_file) { 171 char *filename; 172 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 173 if (!filename) { 174 goto out; 175 } 176 177 fdt = load_device_tree(filename, &fdt_size); 178 if (!fdt) { 179 goto out; 180 } 181 goto done; 182 } 183 184 fdt = create_device_tree(&fdt_size); 185 if (fdt == NULL) { 186 goto out; 187 } 188 189 /* Manipulate device tree in memory. */ 190 qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); 191 qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); 192 193 qemu_devtree_add_subnode(fdt, "/memory"); 194 qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); 195 qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, 196 sizeof(mem_reg_property)); 197 198 qemu_devtree_add_subnode(fdt, "/chosen"); 199 if (initrd_size) { 200 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", 201 initrd_base); 202 if (ret < 0) { 203 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 204 } 205 206 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", 207 (initrd_base + initrd_size)); 208 if (ret < 0) { 209 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 210 } 211 } 212 213 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", 214 params->kernel_cmdline); 215 if (ret < 0) 216 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 217 218 if (kvm_enabled()) { 219 /* Read out host's frequencies */ 220 clock_freq = kvmppc_get_clockfreq(); 221 tb_freq = kvmppc_get_tbfreq(); 222 223 /* indicate KVM hypercall interface */ 224 qemu_devtree_add_subnode(fdt, "/hypervisor"); 225 qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", 226 "linux,kvm"); 227 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 228 qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", 229 hypercall, sizeof(hypercall)); 230 /* if KVM supports the idle hcall, set property indicating this */ 231 if (kvmppc_get_hasidle(env)) { 232 qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 233 } 234 } 235 236 /* Create CPU nodes */ 237 qemu_devtree_add_subnode(fdt, "/cpus"); 238 qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); 239 qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); 240 241 /* We need to generate the cpu nodes in reverse order, so Linux can pick 242 the first node as boot node and be happy */ 243 for (i = smp_cpus - 1; i >= 0; i--) { 244 CPUState *cpu; 245 char cpu_name[128]; 246 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 247 248 cpu = qemu_get_cpu(i); 249 if (cpu == NULL) { 250 continue; 251 } 252 env = cpu->env_ptr; 253 254 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 255 cpu->cpu_index); 256 qemu_devtree_add_subnode(fdt, cpu_name); 257 qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 258 qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 259 qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); 260 qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index); 261 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", 262 env->dcache_line_size); 263 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", 264 env->icache_line_size); 265 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 266 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 267 qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 268 if (cpu->cpu_index) { 269 qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); 270 qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); 271 qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", 272 cpu_release_addr); 273 } else { 274 qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); 275 } 276 } 277 278 qemu_devtree_add_subnode(fdt, "/aliases"); 279 /* XXX These should go into their respective devices' code */ 280 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 281 qemu_devtree_add_subnode(fdt, soc); 282 qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); 283 qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, 284 sizeof(compatible_sb)); 285 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); 286 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); 287 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, 288 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 289 MPC8544_CCSRBAR_SIZE); 290 /* XXX should contain a reasonable value */ 291 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); 292 293 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 294 qemu_devtree_add_subnode(fdt, mpic); 295 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); 296 qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 297 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 298 0x40000); 299 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); 300 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 301 mpic_ph = qemu_devtree_alloc_phandle(fdt); 302 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); 303 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 304 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 305 306 /* 307 * We have to generate ser1 first, because Linux takes the first 308 * device it finds in the dt as serial output device. And we generate 309 * devices in reverse order to the dt. 310 */ 311 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 312 soc, mpic, "serial1", 1, false); 313 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 314 soc, mpic, "serial0", 0, true); 315 316 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 317 MPC8544_UTIL_OFFSET); 318 qemu_devtree_add_subnode(fdt, gutil); 319 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 320 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 321 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 322 323 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 324 qemu_devtree_add_subnode(fdt, msi); 325 qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 326 qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 327 msi_ph = qemu_devtree_alloc_phandle(fdt); 328 qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 329 qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 330 qemu_devtree_setprop_cells(fdt, msi, "interrupts", 331 0xe0, 0x0, 332 0xe1, 0x0, 333 0xe2, 0x0, 334 0xe3, 0x0, 335 0xe4, 0x0, 336 0xe5, 0x0, 337 0xe6, 0x0, 338 0xe7, 0x0); 339 qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); 340 qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 341 342 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 343 qemu_devtree_add_subnode(fdt, pci); 344 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); 345 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 346 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); 347 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 348 0x0, 0x7); 349 pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), 350 params->pci_first_slot, params->pci_nr_slots, 351 &len); 352 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); 353 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 354 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); 355 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); 356 for (i = 0; i < 14; i++) { 357 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 358 } 359 qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 360 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 361 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 362 MPC8544_PCI_REGS_BASE, 0, 0x1000); 363 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); 364 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); 365 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); 366 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); 367 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); 368 369 params->fixup_devtree(params, fdt); 370 371 if (toplevel_compat) { 372 qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, 373 strlen(toplevel_compat) + 1); 374 } 375 376 done: 377 qemu_devtree_dumpdtb(fdt, fdt_size); 378 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 379 if (ret < 0) { 380 goto out; 381 } 382 g_free(fdt); 383 ret = fdt_size; 384 385 out: 386 g_free(pci_map); 387 388 return ret; 389 } 390 391 /* Create -kernel TLB entries for BookE. */ 392 static inline hwaddr booke206_page_size_to_tlb(uint64_t size) 393 { 394 return 63 - clz64(size >> 10); 395 } 396 397 static int booke206_initial_map_tsize(CPUPPCState *env) 398 { 399 struct boot_info *bi = env->load_info; 400 hwaddr dt_end; 401 int ps; 402 403 /* Our initial TLB entry needs to cover everything from 0 to 404 the device tree top */ 405 dt_end = bi->dt_base + bi->dt_size; 406 ps = booke206_page_size_to_tlb(dt_end) + 1; 407 if (ps & 1) { 408 /* e500v2 can only do even TLB size bits */ 409 ps++; 410 } 411 return ps; 412 } 413 414 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 415 { 416 int tsize; 417 418 tsize = booke206_initial_map_tsize(env); 419 return (1ULL << 10 << tsize); 420 } 421 422 static void mmubooke_create_initial_mapping(CPUPPCState *env) 423 { 424 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 425 hwaddr size; 426 int ps; 427 428 ps = booke206_initial_map_tsize(env); 429 size = (ps << MAS1_TSIZE_SHIFT); 430 tlb->mas1 = MAS1_VALID | size; 431 tlb->mas2 = 0; 432 tlb->mas7_3 = 0; 433 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 434 435 env->tlb_dirty = true; 436 } 437 438 static void ppce500_cpu_reset_sec(void *opaque) 439 { 440 PowerPCCPU *cpu = opaque; 441 CPUState *cs = CPU(cpu); 442 CPUPPCState *env = &cpu->env; 443 444 cpu_reset(cs); 445 446 /* Secondary CPU starts in halted state for now. Needs to change when 447 implementing non-kernel boot. */ 448 cs->halted = 1; 449 env->exception_index = EXCP_HLT; 450 } 451 452 static void ppce500_cpu_reset(void *opaque) 453 { 454 PowerPCCPU *cpu = opaque; 455 CPUState *cs = CPU(cpu); 456 CPUPPCState *env = &cpu->env; 457 struct boot_info *bi = env->load_info; 458 459 cpu_reset(cs); 460 461 /* Set initial guest state. */ 462 cs->halted = 0; 463 env->gpr[1] = (16<<20) - 8; 464 env->gpr[3] = bi->dt_base; 465 env->gpr[4] = 0; 466 env->gpr[5] = 0; 467 env->gpr[6] = EPAPR_MAGIC; 468 env->gpr[7] = mmubooke_initial_mapsize(env); 469 env->gpr[8] = 0; 470 env->gpr[9] = 0; 471 env->nip = bi->entry; 472 mmubooke_create_initial_mapping(env); 473 } 474 475 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 476 qemu_irq **irqs) 477 { 478 DeviceState *dev; 479 SysBusDevice *s; 480 int i, j, k; 481 482 dev = qdev_create(NULL, TYPE_OPENPIC); 483 qdev_prop_set_uint32(dev, "model", params->mpic_version); 484 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 485 486 qdev_init_nofail(dev); 487 s = SYS_BUS_DEVICE(dev); 488 489 k = 0; 490 for (i = 0; i < smp_cpus; i++) { 491 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 492 sysbus_connect_irq(s, k++, irqs[i][j]); 493 } 494 } 495 496 return dev; 497 } 498 499 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 500 qemu_irq **irqs) 501 { 502 DeviceState *dev; 503 CPUState *cs; 504 int r; 505 506 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 507 qdev_prop_set_uint32(dev, "model", params->mpic_version); 508 509 r = qdev_init(dev); 510 if (r) { 511 return NULL; 512 } 513 514 for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { 515 if (kvm_openpic_connect_vcpu(dev, cs)) { 516 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 517 __func__); 518 abort(); 519 } 520 } 521 522 return dev; 523 } 524 525 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr, 526 qemu_irq **irqs) 527 { 528 QemuOptsList *list; 529 qemu_irq *mpic; 530 DeviceState *dev = NULL; 531 SysBusDevice *s; 532 int i; 533 534 mpic = g_new(qemu_irq, 256); 535 536 if (kvm_enabled()) { 537 bool irqchip_allowed = true, irqchip_required = false; 538 539 list = qemu_find_opts("machine"); 540 if (!QTAILQ_EMPTY(&list->head)) { 541 irqchip_allowed = qemu_opt_get_bool(QTAILQ_FIRST(&list->head), 542 "kernel_irqchip", true); 543 irqchip_required = qemu_opt_get_bool(QTAILQ_FIRST(&list->head), 544 "kernel_irqchip", false); 545 } 546 547 if (irqchip_allowed) { 548 dev = ppce500_init_mpic_kvm(params, irqs); 549 } 550 551 if (irqchip_required && !dev) { 552 fprintf(stderr, "%s: irqchip requested but unavailable\n", 553 __func__); 554 abort(); 555 } 556 } 557 558 if (!dev) { 559 dev = ppce500_init_mpic_qemu(params, irqs); 560 } 561 562 for (i = 0; i < 256; i++) { 563 mpic[i] = qdev_get_gpio_in(dev, i); 564 } 565 566 s = SYS_BUS_DEVICE(dev); 567 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 568 s->mmio[0].memory); 569 570 return mpic; 571 } 572 573 void ppce500_init(PPCE500Params *params) 574 { 575 MemoryRegion *address_space_mem = get_system_memory(); 576 MemoryRegion *ram = g_new(MemoryRegion, 1); 577 PCIBus *pci_bus; 578 CPUPPCState *env = NULL; 579 uint64_t elf_entry; 580 uint64_t elf_lowaddr; 581 hwaddr entry=0; 582 hwaddr loadaddr=UIMAGE_LOAD_BASE; 583 target_long kernel_size=0; 584 target_ulong dt_base = 0; 585 target_ulong initrd_base = 0; 586 target_long initrd_size = 0; 587 target_ulong cur_base = 0; 588 int i; 589 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; 590 qemu_irq **irqs, *mpic; 591 DeviceState *dev; 592 CPUPPCState *firstenv = NULL; 593 MemoryRegion *ccsr_addr_space; 594 SysBusDevice *s; 595 PPCE500CCSRState *ccsr; 596 597 /* Setup CPUs */ 598 if (params->cpu_model == NULL) { 599 params->cpu_model = "e500v2_v30"; 600 } 601 602 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 603 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 604 for (i = 0; i < smp_cpus; i++) { 605 PowerPCCPU *cpu; 606 CPUState *cs; 607 qemu_irq *input; 608 609 cpu = cpu_ppc_init(params->cpu_model); 610 if (cpu == NULL) { 611 fprintf(stderr, "Unable to initialize CPU!\n"); 612 exit(1); 613 } 614 env = &cpu->env; 615 cs = CPU(cpu); 616 617 if (!firstenv) { 618 firstenv = env; 619 } 620 621 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 622 input = (qemu_irq *)env->irq_inputs; 623 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 624 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 625 env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; 626 env->mpic_iack = MPC8544_CCSRBAR_BASE + 627 MPC8544_MPIC_REGS_OFFSET + 0xa0; 628 629 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 630 631 /* Register reset handler */ 632 if (!i) { 633 /* Primary CPU */ 634 struct boot_info *boot_info; 635 boot_info = g_malloc0(sizeof(struct boot_info)); 636 qemu_register_reset(ppce500_cpu_reset, cpu); 637 env->load_info = boot_info; 638 } else { 639 /* Secondary CPUs */ 640 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 641 } 642 } 643 644 env = firstenv; 645 646 /* Fixup Memory size on a alignment boundary */ 647 ram_size &= ~(RAM_SIZES_ALIGN - 1); 648 params->ram_size = ram_size; 649 650 /* Register Memory */ 651 memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); 652 vmstate_register_ram_global(ram); 653 memory_region_add_subregion(address_space_mem, 0, ram); 654 655 dev = qdev_create(NULL, "e500-ccsr"); 656 object_property_add_child(qdev_get_machine(), "e500-ccsr", 657 OBJECT(dev), NULL); 658 qdev_init_nofail(dev); 659 ccsr = CCSR(dev); 660 ccsr_addr_space = &ccsr->ccsr_space; 661 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, 662 ccsr_addr_space); 663 664 mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); 665 666 /* Serial */ 667 if (serial_hds[0]) { 668 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 669 0, mpic[42], 399193, 670 serial_hds[0], DEVICE_BIG_ENDIAN); 671 } 672 673 if (serial_hds[1]) { 674 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 675 0, mpic[42], 399193, 676 serial_hds[1], DEVICE_BIG_ENDIAN); 677 } 678 679 /* General Utility device */ 680 dev = qdev_create(NULL, "mpc8544-guts"); 681 qdev_init_nofail(dev); 682 s = SYS_BUS_DEVICE(dev); 683 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 684 sysbus_mmio_get_region(s, 0)); 685 686 /* PCI */ 687 dev = qdev_create(NULL, "e500-pcihost"); 688 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 689 qdev_init_nofail(dev); 690 s = SYS_BUS_DEVICE(dev); 691 sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); 692 sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); 693 sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); 694 sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); 695 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 696 sysbus_mmio_get_region(s, 0)); 697 698 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 699 if (!pci_bus) 700 printf("couldn't create PCI controller!\n"); 701 702 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); 703 704 if (pci_bus) { 705 /* Register network interfaces. */ 706 for (i = 0; i < nb_nics; i++) { 707 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 708 } 709 } 710 711 /* Register spinning region */ 712 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 713 714 /* Load kernel. */ 715 if (params->kernel_filename) { 716 kernel_size = load_uimage(params->kernel_filename, &entry, 717 &loadaddr, NULL); 718 if (kernel_size < 0) { 719 kernel_size = load_elf(params->kernel_filename, NULL, NULL, 720 &elf_entry, &elf_lowaddr, NULL, 1, 721 ELF_MACHINE, 0); 722 entry = elf_entry; 723 loadaddr = elf_lowaddr; 724 } 725 /* XXX try again as binary */ 726 if (kernel_size < 0) { 727 fprintf(stderr, "qemu: could not load kernel '%s'\n", 728 params->kernel_filename); 729 exit(1); 730 } 731 732 cur_base = loadaddr + kernel_size; 733 734 /* Reserve space for dtb */ 735 dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 736 cur_base += DTB_MAX_SIZE; 737 } 738 739 /* Load initrd. */ 740 if (params->initrd_filename) { 741 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 742 initrd_size = load_image_targphys(params->initrd_filename, initrd_base, 743 ram_size - initrd_base); 744 745 if (initrd_size < 0) { 746 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 747 params->initrd_filename); 748 exit(1); 749 } 750 751 cur_base = initrd_base + initrd_size; 752 } 753 754 /* If we're loading a kernel directly, we must load the device tree too. */ 755 if (params->kernel_filename) { 756 struct boot_info *boot_info; 757 int dt_size; 758 759 dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, 760 initrd_size); 761 if (dt_size < 0) { 762 fprintf(stderr, "couldn't load device tree\n"); 763 exit(1); 764 } 765 assert(dt_size < DTB_MAX_SIZE); 766 767 boot_info = env->load_info; 768 boot_info->entry = entry; 769 boot_info->dt_base = dt_base; 770 boot_info->dt_size = dt_size; 771 } 772 773 if (kvm_enabled()) { 774 kvmppc_init(); 775 } 776 } 777 778 static int e500_ccsr_initfn(SysBusDevice *dev) 779 { 780 PPCE500CCSRState *ccsr; 781 782 ccsr = CCSR(dev); 783 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 784 MPC8544_CCSRBAR_SIZE); 785 return 0; 786 } 787 788 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 789 { 790 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 791 k->init = e500_ccsr_initfn; 792 } 793 794 static const TypeInfo e500_ccsr_info = { 795 .name = TYPE_CCSR, 796 .parent = TYPE_SYS_BUS_DEVICE, 797 .instance_size = sizeof(PPCE500CCSRState), 798 .class_init = e500_ccsr_class_init, 799 }; 800 801 static void e500_register_types(void) 802 { 803 type_register_static(&e500_ccsr_info); 804 } 805 806 type_init(e500_register_types) 807