xref: /openbmc/qemu/hw/ppc/e500.c (revision 9eb9350c0e519be97716f6b27f664bd0a3c41a36)
1 /*
2  * QEMU PowerPC e500-based platforms
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from hw/ppc440_bamboo.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qemu/guest-random.h"
21 #include "qapi/error.h"
22 #include "e500.h"
23 #include "e500-ccsr.h"
24 #include "net/net.h"
25 #include "qemu/config-file.h"
26 #include "hw/block/flash.h"
27 #include "hw/char/serial-mm.h"
28 #include "hw/pci/pci.h"
29 #include "sysemu/block-backend-io.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/reset.h"
33 #include "sysemu/runstate.h"
34 #include "kvm_ppc.h"
35 #include "sysemu/device_tree.h"
36 #include "hw/ppc/openpic.h"
37 #include "hw/ppc/openpic_kvm.h"
38 #include "hw/ppc/ppc.h"
39 #include "hw/qdev-properties.h"
40 #include "hw/loader.h"
41 #include "elf.h"
42 #include "hw/sysbus.h"
43 #include "qemu/host-utils.h"
44 #include "qemu/option.h"
45 #include "hw/pci-host/ppce500.h"
46 #include "qemu/error-report.h"
47 #include "hw/platform-bus.h"
48 #include "hw/net/fsl_etsec/etsec.h"
49 #include "hw/i2c/i2c.h"
50 #include "hw/irq.h"
51 #include "hw/sd/sdhci.h"
52 #include "hw/misc/unimp.h"
53 
54 #define EPAPR_MAGIC                (0x45504150)
55 #define DTC_LOAD_PAD               0x1800000
56 #define DTC_PAD_MASK               0xFFFFF
57 #define DTB_MAX_SIZE               (8 * MiB)
58 #define INITRD_LOAD_PAD            0x2000000
59 #define INITRD_PAD_MASK            0xFFFFFF
60 
61 #define RAM_SIZES_ALIGN            (64 * MiB)
62 
63 /* TODO: parameterize */
64 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
65 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
66 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
67 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
68 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
69 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
70 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
71 #define MPC85XX_ESDHC_REGS_OFFSET  0x2e000ULL
72 #define MPC85XX_ESDHC_REGS_SIZE    0x1000ULL
73 #define MPC8544_UTIL_OFFSET        0xe0000ULL
74 #define MPC8XXX_GPIO_OFFSET        0x000FF000ULL
75 #define MPC8544_I2C_REGS_OFFSET    0x3000ULL
76 #define MPC8XXX_GPIO_IRQ           47
77 #define MPC8544_I2C_IRQ            43
78 #define MPC85XX_ESDHC_IRQ          72
79 #define RTC_REGS_OFFSET            0x68
80 
81 #define PLATFORM_CLK_FREQ_HZ       (400 * 1000 * 1000)
82 
83 struct boot_info
84 {
85     uint32_t dt_base;
86     uint32_t dt_size;
87     uint32_t entry;
88 };
89 
90 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
91                                 int nr_slots, int *len)
92 {
93     int i = 0;
94     int slot;
95     int pci_irq;
96     int host_irq;
97     int last_slot = first_slot + nr_slots;
98     uint32_t *pci_map;
99 
100     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
101     pci_map = g_malloc(*len);
102 
103     for (slot = first_slot; slot < last_slot; slot++) {
104         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
105             pci_map[i++] = cpu_to_be32(slot << 11);
106             pci_map[i++] = cpu_to_be32(0x0);
107             pci_map[i++] = cpu_to_be32(0x0);
108             pci_map[i++] = cpu_to_be32(pci_irq + 1);
109             pci_map[i++] = cpu_to_be32(mpic);
110             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
111             pci_map[i++] = cpu_to_be32(host_irq + 1);
112             pci_map[i++] = cpu_to_be32(0x1);
113         }
114     }
115 
116     assert((i * sizeof(uint32_t)) == *len);
117 
118     return pci_map;
119 }
120 
121 static void dt_serial_create(void *fdt, unsigned long long offset,
122                              const char *soc, const char *mpic,
123                              const char *alias, int idx, bool defcon)
124 {
125     char *ser;
126 
127     ser = g_strdup_printf("%s/serial@%llx", soc, offset);
128     qemu_fdt_add_subnode(fdt, ser);
129     qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
130     qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
131     qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
132     qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
133     qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
134     qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
135     qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
136     qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
137 
138     if (defcon) {
139         /*
140          * "linux,stdout-path" and "stdout" properties are deprecated by linux
141          * kernel. New platforms should only use the "stdout-path" property. Set
142          * the new property and continue using older property to remain
143          * compatible with the existing firmware.
144          */
145         qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
146         qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
147     }
148     g_free(ser);
149 }
150 
151 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
152 {
153     hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
154     int irq0 = MPC8XXX_GPIO_IRQ;
155     gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
156     gchar *poweroff = g_strdup_printf("%s/power-off", soc);
157     int gpio_ph;
158 
159     qemu_fdt_add_subnode(fdt, node);
160     qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
161     qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
162     qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
163     qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
164     qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
165     qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
166     gpio_ph = qemu_fdt_alloc_phandle(fdt);
167     qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
168     qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
169 
170     /* Power Off Pin */
171     qemu_fdt_add_subnode(fdt, poweroff);
172     qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
173     qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
174 
175     g_free(node);
176     g_free(poweroff);
177 }
178 
179 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
180 {
181     int offset = RTC_REGS_OFFSET;
182 
183     gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
184     qemu_fdt_add_subnode(fdt, rtc);
185     qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
186     qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
187     qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
188 
189     g_free(rtc);
190 }
191 
192 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
193                              const char *alias)
194 {
195     hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
196     int irq0 = MPC8544_I2C_IRQ;
197 
198     gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
199     qemu_fdt_add_subnode(fdt, i2c);
200     qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
201     qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
202     qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
203     qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
204     qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
205     qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
206     qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
207 
208     g_free(i2c);
209 }
210 
211 static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
212 {
213     hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
214     hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
215     int irq = MPC85XX_ESDHC_IRQ;
216     g_autofree char *name = NULL;
217 
218     name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
219     qemu_fdt_add_subnode(fdt, name);
220     qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
221     qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
222     qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
223     qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
224     qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
225     qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
226 }
227 
228 typedef struct PlatformDevtreeData {
229     void *fdt;
230     const char *mpic;
231     int irq_start;
232     const char *node;
233     PlatformBusDevice *pbus;
234 } PlatformDevtreeData;
235 
236 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
237 {
238     eTSEC *etsec = ETSEC_COMMON(sbdev);
239     PlatformBusDevice *pbus = data->pbus;
240     hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
241     int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
242     int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
243     int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
244     gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0);
245     gchar *group = g_strdup_printf("%s/queue-group", node);
246     void *fdt = data->fdt;
247 
248     assert((int64_t)mmio0 >= 0);
249     assert(irq0 >= 0);
250     assert(irq1 >= 0);
251     assert(irq2 >= 0);
252 
253     qemu_fdt_add_subnode(fdt, node);
254     qemu_fdt_setprop(fdt, node, "ranges", NULL, 0);
255     qemu_fdt_setprop_string(fdt, node, "device_type", "network");
256     qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
257     qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
258     qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
259     qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
260     qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
261     qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
262 
263     qemu_fdt_add_subnode(fdt, group);
264     qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
265     qemu_fdt_setprop_cells(fdt, group, "interrupts",
266         data->irq_start + irq0, 0x2,
267         data->irq_start + irq1, 0x2,
268         data->irq_start + irq2, 0x2);
269 
270     g_free(node);
271     g_free(group);
272 
273     return 0;
274 }
275 
276 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
277 {
278     PlatformDevtreeData *data = opaque;
279     bool matched = false;
280 
281     if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
282         create_devtree_etsec(sbdev, data);
283         matched = true;
284     }
285 
286     if (!matched) {
287         error_report("Device %s is not supported by this machine yet.",
288                      qdev_fw_name(DEVICE(sbdev)));
289         exit(1);
290     }
291 }
292 
293 static void create_devtree_flash(SysBusDevice *sbdev,
294                                  PlatformDevtreeData *data)
295 {
296     g_autofree char *name = NULL;
297     uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
298                                                    "num-blocks",
299                                                    &error_fatal);
300     uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
301                                                       "sector-length",
302                                                       &error_fatal);
303     uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
304                                                    "width",
305                                                    &error_fatal);
306     hwaddr flashbase = 0;
307     hwaddr flashsize = num_blocks * sector_length;
308     void *fdt = data->fdt;
309 
310     name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
311     qemu_fdt_add_subnode(fdt, name);
312     qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
313     qemu_fdt_setprop_sized_cells(fdt, name, "reg",
314                                  1, flashbase, 1, flashsize);
315     qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
316 }
317 
318 static void platform_bus_create_devtree(PPCE500MachineState *pms,
319                                         void *fdt, const char *mpic)
320 {
321     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
322     gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
323     const char platcomp[] = "qemu,platform\0simple-bus";
324     uint64_t addr = pmc->platform_bus_base;
325     uint64_t size = pmc->platform_bus_size;
326     int irq_start = pmc->platform_bus_first_irq;
327     SysBusDevice *sbdev;
328     bool ambiguous;
329 
330     /* Create a /platform node that we can put all devices into */
331 
332     qemu_fdt_add_subnode(fdt, node);
333     qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
334 
335     /* Our platform bus region is less than 32bit big, so 1 cell is enough for
336        address and size */
337     qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
338     qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
339     qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
340 
341     qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
342 
343     /* Create dt nodes for dynamic devices */
344     PlatformDevtreeData data = {
345         .fdt = fdt,
346         .mpic = mpic,
347         .irq_start = irq_start,
348         .node = node,
349         .pbus = pms->pbus_dev,
350     };
351 
352     /* Loop through all dynamic sysbus devices and create nodes for them */
353     foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
354 
355     sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
356                                                     &ambiguous));
357     if (sbdev) {
358         assert(!ambiguous);
359         create_devtree_flash(sbdev, &data);
360     }
361 
362     g_free(node);
363 }
364 
365 static int ppce500_load_device_tree(PPCE500MachineState *pms,
366                                     hwaddr addr,
367                                     hwaddr initrd_base,
368                                     hwaddr initrd_size,
369                                     hwaddr kernel_base,
370                                     hwaddr kernel_size,
371                                     bool dry_run)
372 {
373     MachineState *machine = MACHINE(pms);
374     unsigned int smp_cpus = machine->smp.cpus;
375     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
376     CPUPPCState *env = cpu_env(first_cpu);
377     int ret = -1;
378     uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
379     int fdt_size;
380     void *fdt;
381     uint8_t hypercall[16];
382     uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
383     uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
384     int i;
385     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
386     char *soc;
387     char *mpic;
388     uint32_t mpic_ph;
389     uint32_t msi_ph;
390     char *gutil;
391     char *pci;
392     char *msi;
393     uint32_t *pci_map = NULL;
394     int len;
395     uint32_t pci_ranges[14] =
396         {
397             0x2000000, 0x0, pmc->pci_mmio_bus_base,
398             pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
399             0x0, 0x20000000,
400 
401             0x1000000, 0x0, 0x0,
402             pmc->pci_pio_base >> 32, pmc->pci_pio_base,
403             0x0, 0x10000,
404         };
405     const char *dtb_file = machine->dtb;
406     const char *toplevel_compat = machine->dt_compatible;
407     uint8_t rng_seed[32];
408 
409     if (dtb_file) {
410         char *filename;
411         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
412         if (!filename) {
413             goto out;
414         }
415 
416         fdt = load_device_tree(filename, &fdt_size);
417         g_free(filename);
418         if (!fdt) {
419             goto out;
420         }
421         goto done;
422     }
423 
424     fdt = create_device_tree(&fdt_size);
425     if (fdt == NULL) {
426         goto out;
427     }
428 
429     /* Manipulate device tree in memory. */
430     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
431     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
432 
433     qemu_fdt_add_subnode(fdt, "/memory");
434     qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
435     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
436                      sizeof(mem_reg_property));
437 
438     qemu_fdt_add_subnode(fdt, "/chosen");
439     if (initrd_size) {
440         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
441                                     initrd_base);
442         if (ret < 0) {
443             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
444         }
445 
446         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
447                                     (initrd_base + initrd_size));
448         if (ret < 0) {
449             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
450         }
451 
452     }
453 
454     if (kernel_base != -1ULL) {
455         qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
456                                      kernel_base >> 32, kernel_base,
457                                      kernel_size >> 32, kernel_size);
458     }
459 
460     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
461                                       machine->kernel_cmdline);
462     if (ret < 0)
463         fprintf(stderr, "couldn't set /chosen/bootargs\n");
464 
465     qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
466     qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
467 
468     if (kvm_enabled()) {
469         /* Read out host's frequencies */
470         clock_freq = kvmppc_get_clockfreq();
471         tb_freq = kvmppc_get_tbfreq();
472 
473         /* indicate KVM hypercall interface */
474         qemu_fdt_add_subnode(fdt, "/hypervisor");
475         qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
476                                 "linux,kvm");
477         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
478         qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
479                          hypercall, sizeof(hypercall));
480         /* if KVM supports the idle hcall, set property indicating this */
481         if (kvmppc_get_hasidle(env)) {
482             qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
483         }
484     }
485 
486     /* Create CPU nodes */
487     qemu_fdt_add_subnode(fdt, "/cpus");
488     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
489     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
490 
491     /* We need to generate the cpu nodes in reverse order, so Linux can pick
492        the first node as boot node and be happy */
493     for (i = smp_cpus - 1; i >= 0; i--) {
494         CPUState *cpu;
495         char *cpu_name;
496         uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
497 
498         cpu = qemu_get_cpu(i);
499         if (cpu == NULL) {
500             continue;
501         }
502         env = cpu_env(cpu);
503 
504         cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
505         qemu_fdt_add_subnode(fdt, cpu_name);
506         qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
507         qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
508         qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
509         qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
510         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
511                               env->dcache_line_size);
512         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
513                               env->icache_line_size);
514         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
515         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
516         qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
517         if (cpu->cpu_index) {
518             qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
519             qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
520                                     "spin-table");
521             qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
522                                  cpu_release_addr);
523         } else {
524             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
525         }
526         g_free(cpu_name);
527     }
528 
529     qemu_fdt_add_subnode(fdt, "/aliases");
530     /* XXX These should go into their respective devices' code */
531     soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
532     qemu_fdt_add_subnode(fdt, soc);
533     qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
534     qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
535                      sizeof(compatible_sb));
536     qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
537     qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
538     qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
539                            pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
540                            MPC8544_CCSRBAR_SIZE);
541     /* XXX should contain a reasonable value */
542     qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
543 
544     mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
545     qemu_fdt_add_subnode(fdt, mpic);
546     qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
547     qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
548     qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
549                            0x40000);
550     qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
551     qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
552     mpic_ph = qemu_fdt_alloc_phandle(fdt);
553     qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
554     qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
555     qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
556 
557     /*
558      * We have to generate ser1 first, because Linux takes the first
559      * device it finds in the dt as serial output device. And we generate
560      * devices in reverse order to the dt.
561      */
562     if (serial_hd(1)) {
563         dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
564                          soc, mpic, "serial1", 1, false);
565     }
566 
567     if (serial_hd(0)) {
568         dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
569                          soc, mpic, "serial0", 0, true);
570     }
571 
572     /* i2c */
573     dt_i2c_create(fdt, soc, mpic, "i2c");
574 
575     dt_rtc_create(fdt, "i2c", "rtc");
576 
577     /* sdhc */
578     if (pmc->has_esdhc) {
579         dt_sdhc_create(fdt, soc, mpic);
580     }
581 
582     gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
583                             MPC8544_UTIL_OFFSET);
584     qemu_fdt_add_subnode(fdt, gutil);
585     qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
586     qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
587     qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
588     g_free(gutil);
589 
590     msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
591     qemu_fdt_add_subnode(fdt, msi);
592     qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
593     qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
594     msi_ph = qemu_fdt_alloc_phandle(fdt);
595     qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
596     qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
597     qemu_fdt_setprop_cells(fdt, msi, "interrupts",
598         0xe0, 0x0,
599         0xe1, 0x0,
600         0xe2, 0x0,
601         0xe3, 0x0,
602         0xe4, 0x0,
603         0xe5, 0x0,
604         0xe6, 0x0,
605         0xe7, 0x0);
606     qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
607     qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
608     g_free(msi);
609 
610     pci = g_strdup_printf("/pci@%llx",
611                           pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
612     qemu_fdt_add_subnode(fdt, pci);
613     qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
614     qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
615     qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
616     qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
617                            0x0, 0x7);
618     pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
619                              pmc->pci_first_slot, pmc->pci_nr_slots,
620                              &len);
621     qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
622     qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
623     qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
624     qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
625     for (i = 0; i < 14; i++) {
626         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
627     }
628     qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
629     qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
630     qemu_fdt_setprop_cells(fdt, pci, "reg",
631                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
632                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
633                            0, 0x1000);
634     qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
635     qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
636     qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
637     qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
638     qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
639     g_free(pci);
640 
641     if (pmc->has_mpc8xxx_gpio) {
642         create_dt_mpc8xxx_gpio(fdt, soc, mpic);
643     }
644     g_free(soc);
645 
646     platform_bus_create_devtree(pms, fdt, mpic);
647 
648     g_free(mpic);
649 
650     pmc->fixup_devtree(fdt);
651 
652     if (toplevel_compat) {
653         qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
654                          strlen(toplevel_compat) + 1);
655     }
656 
657 done:
658     if (!dry_run) {
659         qemu_fdt_dumpdtb(fdt, fdt_size);
660         cpu_physical_memory_write(addr, fdt, fdt_size);
661 
662         /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
663         g_free(machine->fdt);
664         machine->fdt = fdt;
665     } else {
666         g_free(fdt);
667     }
668     ret = fdt_size;
669 
670 out:
671     g_free(pci_map);
672 
673     return ret;
674 }
675 
676 typedef struct DeviceTreeParams {
677     PPCE500MachineState *machine;
678     hwaddr addr;
679     hwaddr initrd_base;
680     hwaddr initrd_size;
681     hwaddr kernel_base;
682     hwaddr kernel_size;
683     Notifier notifier;
684 } DeviceTreeParams;
685 
686 static void ppce500_reset_device_tree(void *opaque)
687 {
688     DeviceTreeParams *p = opaque;
689     ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
690                              p->initrd_size, p->kernel_base, p->kernel_size,
691                              false);
692 }
693 
694 static void ppce500_init_notify(Notifier *notifier, void *data)
695 {
696     DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
697     ppce500_reset_device_tree(p);
698 }
699 
700 static int ppce500_prep_device_tree(PPCE500MachineState *machine,
701                                     hwaddr addr,
702                                     hwaddr initrd_base,
703                                     hwaddr initrd_size,
704                                     hwaddr kernel_base,
705                                     hwaddr kernel_size)
706 {
707     DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
708     p->machine = machine;
709     p->addr = addr;
710     p->initrd_base = initrd_base;
711     p->initrd_size = initrd_size;
712     p->kernel_base = kernel_base;
713     p->kernel_size = kernel_size;
714 
715     qemu_register_reset_nosnapshotload(ppce500_reset_device_tree, p);
716     p->notifier.notify = ppce500_init_notify;
717     qemu_add_machine_init_done_notifier(&p->notifier);
718 
719     /* Issue the device tree loader once, so that we get the size of the blob */
720     return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
721                                     kernel_base, kernel_size, true);
722 }
723 
724 static hwaddr booke206_page_size_to_tlb(uint64_t size)
725 {
726     return 63 - clz64(size / KiB);
727 }
728 
729 void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
730                       hwaddr len)
731 {
732     tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT;
733     tlb->mas1 |= MAS1_VALID;
734     tlb->mas2 = va & TARGET_PAGE_MASK;
735     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
736     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
737 }
738 
739 static int booke206_initial_map_tsize(CPUPPCState *env)
740 {
741     struct boot_info *bi = env->load_info;
742     hwaddr dt_end;
743     int ps;
744 
745     /* Our initial TLB entry needs to cover everything from 0 to
746        the device tree top */
747     dt_end = bi->dt_base + bi->dt_size;
748     ps = booke206_page_size_to_tlb(dt_end) + 1;
749     if (ps & 1) {
750         /* e500v2 can only do even TLB size bits */
751         ps++;
752     }
753     return ps;
754 }
755 
756 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
757 {
758     int tsize;
759 
760     tsize = booke206_initial_map_tsize(env);
761     return (1ULL << 10 << tsize);
762 }
763 
764 static void ppce500_cpu_reset_sec(void *opaque)
765 {
766     PowerPCCPU *cpu = opaque;
767     CPUState *cs = CPU(cpu);
768 
769     cpu_reset(cs);
770 
771     cs->exception_index = EXCP_HLT;
772 }
773 
774 static void ppce500_cpu_reset(void *opaque)
775 {
776     PowerPCCPU *cpu = opaque;
777     CPUState *cs = CPU(cpu);
778     CPUPPCState *env = &cpu->env;
779     struct boot_info *bi = env->load_info;
780     uint64_t map_size = mmubooke_initial_mapsize(env);
781     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
782 
783     cpu_reset(cs);
784 
785     /* Set initial guest state. */
786     cs->halted = 0;
787     env->gpr[1] = (16 * MiB) - 8;
788     env->gpr[3] = bi->dt_base;
789     env->gpr[4] = 0;
790     env->gpr[5] = 0;
791     env->gpr[6] = EPAPR_MAGIC;
792     env->gpr[7] = map_size;
793     env->gpr[8] = 0;
794     env->gpr[9] = 0;
795     env->nip = bi->entry;
796     /* create initial mapping */
797     booke206_set_tlb(tlb, 0, 0, map_size);
798 #ifdef CONFIG_KVM
799     env->tlb_dirty = true;
800 #endif
801 }
802 
803 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
804                                            IrqLines  *irqs)
805 {
806     DeviceState *dev;
807     SysBusDevice *s;
808     int i, j, k;
809     MachineState *machine = MACHINE(pms);
810     unsigned int smp_cpus = machine->smp.cpus;
811     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
812 
813     dev = qdev_new(TYPE_OPENPIC);
814     object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
815     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
816     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
817 
818     s = SYS_BUS_DEVICE(dev);
819     sysbus_realize_and_unref(s, &error_fatal);
820 
821     k = 0;
822     for (i = 0; i < smp_cpus; i++) {
823         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
824             sysbus_connect_irq(s, k++, irqs[i].irq[j]);
825         }
826     }
827 
828     return dev;
829 }
830 
831 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
832                                           IrqLines *irqs, Error **errp)
833 {
834 #ifdef CONFIG_KVM
835     DeviceState *dev;
836     CPUState *cs;
837 
838     dev = qdev_new(TYPE_KVM_OPENPIC);
839     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
840 
841     if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
842         object_unparent(OBJECT(dev));
843         return NULL;
844     }
845 
846     CPU_FOREACH(cs) {
847         if (kvm_openpic_connect_vcpu(dev, cs)) {
848             fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
849                     __func__);
850             abort();
851         }
852     }
853 
854     return dev;
855 #else
856     g_assert_not_reached();
857 #endif
858 }
859 
860 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
861                                       MemoryRegion *ccsr,
862                                       IrqLines *irqs)
863 {
864     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
865     DeviceState *dev = NULL;
866     SysBusDevice *s;
867 
868     if (kvm_enabled()) {
869         Error *err = NULL;
870 
871         if (kvm_kernel_irqchip_allowed()) {
872             dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
873         }
874         if (kvm_kernel_irqchip_required() && !dev) {
875             error_reportf_err(err,
876                               "kernel_irqchip requested but unavailable: ");
877             exit(1);
878         }
879     }
880 
881     if (!dev) {
882         dev = ppce500_init_mpic_qemu(pms, irqs);
883     }
884 
885     s = SYS_BUS_DEVICE(dev);
886     memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
887                                 s->mmio[0].memory);
888 
889     return dev;
890 }
891 
892 static void ppce500_power_off(void *opaque, int line, int on)
893 {
894     if (on) {
895         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
896     }
897 }
898 
899 void ppce500_init(MachineState *machine)
900 {
901     MemoryRegion *address_space_mem = get_system_memory();
902     PPCE500MachineState *pms = PPCE500_MACHINE(machine);
903     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
904     MachineClass *mc = MACHINE_CLASS(pmc);
905     PCIBus *pci_bus;
906     CPUPPCState *env = NULL;
907     uint64_t loadaddr;
908     hwaddr kernel_base = -1LL;
909     int kernel_size = 0;
910     hwaddr dt_base = 0;
911     hwaddr initrd_base = 0;
912     int initrd_size = 0;
913     hwaddr cur_base = 0;
914     char *filename;
915     const char *payload_name;
916     bool kernel_as_payload;
917     hwaddr bios_entry = 0;
918     target_long payload_size;
919     struct boot_info *boot_info = NULL;
920     int dt_size;
921     int i;
922     unsigned int smp_cpus = machine->smp.cpus;
923     /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
924      * 4 respectively */
925     unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
926     IrqLines *irqs;
927     DeviceState *dev, *mpicdev;
928     DriveInfo *dinfo;
929     CPUPPCState *firstenv = NULL;
930     MemoryRegion *ccsr_addr_space;
931     SysBusDevice *s;
932     PPCE500CCSRState *ccsr;
933     I2CBus *i2c;
934 
935     irqs = g_new0(IrqLines, smp_cpus);
936     for (i = 0; i < smp_cpus; i++) {
937         PowerPCCPU *cpu;
938         CPUState *cs;
939 
940         cpu = POWERPC_CPU(object_new(machine->cpu_type));
941         env = &cpu->env;
942         cs = CPU(cpu);
943 
944         if (env->mmu_model != POWERPC_MMU_BOOKE206) {
945             error_report("MMU model %i not supported by this machine",
946                          env->mmu_model);
947             exit(1);
948         }
949 
950         /*
951          * Secondary CPU starts in halted state for now. Needs to change
952          * when implementing non-kernel boot.
953          */
954         object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
955                                  &error_abort);
956         qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
957 
958         if (!firstenv) {
959             firstenv = env;
960         }
961 
962         irqs[i].irq[OPENPIC_OUTPUT_INT] =
963             qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT);
964         irqs[i].irq[OPENPIC_OUTPUT_CINT] =
965             qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT);
966         env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
967         env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
968 
969         ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
970 
971         /* Register reset handler */
972         if (!i) {
973             /* Primary CPU */
974             boot_info = g_new0(struct boot_info, 1);
975             qemu_register_reset(ppce500_cpu_reset, cpu);
976             env->load_info = boot_info;
977         } else {
978             /* Secondary CPUs */
979             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
980         }
981     }
982 
983     env = firstenv;
984 
985     if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
986         error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
987         exit(EXIT_FAILURE);
988     }
989 
990     /* Register Memory */
991     memory_region_add_subregion(address_space_mem, 0, machine->ram);
992 
993     dev = qdev_new("e500-ccsr");
994     object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
995     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
996     ccsr = CCSR(dev);
997     ccsr_addr_space = &ccsr->ccsr_space;
998     memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
999                                 ccsr_addr_space);
1000 
1001     mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
1002     g_free(irqs);
1003 
1004     /* Serial */
1005     if (serial_hd(0)) {
1006         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
1007                        0, qdev_get_gpio_in(mpicdev, 42), 399193,
1008                        serial_hd(0), DEVICE_BIG_ENDIAN);
1009     }
1010 
1011     if (serial_hd(1)) {
1012         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
1013                        0, qdev_get_gpio_in(mpicdev, 42), 399193,
1014                        serial_hd(1), DEVICE_BIG_ENDIAN);
1015     }
1016 
1017     /* I2C */
1018     dev = qdev_new("mpc-i2c");
1019     s = SYS_BUS_DEVICE(dev);
1020     sysbus_realize_and_unref(s, &error_fatal);
1021     sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
1022     memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
1023                                 sysbus_mmio_get_region(s, 0));
1024     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
1025     i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
1026 
1027     /* eSDHC */
1028     if (pmc->has_esdhc) {
1029         dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
1030         qdev_prop_set_string(dev, "name", "esdhc");
1031         qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE);
1032         s = SYS_BUS_DEVICE(dev);
1033         sysbus_realize_and_unref(s, &error_fatal);
1034         memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1035                                     sysbus_mmio_get_region(s, 0));
1036 
1037         /*
1038          * Compatible with:
1039          * - SD Host Controller Specification Version 2.0 Part A2
1040          * (See MPC8569E Reference Manual)
1041          */
1042         dev = qdev_new(TYPE_SYSBUS_SDHCI);
1043         qdev_prop_set_uint8(dev, "sd-spec-version", 2);
1044         qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
1045         s = SYS_BUS_DEVICE(dev);
1046         sysbus_realize_and_unref(s, &error_fatal);
1047         sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
1048         memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1049                                     sysbus_mmio_get_region(s, 0));
1050     }
1051 
1052     /* General Utility device */
1053     dev = qdev_new("mpc8544-guts");
1054     s = SYS_BUS_DEVICE(dev);
1055     sysbus_realize_and_unref(s, &error_fatal);
1056     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
1057                                 sysbus_mmio_get_region(s, 0));
1058 
1059     /* PCI */
1060     dev = qdev_new("e500-pcihost");
1061     object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
1062     qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
1063     qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
1064     s = SYS_BUS_DEVICE(dev);
1065     sysbus_realize_and_unref(s, &error_fatal);
1066     for (i = 0; i < PCI_NUM_PINS; i++) {
1067         sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
1068     }
1069 
1070     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
1071                                 sysbus_mmio_get_region(s, 0));
1072 
1073     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
1074     if (!pci_bus)
1075         printf("couldn't create PCI controller!\n");
1076 
1077     if (pci_bus) {
1078         /* Register network interfaces. */
1079         pci_init_nic_devices(pci_bus, mc->default_nic);
1080     }
1081 
1082     /* Register spinning region */
1083     sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
1084 
1085     if (pmc->has_mpc8xxx_gpio) {
1086         qemu_irq poweroff_irq;
1087 
1088         dev = qdev_new("mpc8xxx_gpio");
1089         s = SYS_BUS_DEVICE(dev);
1090         sysbus_realize_and_unref(s, &error_fatal);
1091         sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
1092         memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
1093                                     sysbus_mmio_get_region(s, 0));
1094 
1095         /* Power Off GPIO at Pin 0 */
1096         poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
1097         qdev_connect_gpio_out(dev, 0, poweroff_irq);
1098     }
1099 
1100     /* Platform Bus Device */
1101     dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1102     dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1103     qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1104     qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
1105     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1106     pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
1107 
1108     s = SYS_BUS_DEVICE(pms->pbus_dev);
1109     for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1110         int irqn = pmc->platform_bus_first_irq + i;
1111         sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
1112     }
1113 
1114     memory_region_add_subregion(address_space_mem,
1115                                 pmc->platform_bus_base,
1116                                 &pms->pbus_dev->mmio);
1117 
1118     dinfo = drive_get(IF_PFLASH, 0, 0);
1119     if (dinfo) {
1120         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
1121         BlockDriverState *bs = blk_bs(blk);
1122         uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio);
1123         uint64_t size = bdrv_getlength(bs);
1124         uint32_t sector_len = 64 * KiB;
1125 
1126         if (!is_power_of_2(size)) {
1127             error_report("Size of pflash file must be a power of two.");
1128             exit(1);
1129         }
1130 
1131         if (size > mmio_size) {
1132             error_report("Size of pflash file must not be bigger than %" PRIu64
1133                          " bytes.", mmio_size);
1134             exit(1);
1135         }
1136 
1137         if (!QEMU_IS_ALIGNED(size, sector_len)) {
1138             error_report("Size of pflash file must be a multiple of %" PRIu32
1139                          ".", sector_len);
1140             exit(1);
1141         }
1142 
1143         dev = qdev_new(TYPE_PFLASH_CFI01);
1144         qdev_prop_set_drive(dev, "drive", blk);
1145         qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
1146         qdev_prop_set_uint64(dev, "sector-length", sector_len);
1147         qdev_prop_set_uint8(dev, "width", 2);
1148         qdev_prop_set_bit(dev, "big-endian", true);
1149         qdev_prop_set_uint16(dev, "id0", 0x89);
1150         qdev_prop_set_uint16(dev, "id1", 0x18);
1151         qdev_prop_set_uint16(dev, "id2", 0x0000);
1152         qdev_prop_set_uint16(dev, "id3", 0x0);
1153         qdev_prop_set_string(dev, "name", "e500.flash");
1154         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1155 
1156         memory_region_add_subregion(&pms->pbus_dev->mmio, 0,
1157                                     pflash_cfi01_get_memory(PFLASH_CFI01(dev)));
1158     }
1159 
1160     /*
1161      * Smart firmware defaults ahead!
1162      *
1163      * We follow the following table to select which payload we execute.
1164      *
1165      *  -kernel | -bios | payload
1166      * ---------+-------+---------
1167      *     N    |   Y   | u-boot
1168      *     N    |   N   | u-boot
1169      *     Y    |   Y   | u-boot
1170      *     Y    |   N   | kernel
1171      *
1172      * This ensures backwards compatibility with how we used to expose
1173      * -kernel to users but allows them to run through u-boot as well.
1174      */
1175     kernel_as_payload = false;
1176     if (machine->firmware == NULL) {
1177         if (machine->kernel_filename) {
1178             payload_name = machine->kernel_filename;
1179             kernel_as_payload = true;
1180         } else {
1181             payload_name = "u-boot.e500";
1182         }
1183     } else {
1184         payload_name = machine->firmware;
1185     }
1186 
1187     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
1188     if (!filename) {
1189         error_report("could not find firmware/kernel file '%s'", payload_name);
1190         exit(1);
1191     }
1192 
1193     payload_size = load_elf(filename, NULL, NULL, NULL,
1194                             &bios_entry, &loadaddr, NULL, NULL,
1195                             1, PPC_ELF_MACHINE, 0, 0);
1196     if (payload_size < 0) {
1197         /*
1198          * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1199          * ePAPR compliant kernel
1200          */
1201         loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
1202         payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1203                                    NULL, NULL);
1204         if (payload_size < 0) {
1205             error_report("could not load firmware '%s'", filename);
1206             exit(1);
1207         }
1208     }
1209 
1210     g_free(filename);
1211 
1212     if (kernel_as_payload) {
1213         kernel_base = loadaddr;
1214         kernel_size = payload_size;
1215     }
1216 
1217     cur_base = loadaddr + payload_size;
1218     if (cur_base < 32 * MiB) {
1219         /* u-boot occupies memory up to 32MB, so load blobs above */
1220         cur_base = 32 * MiB;
1221     }
1222 
1223     /* Load bare kernel only if no bios/u-boot has been provided */
1224     if (machine->kernel_filename && !kernel_as_payload) {
1225         kernel_base = cur_base;
1226         kernel_size = load_image_targphys(machine->kernel_filename,
1227                                           cur_base,
1228                                           machine->ram_size - cur_base);
1229         if (kernel_size < 0) {
1230             error_report("could not load kernel '%s'",
1231                          machine->kernel_filename);
1232             exit(1);
1233         }
1234 
1235         cur_base += kernel_size;
1236     }
1237 
1238     /* Load initrd. */
1239     if (machine->initrd_filename) {
1240         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1241         initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1242                                           machine->ram_size - initrd_base);
1243 
1244         if (initrd_size < 0) {
1245             error_report("could not load initial ram disk '%s'",
1246                          machine->initrd_filename);
1247             exit(1);
1248         }
1249 
1250         cur_base = initrd_base + initrd_size;
1251     }
1252 
1253     /*
1254      * Reserve space for dtb behind the kernel image because Linux has a bug
1255      * where it can only handle the dtb if it's within the first 64MB of where
1256      * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1257      * ensures enough space between kernel and initrd.
1258      */
1259     dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1260     if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
1261             error_report("not enough memory for device tree");
1262             exit(1);
1263     }
1264 
1265     dt_size = ppce500_prep_device_tree(pms, dt_base,
1266                                        initrd_base, initrd_size,
1267                                        kernel_base, kernel_size);
1268     if (dt_size < 0) {
1269         error_report("couldn't load device tree");
1270         exit(1);
1271     }
1272     assert(dt_size < DTB_MAX_SIZE);
1273 
1274     boot_info->entry = bios_entry;
1275     boot_info->dt_base = dt_base;
1276     boot_info->dt_size = dt_size;
1277 }
1278 
1279 static void e500_ccsr_initfn(Object *obj)
1280 {
1281     PPCE500CCSRState *ccsr = CCSR(obj);
1282     memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1283                        MPC8544_CCSRBAR_SIZE);
1284 }
1285 
1286 static const TypeInfo e500_ccsr_info = {
1287     .name          = TYPE_CCSR,
1288     .parent        = TYPE_SYS_BUS_DEVICE,
1289     .instance_size = sizeof(PPCE500CCSRState),
1290     .instance_init = e500_ccsr_initfn,
1291 };
1292 
1293 static const TypeInfo ppce500_info = {
1294     .name          = TYPE_PPCE500_MACHINE,
1295     .parent        = TYPE_MACHINE,
1296     .abstract      = true,
1297     .instance_size = sizeof(PPCE500MachineState),
1298     .class_size    = sizeof(PPCE500MachineClass),
1299 };
1300 
1301 static void e500_register_types(void)
1302 {
1303     type_register_static(&e500_ccsr_info);
1304     type_register_static(&ppce500_info);
1305 }
1306 
1307 type_init(e500_register_types)
1308