1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "e500.h" 22 #include "e500-ccsr.h" 23 #include "net/net.h" 24 #include "qemu/config-file.h" 25 #include "hw/hw.h" 26 #include "hw/char/serial.h" 27 #include "hw/pci/pci.h" 28 #include "hw/boards.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "kvm_ppc.h" 32 #include "sysemu/device_tree.h" 33 #include "hw/ppc/openpic.h" 34 #include "hw/ppc/openpic_kvm.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/loader.h" 37 #include "elf.h" 38 #include "hw/sysbus.h" 39 #include "exec/address-spaces.h" 40 #include "qemu/host-utils.h" 41 #include "qemu/option.h" 42 #include "hw/pci-host/ppce500.h" 43 #include "qemu/error-report.h" 44 #include "hw/platform-bus.h" 45 #include "hw/net/fsl_etsec/etsec.h" 46 #include "hw/i2c/i2c.h" 47 48 #define EPAPR_MAGIC (0x45504150) 49 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 50 #define DTC_LOAD_PAD 0x1800000 51 #define DTC_PAD_MASK 0xFFFFF 52 #define DTB_MAX_SIZE (8 * MiB) 53 #define INITRD_LOAD_PAD 0x2000000 54 #define INITRD_PAD_MASK 0xFFFFFF 55 56 #define RAM_SIZES_ALIGN (64 * MiB) 57 58 /* TODO: parameterize */ 59 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 60 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 61 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 62 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 63 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 64 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 65 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 66 #define MPC8544_UTIL_OFFSET 0xe0000ULL 67 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 68 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 69 #define MPC8XXX_GPIO_IRQ 47 70 #define MPC8544_I2C_IRQ 43 71 #define RTC_REGS_OFFSET 0x68 72 73 struct boot_info 74 { 75 uint32_t dt_base; 76 uint32_t dt_size; 77 uint32_t entry; 78 }; 79 80 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 81 int nr_slots, int *len) 82 { 83 int i = 0; 84 int slot; 85 int pci_irq; 86 int host_irq; 87 int last_slot = first_slot + nr_slots; 88 uint32_t *pci_map; 89 90 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 91 pci_map = g_malloc(*len); 92 93 for (slot = first_slot; slot < last_slot; slot++) { 94 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 95 pci_map[i++] = cpu_to_be32(slot << 11); 96 pci_map[i++] = cpu_to_be32(0x0); 97 pci_map[i++] = cpu_to_be32(0x0); 98 pci_map[i++] = cpu_to_be32(pci_irq + 1); 99 pci_map[i++] = cpu_to_be32(mpic); 100 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 101 pci_map[i++] = cpu_to_be32(host_irq + 1); 102 pci_map[i++] = cpu_to_be32(0x1); 103 } 104 } 105 106 assert((i * sizeof(uint32_t)) == *len); 107 108 return pci_map; 109 } 110 111 static void dt_serial_create(void *fdt, unsigned long long offset, 112 const char *soc, const char *mpic, 113 const char *alias, int idx, bool defcon) 114 { 115 char *ser; 116 117 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 118 qemu_fdt_add_subnode(fdt, ser); 119 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 120 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 121 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 122 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 123 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 124 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 125 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 126 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 127 128 if (defcon) { 129 /* 130 * "linux,stdout-path" and "stdout" properties are deprecated by linux 131 * kernel. New platforms should only use the "stdout-path" property. Set 132 * the new property and continue using older property to remain 133 * compatible with the existing firmware. 134 */ 135 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 136 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 137 } 138 g_free(ser); 139 } 140 141 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 142 { 143 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 144 int irq0 = MPC8XXX_GPIO_IRQ; 145 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 146 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 147 int gpio_ph; 148 149 qemu_fdt_add_subnode(fdt, node); 150 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 151 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 152 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 153 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 154 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 155 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 156 gpio_ph = qemu_fdt_alloc_phandle(fdt); 157 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 158 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 159 160 /* Power Off Pin */ 161 qemu_fdt_add_subnode(fdt, poweroff); 162 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 163 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 164 165 g_free(node); 166 g_free(poweroff); 167 } 168 169 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 170 { 171 int offset = RTC_REGS_OFFSET; 172 173 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 174 qemu_fdt_add_subnode(fdt, rtc); 175 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 176 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 177 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 178 179 g_free(rtc); 180 } 181 182 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 183 const char *alias) 184 { 185 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 186 int irq0 = MPC8544_I2C_IRQ; 187 188 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 189 qemu_fdt_add_subnode(fdt, i2c); 190 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 191 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 192 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 193 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 194 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 195 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 196 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 197 198 g_free(i2c); 199 } 200 201 202 typedef struct PlatformDevtreeData { 203 void *fdt; 204 const char *mpic; 205 int irq_start; 206 const char *node; 207 PlatformBusDevice *pbus; 208 } PlatformDevtreeData; 209 210 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 211 { 212 eTSEC *etsec = ETSEC_COMMON(sbdev); 213 PlatformBusDevice *pbus = data->pbus; 214 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 215 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 216 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 217 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 218 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 219 gchar *group = g_strdup_printf("%s/queue-group", node); 220 void *fdt = data->fdt; 221 222 assert((int64_t)mmio0 >= 0); 223 assert(irq0 >= 0); 224 assert(irq1 >= 0); 225 assert(irq2 >= 0); 226 227 qemu_fdt_add_subnode(fdt, node); 228 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 229 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 230 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 231 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 232 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 233 234 qemu_fdt_add_subnode(fdt, group); 235 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 236 qemu_fdt_setprop_cells(fdt, group, "interrupts", 237 data->irq_start + irq0, 0x2, 238 data->irq_start + irq1, 0x2, 239 data->irq_start + irq2, 0x2); 240 241 g_free(node); 242 g_free(group); 243 244 return 0; 245 } 246 247 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 248 { 249 PlatformDevtreeData *data = opaque; 250 bool matched = false; 251 252 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 253 create_devtree_etsec(sbdev, data); 254 matched = true; 255 } 256 257 if (!matched) { 258 error_report("Device %s is not supported by this machine yet.", 259 qdev_fw_name(DEVICE(sbdev))); 260 exit(1); 261 } 262 } 263 264 static void platform_bus_create_devtree(PPCE500MachineState *pms, 265 void *fdt, const char *mpic) 266 { 267 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 268 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 269 const char platcomp[] = "qemu,platform\0simple-bus"; 270 uint64_t addr = pmc->platform_bus_base; 271 uint64_t size = pmc->platform_bus_size; 272 int irq_start = pmc->platform_bus_first_irq; 273 274 /* Create a /platform node that we can put all devices into */ 275 276 qemu_fdt_add_subnode(fdt, node); 277 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 278 279 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 280 address and size */ 281 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 282 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 283 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 284 285 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 286 287 /* Create dt nodes for dynamic devices */ 288 PlatformDevtreeData data = { 289 .fdt = fdt, 290 .mpic = mpic, 291 .irq_start = irq_start, 292 .node = node, 293 .pbus = pms->pbus_dev, 294 }; 295 296 /* Loop through all dynamic sysbus devices and create nodes for them */ 297 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 298 299 g_free(node); 300 } 301 302 static int ppce500_load_device_tree(PPCE500MachineState *pms, 303 hwaddr addr, 304 hwaddr initrd_base, 305 hwaddr initrd_size, 306 hwaddr kernel_base, 307 hwaddr kernel_size, 308 bool dry_run) 309 { 310 MachineState *machine = MACHINE(pms); 311 unsigned int smp_cpus = machine->smp.cpus; 312 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 313 CPUPPCState *env = first_cpu->env_ptr; 314 int ret = -1; 315 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 316 int fdt_size; 317 void *fdt; 318 uint8_t hypercall[16]; 319 uint32_t clock_freq = 400000000; 320 uint32_t tb_freq = 400000000; 321 int i; 322 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 323 char *soc; 324 char *mpic; 325 uint32_t mpic_ph; 326 uint32_t msi_ph; 327 char *gutil; 328 char *pci; 329 char *msi; 330 uint32_t *pci_map = NULL; 331 int len; 332 uint32_t pci_ranges[14] = 333 { 334 0x2000000, 0x0, pmc->pci_mmio_bus_base, 335 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 336 0x0, 0x20000000, 337 338 0x1000000, 0x0, 0x0, 339 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 340 0x0, 0x10000, 341 }; 342 QemuOpts *machine_opts = qemu_get_machine_opts(); 343 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 344 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 345 346 if (dtb_file) { 347 char *filename; 348 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 349 if (!filename) { 350 goto out; 351 } 352 353 fdt = load_device_tree(filename, &fdt_size); 354 g_free(filename); 355 if (!fdt) { 356 goto out; 357 } 358 goto done; 359 } 360 361 fdt = create_device_tree(&fdt_size); 362 if (fdt == NULL) { 363 goto out; 364 } 365 366 /* Manipulate device tree in memory. */ 367 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 368 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 369 370 qemu_fdt_add_subnode(fdt, "/memory"); 371 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 372 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 373 sizeof(mem_reg_property)); 374 375 qemu_fdt_add_subnode(fdt, "/chosen"); 376 if (initrd_size) { 377 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 378 initrd_base); 379 if (ret < 0) { 380 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 381 } 382 383 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 384 (initrd_base + initrd_size)); 385 if (ret < 0) { 386 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 387 } 388 389 } 390 391 if (kernel_base != -1ULL) { 392 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 393 kernel_base >> 32, kernel_base, 394 kernel_size >> 32, kernel_size); 395 } 396 397 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 398 machine->kernel_cmdline); 399 if (ret < 0) 400 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 401 402 if (kvm_enabled()) { 403 /* Read out host's frequencies */ 404 clock_freq = kvmppc_get_clockfreq(); 405 tb_freq = kvmppc_get_tbfreq(); 406 407 /* indicate KVM hypercall interface */ 408 qemu_fdt_add_subnode(fdt, "/hypervisor"); 409 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 410 "linux,kvm"); 411 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 412 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 413 hypercall, sizeof(hypercall)); 414 /* if KVM supports the idle hcall, set property indicating this */ 415 if (kvmppc_get_hasidle(env)) { 416 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 417 } 418 } 419 420 /* Create CPU nodes */ 421 qemu_fdt_add_subnode(fdt, "/cpus"); 422 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 423 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 424 425 /* We need to generate the cpu nodes in reverse order, so Linux can pick 426 the first node as boot node and be happy */ 427 for (i = smp_cpus - 1; i >= 0; i--) { 428 CPUState *cpu; 429 char *cpu_name; 430 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 431 432 cpu = qemu_get_cpu(i); 433 if (cpu == NULL) { 434 continue; 435 } 436 env = cpu->env_ptr; 437 438 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 439 qemu_fdt_add_subnode(fdt, cpu_name); 440 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 441 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 442 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 443 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 444 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 445 env->dcache_line_size); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 447 env->icache_line_size); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 450 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 451 if (cpu->cpu_index) { 452 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 453 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 454 "spin-table"); 455 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 456 cpu_release_addr); 457 } else { 458 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 459 } 460 g_free(cpu_name); 461 } 462 463 qemu_fdt_add_subnode(fdt, "/aliases"); 464 /* XXX These should go into their respective devices' code */ 465 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 466 qemu_fdt_add_subnode(fdt, soc); 467 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 468 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 469 sizeof(compatible_sb)); 470 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 471 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 472 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 473 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 474 MPC8544_CCSRBAR_SIZE); 475 /* XXX should contain a reasonable value */ 476 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 477 478 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 479 qemu_fdt_add_subnode(fdt, mpic); 480 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 481 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 482 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 483 0x40000); 484 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 485 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 486 mpic_ph = qemu_fdt_alloc_phandle(fdt); 487 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 488 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 489 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 490 491 /* 492 * We have to generate ser1 first, because Linux takes the first 493 * device it finds in the dt as serial output device. And we generate 494 * devices in reverse order to the dt. 495 */ 496 if (serial_hd(1)) { 497 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 498 soc, mpic, "serial1", 1, false); 499 } 500 501 if (serial_hd(0)) { 502 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 503 soc, mpic, "serial0", 0, true); 504 } 505 506 /* i2c */ 507 dt_i2c_create(fdt, soc, mpic, "i2c"); 508 509 dt_rtc_create(fdt, "i2c", "rtc"); 510 511 512 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 513 MPC8544_UTIL_OFFSET); 514 qemu_fdt_add_subnode(fdt, gutil); 515 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 516 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 517 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 518 g_free(gutil); 519 520 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 521 qemu_fdt_add_subnode(fdt, msi); 522 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 523 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 524 msi_ph = qemu_fdt_alloc_phandle(fdt); 525 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 526 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 527 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 528 0xe0, 0x0, 529 0xe1, 0x0, 530 0xe2, 0x0, 531 0xe3, 0x0, 532 0xe4, 0x0, 533 0xe5, 0x0, 534 0xe6, 0x0, 535 0xe7, 0x0); 536 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 537 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 538 g_free(msi); 539 540 pci = g_strdup_printf("/pci@%llx", 541 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 542 qemu_fdt_add_subnode(fdt, pci); 543 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 544 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 545 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 546 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 547 0x0, 0x7); 548 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 549 pmc->pci_first_slot, pmc->pci_nr_slots, 550 &len); 551 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 552 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 553 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 554 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 555 for (i = 0; i < 14; i++) { 556 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 557 } 558 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 559 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 560 qemu_fdt_setprop_cells(fdt, pci, "reg", 561 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 562 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 563 0, 0x1000); 564 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 565 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 566 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 567 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 568 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 569 g_free(pci); 570 571 if (pmc->has_mpc8xxx_gpio) { 572 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 573 } 574 g_free(soc); 575 576 if (pms->pbus_dev) { 577 platform_bus_create_devtree(pms, fdt, mpic); 578 } 579 g_free(mpic); 580 581 pmc->fixup_devtree(fdt); 582 583 if (toplevel_compat) { 584 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 585 strlen(toplevel_compat) + 1); 586 } 587 588 done: 589 if (!dry_run) { 590 qemu_fdt_dumpdtb(fdt, fdt_size); 591 cpu_physical_memory_write(addr, fdt, fdt_size); 592 } 593 ret = fdt_size; 594 595 out: 596 g_free(pci_map); 597 598 return ret; 599 } 600 601 typedef struct DeviceTreeParams { 602 PPCE500MachineState *machine; 603 hwaddr addr; 604 hwaddr initrd_base; 605 hwaddr initrd_size; 606 hwaddr kernel_base; 607 hwaddr kernel_size; 608 Notifier notifier; 609 } DeviceTreeParams; 610 611 static void ppce500_reset_device_tree(void *opaque) 612 { 613 DeviceTreeParams *p = opaque; 614 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 615 p->initrd_size, p->kernel_base, p->kernel_size, 616 false); 617 } 618 619 static void ppce500_init_notify(Notifier *notifier, void *data) 620 { 621 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 622 ppce500_reset_device_tree(p); 623 } 624 625 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 626 hwaddr addr, 627 hwaddr initrd_base, 628 hwaddr initrd_size, 629 hwaddr kernel_base, 630 hwaddr kernel_size) 631 { 632 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 633 p->machine = machine; 634 p->addr = addr; 635 p->initrd_base = initrd_base; 636 p->initrd_size = initrd_size; 637 p->kernel_base = kernel_base; 638 p->kernel_size = kernel_size; 639 640 qemu_register_reset(ppce500_reset_device_tree, p); 641 p->notifier.notify = ppce500_init_notify; 642 qemu_add_machine_init_done_notifier(&p->notifier); 643 644 /* Issue the device tree loader once, so that we get the size of the blob */ 645 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 646 kernel_base, kernel_size, true); 647 } 648 649 /* Create -kernel TLB entries for BookE. */ 650 hwaddr booke206_page_size_to_tlb(uint64_t size) 651 { 652 return 63 - clz64(size / KiB); 653 } 654 655 static int booke206_initial_map_tsize(CPUPPCState *env) 656 { 657 struct boot_info *bi = env->load_info; 658 hwaddr dt_end; 659 int ps; 660 661 /* Our initial TLB entry needs to cover everything from 0 to 662 the device tree top */ 663 dt_end = bi->dt_base + bi->dt_size; 664 ps = booke206_page_size_to_tlb(dt_end) + 1; 665 if (ps & 1) { 666 /* e500v2 can only do even TLB size bits */ 667 ps++; 668 } 669 return ps; 670 } 671 672 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 673 { 674 int tsize; 675 676 tsize = booke206_initial_map_tsize(env); 677 return (1ULL << 10 << tsize); 678 } 679 680 static void mmubooke_create_initial_mapping(CPUPPCState *env) 681 { 682 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 683 hwaddr size; 684 int ps; 685 686 ps = booke206_initial_map_tsize(env); 687 size = (ps << MAS1_TSIZE_SHIFT); 688 tlb->mas1 = MAS1_VALID | size; 689 tlb->mas2 = 0; 690 tlb->mas7_3 = 0; 691 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 692 693 env->tlb_dirty = true; 694 } 695 696 static void ppce500_cpu_reset_sec(void *opaque) 697 { 698 PowerPCCPU *cpu = opaque; 699 CPUState *cs = CPU(cpu); 700 701 cpu_reset(cs); 702 703 /* Secondary CPU starts in halted state for now. Needs to change when 704 implementing non-kernel boot. */ 705 cs->halted = 1; 706 cs->exception_index = EXCP_HLT; 707 } 708 709 static void ppce500_cpu_reset(void *opaque) 710 { 711 PowerPCCPU *cpu = opaque; 712 CPUState *cs = CPU(cpu); 713 CPUPPCState *env = &cpu->env; 714 struct boot_info *bi = env->load_info; 715 716 cpu_reset(cs); 717 718 /* Set initial guest state. */ 719 cs->halted = 0; 720 env->gpr[1] = (16 * MiB) - 8; 721 env->gpr[3] = bi->dt_base; 722 env->gpr[4] = 0; 723 env->gpr[5] = 0; 724 env->gpr[6] = EPAPR_MAGIC; 725 env->gpr[7] = mmubooke_initial_mapsize(env); 726 env->gpr[8] = 0; 727 env->gpr[9] = 0; 728 env->nip = bi->entry; 729 mmubooke_create_initial_mapping(env); 730 } 731 732 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 733 IrqLines *irqs) 734 { 735 DeviceState *dev; 736 SysBusDevice *s; 737 int i, j, k; 738 MachineState *machine = MACHINE(pms); 739 unsigned int smp_cpus = machine->smp.cpus; 740 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 741 742 dev = qdev_create(NULL, TYPE_OPENPIC); 743 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 744 &error_fatal); 745 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 746 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 747 748 qdev_init_nofail(dev); 749 s = SYS_BUS_DEVICE(dev); 750 751 k = 0; 752 for (i = 0; i < smp_cpus; i++) { 753 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 754 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 755 } 756 } 757 758 return dev; 759 } 760 761 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 762 IrqLines *irqs, Error **errp) 763 { 764 Error *err = NULL; 765 DeviceState *dev; 766 CPUState *cs; 767 768 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 769 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 770 771 object_property_set_bool(OBJECT(dev), true, "realized", &err); 772 if (err) { 773 error_propagate(errp, err); 774 object_unparent(OBJECT(dev)); 775 return NULL; 776 } 777 778 CPU_FOREACH(cs) { 779 if (kvm_openpic_connect_vcpu(dev, cs)) { 780 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 781 __func__); 782 abort(); 783 } 784 } 785 786 return dev; 787 } 788 789 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 790 MemoryRegion *ccsr, 791 IrqLines *irqs) 792 { 793 MachineState *machine = MACHINE(pms); 794 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 795 DeviceState *dev = NULL; 796 SysBusDevice *s; 797 798 if (kvm_enabled()) { 799 Error *err = NULL; 800 801 if (machine_kernel_irqchip_allowed(machine)) { 802 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 803 } 804 if (machine_kernel_irqchip_required(machine) && !dev) { 805 error_reportf_err(err, 806 "kernel_irqchip requested but unavailable: "); 807 exit(1); 808 } 809 } 810 811 if (!dev) { 812 dev = ppce500_init_mpic_qemu(pms, irqs); 813 } 814 815 s = SYS_BUS_DEVICE(dev); 816 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 817 s->mmio[0].memory); 818 819 return dev; 820 } 821 822 static void ppce500_power_off(void *opaque, int line, int on) 823 { 824 if (on) { 825 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 826 } 827 } 828 829 void ppce500_init(MachineState *machine) 830 { 831 MemoryRegion *address_space_mem = get_system_memory(); 832 MemoryRegion *ram = g_new(MemoryRegion, 1); 833 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 834 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 835 PCIBus *pci_bus; 836 CPUPPCState *env = NULL; 837 uint64_t loadaddr; 838 hwaddr kernel_base = -1LL; 839 int kernel_size = 0; 840 hwaddr dt_base = 0; 841 hwaddr initrd_base = 0; 842 int initrd_size = 0; 843 hwaddr cur_base = 0; 844 char *filename; 845 const char *payload_name; 846 bool kernel_as_payload; 847 hwaddr bios_entry = 0; 848 target_long payload_size; 849 struct boot_info *boot_info; 850 int dt_size; 851 int i; 852 unsigned int smp_cpus = machine->smp.cpus; 853 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 854 * 4 respectively */ 855 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 856 IrqLines *irqs; 857 DeviceState *dev, *mpicdev; 858 CPUPPCState *firstenv = NULL; 859 MemoryRegion *ccsr_addr_space; 860 SysBusDevice *s; 861 PPCE500CCSRState *ccsr; 862 I2CBus *i2c; 863 864 irqs = g_new0(IrqLines, smp_cpus); 865 for (i = 0; i < smp_cpus; i++) { 866 PowerPCCPU *cpu; 867 CPUState *cs; 868 qemu_irq *input; 869 870 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 871 env = &cpu->env; 872 cs = CPU(cpu); 873 874 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 875 error_report("MMU model %i not supported by this machine", 876 env->mmu_model); 877 exit(1); 878 } 879 880 if (!firstenv) { 881 firstenv = env; 882 } 883 884 input = (qemu_irq *)env->irq_inputs; 885 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 886 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 887 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 888 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 889 890 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 891 892 /* Register reset handler */ 893 if (!i) { 894 /* Primary CPU */ 895 struct boot_info *boot_info; 896 boot_info = g_malloc0(sizeof(struct boot_info)); 897 qemu_register_reset(ppce500_cpu_reset, cpu); 898 env->load_info = boot_info; 899 } else { 900 /* Secondary CPUs */ 901 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 902 } 903 } 904 905 env = firstenv; 906 907 /* Fixup Memory size on a alignment boundary */ 908 ram_size &= ~(RAM_SIZES_ALIGN - 1); 909 machine->ram_size = ram_size; 910 911 /* Register Memory */ 912 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 913 memory_region_add_subregion(address_space_mem, 0, ram); 914 915 dev = qdev_create(NULL, "e500-ccsr"); 916 object_property_add_child(qdev_get_machine(), "e500-ccsr", 917 OBJECT(dev), NULL); 918 qdev_init_nofail(dev); 919 ccsr = CCSR(dev); 920 ccsr_addr_space = &ccsr->ccsr_space; 921 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 922 ccsr_addr_space); 923 924 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 925 926 /* Serial */ 927 if (serial_hd(0)) { 928 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 929 0, qdev_get_gpio_in(mpicdev, 42), 399193, 930 serial_hd(0), DEVICE_BIG_ENDIAN); 931 } 932 933 if (serial_hd(1)) { 934 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 935 0, qdev_get_gpio_in(mpicdev, 42), 399193, 936 serial_hd(1), DEVICE_BIG_ENDIAN); 937 } 938 /* I2C */ 939 dev = qdev_create(NULL, "mpc-i2c"); 940 s = SYS_BUS_DEVICE(dev); 941 qdev_init_nofail(dev); 942 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 943 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 944 sysbus_mmio_get_region(s, 0)); 945 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 946 i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET); 947 948 949 /* General Utility device */ 950 dev = qdev_create(NULL, "mpc8544-guts"); 951 qdev_init_nofail(dev); 952 s = SYS_BUS_DEVICE(dev); 953 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 954 sysbus_mmio_get_region(s, 0)); 955 956 /* PCI */ 957 dev = qdev_create(NULL, "e500-pcihost"); 958 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 959 &error_abort); 960 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 961 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 962 qdev_init_nofail(dev); 963 s = SYS_BUS_DEVICE(dev); 964 for (i = 0; i < PCI_NUM_PINS; i++) { 965 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 966 } 967 968 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 969 sysbus_mmio_get_region(s, 0)); 970 971 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 972 if (!pci_bus) 973 printf("couldn't create PCI controller!\n"); 974 975 if (pci_bus) { 976 /* Register network interfaces. */ 977 for (i = 0; i < nb_nics; i++) { 978 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 979 } 980 } 981 982 /* Register spinning region */ 983 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 984 985 if (pmc->has_mpc8xxx_gpio) { 986 qemu_irq poweroff_irq; 987 988 dev = qdev_create(NULL, "mpc8xxx_gpio"); 989 s = SYS_BUS_DEVICE(dev); 990 qdev_init_nofail(dev); 991 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 992 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 993 sysbus_mmio_get_region(s, 0)); 994 995 /* Power Off GPIO at Pin 0 */ 996 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 997 qdev_connect_gpio_out(dev, 0, poweroff_irq); 998 } 999 1000 /* Platform Bus Device */ 1001 if (pmc->has_platform_bus) { 1002 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1003 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1004 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1005 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1006 qdev_init_nofail(dev); 1007 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1008 1009 s = SYS_BUS_DEVICE(pms->pbus_dev); 1010 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1011 int irqn = pmc->platform_bus_first_irq + i; 1012 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1013 } 1014 1015 memory_region_add_subregion(address_space_mem, 1016 pmc->platform_bus_base, 1017 sysbus_mmio_get_region(s, 0)); 1018 } 1019 1020 /* 1021 * Smart firmware defaults ahead! 1022 * 1023 * We follow the following table to select which payload we execute. 1024 * 1025 * -kernel | -bios | payload 1026 * ---------+-------+--------- 1027 * N | Y | u-boot 1028 * N | N | u-boot 1029 * Y | Y | u-boot 1030 * Y | N | kernel 1031 * 1032 * This ensures backwards compatibility with how we used to expose 1033 * -kernel to users but allows them to run through u-boot as well. 1034 */ 1035 kernel_as_payload = false; 1036 if (bios_name == NULL) { 1037 if (machine->kernel_filename) { 1038 payload_name = machine->kernel_filename; 1039 kernel_as_payload = true; 1040 } else { 1041 payload_name = "u-boot.e500"; 1042 } 1043 } else { 1044 payload_name = bios_name; 1045 } 1046 1047 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1048 1049 payload_size = load_elf(filename, NULL, NULL, NULL, 1050 &bios_entry, &loadaddr, NULL, 1051 1, PPC_ELF_MACHINE, 0, 0); 1052 if (payload_size < 0) { 1053 /* 1054 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1055 * ePAPR compliant kernel 1056 */ 1057 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1058 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1059 NULL, NULL); 1060 if (payload_size < 0) { 1061 error_report("could not load firmware '%s'", filename); 1062 exit(1); 1063 } 1064 } 1065 1066 g_free(filename); 1067 1068 if (kernel_as_payload) { 1069 kernel_base = loadaddr; 1070 kernel_size = payload_size; 1071 } 1072 1073 cur_base = loadaddr + payload_size; 1074 if (cur_base < 32 * MiB) { 1075 /* u-boot occupies memory up to 32MB, so load blobs above */ 1076 cur_base = 32 * MiB; 1077 } 1078 1079 /* Load bare kernel only if no bios/u-boot has been provided */ 1080 if (machine->kernel_filename && !kernel_as_payload) { 1081 kernel_base = cur_base; 1082 kernel_size = load_image_targphys(machine->kernel_filename, 1083 cur_base, 1084 ram_size - cur_base); 1085 if (kernel_size < 0) { 1086 error_report("could not load kernel '%s'", 1087 machine->kernel_filename); 1088 exit(1); 1089 } 1090 1091 cur_base += kernel_size; 1092 } 1093 1094 /* Load initrd. */ 1095 if (machine->initrd_filename) { 1096 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1097 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1098 ram_size - initrd_base); 1099 1100 if (initrd_size < 0) { 1101 error_report("could not load initial ram disk '%s'", 1102 machine->initrd_filename); 1103 exit(1); 1104 } 1105 1106 cur_base = initrd_base + initrd_size; 1107 } 1108 1109 /* 1110 * Reserve space for dtb behind the kernel image because Linux has a bug 1111 * where it can only handle the dtb if it's within the first 64MB of where 1112 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1113 * ensures enough space between kernel and initrd. 1114 */ 1115 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1116 if (dt_base + DTB_MAX_SIZE > ram_size) { 1117 error_report("not enough memory for device tree"); 1118 exit(1); 1119 } 1120 1121 dt_size = ppce500_prep_device_tree(pms, dt_base, 1122 initrd_base, initrd_size, 1123 kernel_base, kernel_size); 1124 if (dt_size < 0) { 1125 error_report("couldn't load device tree"); 1126 exit(1); 1127 } 1128 assert(dt_size < DTB_MAX_SIZE); 1129 1130 boot_info = env->load_info; 1131 boot_info->entry = bios_entry; 1132 boot_info->dt_base = dt_base; 1133 boot_info->dt_size = dt_size; 1134 } 1135 1136 static void e500_ccsr_initfn(Object *obj) 1137 { 1138 PPCE500CCSRState *ccsr = CCSR(obj); 1139 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1140 MPC8544_CCSRBAR_SIZE); 1141 } 1142 1143 static const TypeInfo e500_ccsr_info = { 1144 .name = TYPE_CCSR, 1145 .parent = TYPE_SYS_BUS_DEVICE, 1146 .instance_size = sizeof(PPCE500CCSRState), 1147 .instance_init = e500_ccsr_initfn, 1148 }; 1149 1150 static const TypeInfo ppce500_info = { 1151 .name = TYPE_PPCE500_MACHINE, 1152 .parent = TYPE_MACHINE, 1153 .abstract = true, 1154 .instance_size = sizeof(PPCE500MachineState), 1155 .class_size = sizeof(PPCE500MachineClass), 1156 }; 1157 1158 static void e500_register_types(void) 1159 { 1160 type_register_static(&e500_ccsr_info); 1161 type_register_static(&ppce500_info); 1162 } 1163 1164 type_init(e500_register_types) 1165