1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/datadir.h" 20 #include "qemu/units.h" 21 #include "qapi/error.h" 22 #include "e500.h" 23 #include "e500-ccsr.h" 24 #include "net/net.h" 25 #include "qemu/config-file.h" 26 #include "hw/char/serial.h" 27 #include "hw/pci/pci.h" 28 #include "hw/boards.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/reset.h" 32 #include "sysemu/runstate.h" 33 #include "kvm_ppc.h" 34 #include "sysemu/device_tree.h" 35 #include "hw/ppc/openpic.h" 36 #include "hw/ppc/openpic_kvm.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "hw/sysbus.h" 42 #include "exec/address-spaces.h" 43 #include "qemu/host-utils.h" 44 #include "qemu/option.h" 45 #include "hw/pci-host/ppce500.h" 46 #include "qemu/error-report.h" 47 #include "hw/platform-bus.h" 48 #include "hw/net/fsl_etsec/etsec.h" 49 #include "hw/i2c/i2c.h" 50 #include "hw/irq.h" 51 52 #define EPAPR_MAGIC (0x45504150) 53 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 54 #define DTC_LOAD_PAD 0x1800000 55 #define DTC_PAD_MASK 0xFFFFF 56 #define DTB_MAX_SIZE (8 * MiB) 57 #define INITRD_LOAD_PAD 0x2000000 58 #define INITRD_PAD_MASK 0xFFFFFF 59 60 #define RAM_SIZES_ALIGN (64 * MiB) 61 62 /* TODO: parameterize */ 63 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 64 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 65 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 66 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 67 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 68 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 69 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 70 #define MPC8544_UTIL_OFFSET 0xe0000ULL 71 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 72 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 73 #define MPC8XXX_GPIO_IRQ 47 74 #define MPC8544_I2C_IRQ 43 75 #define RTC_REGS_OFFSET 0x68 76 77 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 78 79 struct boot_info 80 { 81 uint32_t dt_base; 82 uint32_t dt_size; 83 uint32_t entry; 84 }; 85 86 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 87 int nr_slots, int *len) 88 { 89 int i = 0; 90 int slot; 91 int pci_irq; 92 int host_irq; 93 int last_slot = first_slot + nr_slots; 94 uint32_t *pci_map; 95 96 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 97 pci_map = g_malloc(*len); 98 99 for (slot = first_slot; slot < last_slot; slot++) { 100 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 101 pci_map[i++] = cpu_to_be32(slot << 11); 102 pci_map[i++] = cpu_to_be32(0x0); 103 pci_map[i++] = cpu_to_be32(0x0); 104 pci_map[i++] = cpu_to_be32(pci_irq + 1); 105 pci_map[i++] = cpu_to_be32(mpic); 106 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 107 pci_map[i++] = cpu_to_be32(host_irq + 1); 108 pci_map[i++] = cpu_to_be32(0x1); 109 } 110 } 111 112 assert((i * sizeof(uint32_t)) == *len); 113 114 return pci_map; 115 } 116 117 static void dt_serial_create(void *fdt, unsigned long long offset, 118 const char *soc, const char *mpic, 119 const char *alias, int idx, bool defcon) 120 { 121 char *ser; 122 123 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 124 qemu_fdt_add_subnode(fdt, ser); 125 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 126 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 127 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 128 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 129 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 130 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 131 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 132 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 133 134 if (defcon) { 135 /* 136 * "linux,stdout-path" and "stdout" properties are deprecated by linux 137 * kernel. New platforms should only use the "stdout-path" property. Set 138 * the new property and continue using older property to remain 139 * compatible with the existing firmware. 140 */ 141 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 142 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 143 } 144 g_free(ser); 145 } 146 147 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 148 { 149 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 150 int irq0 = MPC8XXX_GPIO_IRQ; 151 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 152 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 153 int gpio_ph; 154 155 qemu_fdt_add_subnode(fdt, node); 156 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 157 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 158 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 159 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 160 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 161 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 162 gpio_ph = qemu_fdt_alloc_phandle(fdt); 163 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 164 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 165 166 /* Power Off Pin */ 167 qemu_fdt_add_subnode(fdt, poweroff); 168 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 169 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 170 171 g_free(node); 172 g_free(poweroff); 173 } 174 175 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 176 { 177 int offset = RTC_REGS_OFFSET; 178 179 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 180 qemu_fdt_add_subnode(fdt, rtc); 181 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 182 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 183 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 184 185 g_free(rtc); 186 } 187 188 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 189 const char *alias) 190 { 191 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 192 int irq0 = MPC8544_I2C_IRQ; 193 194 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 195 qemu_fdt_add_subnode(fdt, i2c); 196 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 197 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 198 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 199 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 200 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 201 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 202 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 203 204 g_free(i2c); 205 } 206 207 208 typedef struct PlatformDevtreeData { 209 void *fdt; 210 const char *mpic; 211 int irq_start; 212 const char *node; 213 PlatformBusDevice *pbus; 214 } PlatformDevtreeData; 215 216 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 217 { 218 eTSEC *etsec = ETSEC_COMMON(sbdev); 219 PlatformBusDevice *pbus = data->pbus; 220 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 221 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 222 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 223 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 224 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 225 gchar *group = g_strdup_printf("%s/queue-group", node); 226 void *fdt = data->fdt; 227 228 assert((int64_t)mmio0 >= 0); 229 assert(irq0 >= 0); 230 assert(irq1 >= 0); 231 assert(irq2 >= 0); 232 233 qemu_fdt_add_subnode(fdt, node); 234 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 235 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 236 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 237 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 238 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 239 240 qemu_fdt_add_subnode(fdt, group); 241 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 242 qemu_fdt_setprop_cells(fdt, group, "interrupts", 243 data->irq_start + irq0, 0x2, 244 data->irq_start + irq1, 0x2, 245 data->irq_start + irq2, 0x2); 246 247 g_free(node); 248 g_free(group); 249 250 return 0; 251 } 252 253 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 254 { 255 PlatformDevtreeData *data = opaque; 256 bool matched = false; 257 258 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 259 create_devtree_etsec(sbdev, data); 260 matched = true; 261 } 262 263 if (!matched) { 264 error_report("Device %s is not supported by this machine yet.", 265 qdev_fw_name(DEVICE(sbdev))); 266 exit(1); 267 } 268 } 269 270 static void platform_bus_create_devtree(PPCE500MachineState *pms, 271 void *fdt, const char *mpic) 272 { 273 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 274 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 275 const char platcomp[] = "qemu,platform\0simple-bus"; 276 uint64_t addr = pmc->platform_bus_base; 277 uint64_t size = pmc->platform_bus_size; 278 int irq_start = pmc->platform_bus_first_irq; 279 280 /* Create a /platform node that we can put all devices into */ 281 282 qemu_fdt_add_subnode(fdt, node); 283 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 284 285 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 286 address and size */ 287 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 288 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 289 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 290 291 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 292 293 /* Create dt nodes for dynamic devices */ 294 PlatformDevtreeData data = { 295 .fdt = fdt, 296 .mpic = mpic, 297 .irq_start = irq_start, 298 .node = node, 299 .pbus = pms->pbus_dev, 300 }; 301 302 /* Loop through all dynamic sysbus devices and create nodes for them */ 303 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 304 305 g_free(node); 306 } 307 308 static int ppce500_load_device_tree(PPCE500MachineState *pms, 309 hwaddr addr, 310 hwaddr initrd_base, 311 hwaddr initrd_size, 312 hwaddr kernel_base, 313 hwaddr kernel_size, 314 bool dry_run) 315 { 316 MachineState *machine = MACHINE(pms); 317 unsigned int smp_cpus = machine->smp.cpus; 318 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 319 CPUPPCState *env = first_cpu->env_ptr; 320 int ret = -1; 321 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 322 int fdt_size; 323 void *fdt; 324 uint8_t hypercall[16]; 325 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 326 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 327 int i; 328 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 329 char *soc; 330 char *mpic; 331 uint32_t mpic_ph; 332 uint32_t msi_ph; 333 char *gutil; 334 char *pci; 335 char *msi; 336 uint32_t *pci_map = NULL; 337 int len; 338 uint32_t pci_ranges[14] = 339 { 340 0x2000000, 0x0, pmc->pci_mmio_bus_base, 341 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 342 0x0, 0x20000000, 343 344 0x1000000, 0x0, 0x0, 345 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 346 0x0, 0x10000, 347 }; 348 const char *dtb_file = machine->dtb; 349 const char *toplevel_compat = machine->dt_compatible; 350 351 if (dtb_file) { 352 char *filename; 353 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 354 if (!filename) { 355 goto out; 356 } 357 358 fdt = load_device_tree(filename, &fdt_size); 359 g_free(filename); 360 if (!fdt) { 361 goto out; 362 } 363 goto done; 364 } 365 366 fdt = create_device_tree(&fdt_size); 367 if (fdt == NULL) { 368 goto out; 369 } 370 371 /* Manipulate device tree in memory. */ 372 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 373 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 374 375 qemu_fdt_add_subnode(fdt, "/memory"); 376 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 377 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 378 sizeof(mem_reg_property)); 379 380 qemu_fdt_add_subnode(fdt, "/chosen"); 381 if (initrd_size) { 382 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 383 initrd_base); 384 if (ret < 0) { 385 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 386 } 387 388 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 389 (initrd_base + initrd_size)); 390 if (ret < 0) { 391 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 392 } 393 394 } 395 396 if (kernel_base != -1ULL) { 397 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 398 kernel_base >> 32, kernel_base, 399 kernel_size >> 32, kernel_size); 400 } 401 402 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 403 machine->kernel_cmdline); 404 if (ret < 0) 405 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 406 407 if (kvm_enabled()) { 408 /* Read out host's frequencies */ 409 clock_freq = kvmppc_get_clockfreq(); 410 tb_freq = kvmppc_get_tbfreq(); 411 412 /* indicate KVM hypercall interface */ 413 qemu_fdt_add_subnode(fdt, "/hypervisor"); 414 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 415 "linux,kvm"); 416 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 417 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 418 hypercall, sizeof(hypercall)); 419 /* if KVM supports the idle hcall, set property indicating this */ 420 if (kvmppc_get_hasidle(env)) { 421 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 422 } 423 } 424 425 /* Create CPU nodes */ 426 qemu_fdt_add_subnode(fdt, "/cpus"); 427 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 428 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 429 430 /* We need to generate the cpu nodes in reverse order, so Linux can pick 431 the first node as boot node and be happy */ 432 for (i = smp_cpus - 1; i >= 0; i--) { 433 CPUState *cpu; 434 char *cpu_name; 435 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 436 437 cpu = qemu_get_cpu(i); 438 if (cpu == NULL) { 439 continue; 440 } 441 env = cpu->env_ptr; 442 443 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 444 qemu_fdt_add_subnode(fdt, cpu_name); 445 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 447 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 450 env->dcache_line_size); 451 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 452 env->icache_line_size); 453 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 454 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 455 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 456 if (cpu->cpu_index) { 457 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 458 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 459 "spin-table"); 460 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 461 cpu_release_addr); 462 } else { 463 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 464 } 465 g_free(cpu_name); 466 } 467 468 qemu_fdt_add_subnode(fdt, "/aliases"); 469 /* XXX These should go into their respective devices' code */ 470 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 471 qemu_fdt_add_subnode(fdt, soc); 472 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 473 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 474 sizeof(compatible_sb)); 475 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 476 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 477 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 478 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 479 MPC8544_CCSRBAR_SIZE); 480 /* XXX should contain a reasonable value */ 481 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 482 483 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 484 qemu_fdt_add_subnode(fdt, mpic); 485 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 486 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 487 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 488 0x40000); 489 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 490 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 491 mpic_ph = qemu_fdt_alloc_phandle(fdt); 492 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 493 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 494 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 495 496 /* 497 * We have to generate ser1 first, because Linux takes the first 498 * device it finds in the dt as serial output device. And we generate 499 * devices in reverse order to the dt. 500 */ 501 if (serial_hd(1)) { 502 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 503 soc, mpic, "serial1", 1, false); 504 } 505 506 if (serial_hd(0)) { 507 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 508 soc, mpic, "serial0", 0, true); 509 } 510 511 /* i2c */ 512 dt_i2c_create(fdt, soc, mpic, "i2c"); 513 514 dt_rtc_create(fdt, "i2c", "rtc"); 515 516 517 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 518 MPC8544_UTIL_OFFSET); 519 qemu_fdt_add_subnode(fdt, gutil); 520 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 521 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 522 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 523 g_free(gutil); 524 525 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 526 qemu_fdt_add_subnode(fdt, msi); 527 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 528 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 529 msi_ph = qemu_fdt_alloc_phandle(fdt); 530 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 531 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 532 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 533 0xe0, 0x0, 534 0xe1, 0x0, 535 0xe2, 0x0, 536 0xe3, 0x0, 537 0xe4, 0x0, 538 0xe5, 0x0, 539 0xe6, 0x0, 540 0xe7, 0x0); 541 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 542 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 543 g_free(msi); 544 545 pci = g_strdup_printf("/pci@%llx", 546 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 547 qemu_fdt_add_subnode(fdt, pci); 548 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 549 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 550 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 551 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 552 0x0, 0x7); 553 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 554 pmc->pci_first_slot, pmc->pci_nr_slots, 555 &len); 556 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 557 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 558 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 559 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 560 for (i = 0; i < 14; i++) { 561 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 562 } 563 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 564 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 565 qemu_fdt_setprop_cells(fdt, pci, "reg", 566 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 567 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 568 0, 0x1000); 569 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 570 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 571 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 572 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 573 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 574 g_free(pci); 575 576 if (pmc->has_mpc8xxx_gpio) { 577 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 578 } 579 g_free(soc); 580 581 if (pms->pbus_dev) { 582 platform_bus_create_devtree(pms, fdt, mpic); 583 } 584 g_free(mpic); 585 586 pmc->fixup_devtree(fdt); 587 588 if (toplevel_compat) { 589 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 590 strlen(toplevel_compat) + 1); 591 } 592 593 done: 594 if (!dry_run) { 595 qemu_fdt_dumpdtb(fdt, fdt_size); 596 cpu_physical_memory_write(addr, fdt, fdt_size); 597 } 598 ret = fdt_size; 599 g_free(fdt); 600 601 out: 602 g_free(pci_map); 603 604 return ret; 605 } 606 607 typedef struct DeviceTreeParams { 608 PPCE500MachineState *machine; 609 hwaddr addr; 610 hwaddr initrd_base; 611 hwaddr initrd_size; 612 hwaddr kernel_base; 613 hwaddr kernel_size; 614 Notifier notifier; 615 } DeviceTreeParams; 616 617 static void ppce500_reset_device_tree(void *opaque) 618 { 619 DeviceTreeParams *p = opaque; 620 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 621 p->initrd_size, p->kernel_base, p->kernel_size, 622 false); 623 } 624 625 static void ppce500_init_notify(Notifier *notifier, void *data) 626 { 627 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 628 ppce500_reset_device_tree(p); 629 } 630 631 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 632 hwaddr addr, 633 hwaddr initrd_base, 634 hwaddr initrd_size, 635 hwaddr kernel_base, 636 hwaddr kernel_size) 637 { 638 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 639 p->machine = machine; 640 p->addr = addr; 641 p->initrd_base = initrd_base; 642 p->initrd_size = initrd_size; 643 p->kernel_base = kernel_base; 644 p->kernel_size = kernel_size; 645 646 qemu_register_reset(ppce500_reset_device_tree, p); 647 p->notifier.notify = ppce500_init_notify; 648 qemu_add_machine_init_done_notifier(&p->notifier); 649 650 /* Issue the device tree loader once, so that we get the size of the blob */ 651 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 652 kernel_base, kernel_size, true); 653 } 654 655 /* Create -kernel TLB entries for BookE. */ 656 hwaddr booke206_page_size_to_tlb(uint64_t size) 657 { 658 return 63 - clz64(size / KiB); 659 } 660 661 static int booke206_initial_map_tsize(CPUPPCState *env) 662 { 663 struct boot_info *bi = env->load_info; 664 hwaddr dt_end; 665 int ps; 666 667 /* Our initial TLB entry needs to cover everything from 0 to 668 the device tree top */ 669 dt_end = bi->dt_base + bi->dt_size; 670 ps = booke206_page_size_to_tlb(dt_end) + 1; 671 if (ps & 1) { 672 /* e500v2 can only do even TLB size bits */ 673 ps++; 674 } 675 return ps; 676 } 677 678 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 679 { 680 int tsize; 681 682 tsize = booke206_initial_map_tsize(env); 683 return (1ULL << 10 << tsize); 684 } 685 686 static void mmubooke_create_initial_mapping(CPUPPCState *env) 687 { 688 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 689 hwaddr size; 690 int ps; 691 692 ps = booke206_initial_map_tsize(env); 693 size = (ps << MAS1_TSIZE_SHIFT); 694 tlb->mas1 = MAS1_VALID | size; 695 tlb->mas2 = 0; 696 tlb->mas7_3 = 0; 697 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 698 699 env->tlb_dirty = true; 700 } 701 702 static void ppce500_cpu_reset_sec(void *opaque) 703 { 704 PowerPCCPU *cpu = opaque; 705 CPUState *cs = CPU(cpu); 706 707 cpu_reset(cs); 708 709 cs->exception_index = EXCP_HLT; 710 } 711 712 static void ppce500_cpu_reset(void *opaque) 713 { 714 PowerPCCPU *cpu = opaque; 715 CPUState *cs = CPU(cpu); 716 CPUPPCState *env = &cpu->env; 717 struct boot_info *bi = env->load_info; 718 719 cpu_reset(cs); 720 721 /* Set initial guest state. */ 722 cs->halted = 0; 723 env->gpr[1] = (16 * MiB) - 8; 724 env->gpr[3] = bi->dt_base; 725 env->gpr[4] = 0; 726 env->gpr[5] = 0; 727 env->gpr[6] = EPAPR_MAGIC; 728 env->gpr[7] = mmubooke_initial_mapsize(env); 729 env->gpr[8] = 0; 730 env->gpr[9] = 0; 731 env->nip = bi->entry; 732 mmubooke_create_initial_mapping(env); 733 } 734 735 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 736 IrqLines *irqs) 737 { 738 DeviceState *dev; 739 SysBusDevice *s; 740 int i, j, k; 741 MachineState *machine = MACHINE(pms); 742 unsigned int smp_cpus = machine->smp.cpus; 743 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 744 745 dev = qdev_new(TYPE_OPENPIC); 746 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 747 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 748 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 749 750 s = SYS_BUS_DEVICE(dev); 751 sysbus_realize_and_unref(s, &error_fatal); 752 753 k = 0; 754 for (i = 0; i < smp_cpus; i++) { 755 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 756 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 757 } 758 } 759 760 return dev; 761 } 762 763 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 764 IrqLines *irqs, Error **errp) 765 { 766 DeviceState *dev; 767 CPUState *cs; 768 769 dev = qdev_new(TYPE_KVM_OPENPIC); 770 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 771 772 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 773 object_unparent(OBJECT(dev)); 774 return NULL; 775 } 776 777 CPU_FOREACH(cs) { 778 if (kvm_openpic_connect_vcpu(dev, cs)) { 779 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 780 __func__); 781 abort(); 782 } 783 } 784 785 return dev; 786 } 787 788 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 789 MemoryRegion *ccsr, 790 IrqLines *irqs) 791 { 792 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 793 DeviceState *dev = NULL; 794 SysBusDevice *s; 795 796 if (kvm_enabled()) { 797 Error *err = NULL; 798 799 if (kvm_kernel_irqchip_allowed()) { 800 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 801 } 802 if (kvm_kernel_irqchip_required() && !dev) { 803 error_reportf_err(err, 804 "kernel_irqchip requested but unavailable: "); 805 exit(1); 806 } 807 } 808 809 if (!dev) { 810 dev = ppce500_init_mpic_qemu(pms, irqs); 811 } 812 813 s = SYS_BUS_DEVICE(dev); 814 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 815 s->mmio[0].memory); 816 817 return dev; 818 } 819 820 static void ppce500_power_off(void *opaque, int line, int on) 821 { 822 if (on) { 823 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 824 } 825 } 826 827 void ppce500_init(MachineState *machine) 828 { 829 MemoryRegion *address_space_mem = get_system_memory(); 830 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 831 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 832 PCIBus *pci_bus; 833 CPUPPCState *env = NULL; 834 uint64_t loadaddr; 835 hwaddr kernel_base = -1LL; 836 int kernel_size = 0; 837 hwaddr dt_base = 0; 838 hwaddr initrd_base = 0; 839 int initrd_size = 0; 840 hwaddr cur_base = 0; 841 char *filename; 842 const char *payload_name; 843 bool kernel_as_payload; 844 hwaddr bios_entry = 0; 845 target_long payload_size; 846 struct boot_info *boot_info; 847 int dt_size; 848 int i; 849 unsigned int smp_cpus = machine->smp.cpus; 850 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 851 * 4 respectively */ 852 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 853 IrqLines *irqs; 854 DeviceState *dev, *mpicdev; 855 CPUPPCState *firstenv = NULL; 856 MemoryRegion *ccsr_addr_space; 857 SysBusDevice *s; 858 PPCE500CCSRState *ccsr; 859 I2CBus *i2c; 860 861 irqs = g_new0(IrqLines, smp_cpus); 862 for (i = 0; i < smp_cpus; i++) { 863 PowerPCCPU *cpu; 864 CPUState *cs; 865 qemu_irq *input; 866 867 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 868 env = &cpu->env; 869 cs = CPU(cpu); 870 871 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 872 error_report("MMU model %i not supported by this machine", 873 env->mmu_model); 874 exit(1); 875 } 876 877 /* 878 * Secondary CPU starts in halted state for now. Needs to change 879 * when implementing non-kernel boot. 880 */ 881 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 882 &error_fatal); 883 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 884 885 if (!firstenv) { 886 firstenv = env; 887 } 888 889 input = (qemu_irq *)env->irq_inputs; 890 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 891 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 892 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 893 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 894 895 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 896 897 /* Register reset handler */ 898 if (!i) { 899 /* Primary CPU */ 900 struct boot_info *boot_info; 901 boot_info = g_malloc0(sizeof(struct boot_info)); 902 qemu_register_reset(ppce500_cpu_reset, cpu); 903 env->load_info = boot_info; 904 } else { 905 /* Secondary CPUs */ 906 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 907 } 908 } 909 910 env = firstenv; 911 912 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 913 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 914 exit(EXIT_FAILURE); 915 } 916 917 /* Register Memory */ 918 memory_region_add_subregion(address_space_mem, 0, machine->ram); 919 920 dev = qdev_new("e500-ccsr"); 921 object_property_add_child(qdev_get_machine(), "e500-ccsr", 922 OBJECT(dev)); 923 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 924 ccsr = CCSR(dev); 925 ccsr_addr_space = &ccsr->ccsr_space; 926 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 927 ccsr_addr_space); 928 929 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 930 g_free(irqs); 931 932 /* Serial */ 933 if (serial_hd(0)) { 934 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 935 0, qdev_get_gpio_in(mpicdev, 42), 399193, 936 serial_hd(0), DEVICE_BIG_ENDIAN); 937 } 938 939 if (serial_hd(1)) { 940 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 941 0, qdev_get_gpio_in(mpicdev, 42), 399193, 942 serial_hd(1), DEVICE_BIG_ENDIAN); 943 } 944 /* I2C */ 945 dev = qdev_new("mpc-i2c"); 946 s = SYS_BUS_DEVICE(dev); 947 sysbus_realize_and_unref(s, &error_fatal); 948 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 949 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 950 sysbus_mmio_get_region(s, 0)); 951 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 952 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 953 954 955 /* General Utility device */ 956 dev = qdev_new("mpc8544-guts"); 957 s = SYS_BUS_DEVICE(dev); 958 sysbus_realize_and_unref(s, &error_fatal); 959 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 960 sysbus_mmio_get_region(s, 0)); 961 962 /* PCI */ 963 dev = qdev_new("e500-pcihost"); 964 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 965 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 966 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 967 s = SYS_BUS_DEVICE(dev); 968 sysbus_realize_and_unref(s, &error_fatal); 969 for (i = 0; i < PCI_NUM_PINS; i++) { 970 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 971 } 972 973 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 974 sysbus_mmio_get_region(s, 0)); 975 976 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 977 if (!pci_bus) 978 printf("couldn't create PCI controller!\n"); 979 980 if (pci_bus) { 981 /* Register network interfaces. */ 982 for (i = 0; i < nb_nics; i++) { 983 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 984 } 985 } 986 987 /* Register spinning region */ 988 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 989 990 if (pmc->has_mpc8xxx_gpio) { 991 qemu_irq poweroff_irq; 992 993 dev = qdev_new("mpc8xxx_gpio"); 994 s = SYS_BUS_DEVICE(dev); 995 sysbus_realize_and_unref(s, &error_fatal); 996 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 997 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 998 sysbus_mmio_get_region(s, 0)); 999 1000 /* Power Off GPIO at Pin 0 */ 1001 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1002 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1003 } 1004 1005 /* Platform Bus Device */ 1006 if (pmc->has_platform_bus) { 1007 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1008 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1009 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1010 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1011 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1012 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1013 1014 s = SYS_BUS_DEVICE(pms->pbus_dev); 1015 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1016 int irqn = pmc->platform_bus_first_irq + i; 1017 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1018 } 1019 1020 memory_region_add_subregion(address_space_mem, 1021 pmc->platform_bus_base, 1022 sysbus_mmio_get_region(s, 0)); 1023 } 1024 1025 /* 1026 * Smart firmware defaults ahead! 1027 * 1028 * We follow the following table to select which payload we execute. 1029 * 1030 * -kernel | -bios | payload 1031 * ---------+-------+--------- 1032 * N | Y | u-boot 1033 * N | N | u-boot 1034 * Y | Y | u-boot 1035 * Y | N | kernel 1036 * 1037 * This ensures backwards compatibility with how we used to expose 1038 * -kernel to users but allows them to run through u-boot as well. 1039 */ 1040 kernel_as_payload = false; 1041 if (machine->firmware == NULL) { 1042 if (machine->kernel_filename) { 1043 payload_name = machine->kernel_filename; 1044 kernel_as_payload = true; 1045 } else { 1046 payload_name = "u-boot.e500"; 1047 } 1048 } else { 1049 payload_name = machine->firmware; 1050 } 1051 1052 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1053 if (!filename) { 1054 error_report("could not find firmware/kernel file '%s'", payload_name); 1055 exit(1); 1056 } 1057 1058 payload_size = load_elf(filename, NULL, NULL, NULL, 1059 &bios_entry, &loadaddr, NULL, NULL, 1060 1, PPC_ELF_MACHINE, 0, 0); 1061 if (payload_size < 0) { 1062 /* 1063 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1064 * ePAPR compliant kernel 1065 */ 1066 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1067 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1068 NULL, NULL); 1069 if (payload_size < 0) { 1070 error_report("could not load firmware '%s'", filename); 1071 exit(1); 1072 } 1073 } 1074 1075 g_free(filename); 1076 1077 if (kernel_as_payload) { 1078 kernel_base = loadaddr; 1079 kernel_size = payload_size; 1080 } 1081 1082 cur_base = loadaddr + payload_size; 1083 if (cur_base < 32 * MiB) { 1084 /* u-boot occupies memory up to 32MB, so load blobs above */ 1085 cur_base = 32 * MiB; 1086 } 1087 1088 /* Load bare kernel only if no bios/u-boot has been provided */ 1089 if (machine->kernel_filename && !kernel_as_payload) { 1090 kernel_base = cur_base; 1091 kernel_size = load_image_targphys(machine->kernel_filename, 1092 cur_base, 1093 machine->ram_size - cur_base); 1094 if (kernel_size < 0) { 1095 error_report("could not load kernel '%s'", 1096 machine->kernel_filename); 1097 exit(1); 1098 } 1099 1100 cur_base += kernel_size; 1101 } 1102 1103 /* Load initrd. */ 1104 if (machine->initrd_filename) { 1105 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1106 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1107 machine->ram_size - initrd_base); 1108 1109 if (initrd_size < 0) { 1110 error_report("could not load initial ram disk '%s'", 1111 machine->initrd_filename); 1112 exit(1); 1113 } 1114 1115 cur_base = initrd_base + initrd_size; 1116 } 1117 1118 /* 1119 * Reserve space for dtb behind the kernel image because Linux has a bug 1120 * where it can only handle the dtb if it's within the first 64MB of where 1121 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1122 * ensures enough space between kernel and initrd. 1123 */ 1124 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1125 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1126 error_report("not enough memory for device tree"); 1127 exit(1); 1128 } 1129 1130 dt_size = ppce500_prep_device_tree(pms, dt_base, 1131 initrd_base, initrd_size, 1132 kernel_base, kernel_size); 1133 if (dt_size < 0) { 1134 error_report("couldn't load device tree"); 1135 exit(1); 1136 } 1137 assert(dt_size < DTB_MAX_SIZE); 1138 1139 boot_info = env->load_info; 1140 boot_info->entry = bios_entry; 1141 boot_info->dt_base = dt_base; 1142 boot_info->dt_size = dt_size; 1143 } 1144 1145 static void e500_ccsr_initfn(Object *obj) 1146 { 1147 PPCE500CCSRState *ccsr = CCSR(obj); 1148 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1149 MPC8544_CCSRBAR_SIZE); 1150 } 1151 1152 static const TypeInfo e500_ccsr_info = { 1153 .name = TYPE_CCSR, 1154 .parent = TYPE_SYS_BUS_DEVICE, 1155 .instance_size = sizeof(PPCE500CCSRState), 1156 .instance_init = e500_ccsr_initfn, 1157 }; 1158 1159 static const TypeInfo ppce500_info = { 1160 .name = TYPE_PPCE500_MACHINE, 1161 .parent = TYPE_MACHINE, 1162 .abstract = true, 1163 .instance_size = sizeof(PPCE500MachineState), 1164 .class_size = sizeof(PPCE500MachineClass), 1165 }; 1166 1167 static void e500_register_types(void) 1168 { 1169 type_register_static(&e500_ccsr_info); 1170 type_register_static(&ppce500_info); 1171 } 1172 1173 type_init(e500_register_types) 1174