1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "net.h" 21 #include "hw/hw.h" 22 #include "hw/serial.h" 23 #include "hw/pci.h" 24 #include "hw/boards.h" 25 #include "sysemu.h" 26 #include "kvm.h" 27 #include "kvm_ppc.h" 28 #include "device_tree.h" 29 #include "hw/openpic.h" 30 #include "hw/ppc.h" 31 #include "hw/loader.h" 32 #include "elf.h" 33 #include "hw/sysbus.h" 34 #include "exec-memory.h" 35 #include "host-utils.h" 36 37 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 38 #define UIMAGE_LOAD_BASE 0 39 #define DTC_LOAD_PAD 0x1800000 40 #define DTC_PAD_MASK 0xFFFFF 41 #define INITRD_LOAD_PAD 0x2000000 42 #define INITRD_PAD_MASK 0xFFFFFF 43 44 #define RAM_SIZES_ALIGN (64UL << 20) 45 46 /* TODO: parameterize */ 47 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 48 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 49 #define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000ULL) 50 #define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500ULL) 51 #define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600ULL) 52 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL) 53 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 54 #define MPC8544_PCI_IO 0xE1000000ULL 55 #define MPC8544_PCI_IOLEN 0x10000ULL 56 #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL) 57 #define MPC8544_SPIN_BASE 0xEF000000ULL 58 59 struct boot_info 60 { 61 uint32_t dt_base; 62 uint32_t dt_size; 63 uint32_t entry; 64 }; 65 66 static void pci_map_create(void *fdt, uint32_t *pci_map, uint32_t mpic) 67 { 68 int i; 69 const uint32_t tmp[] = { 70 /* IDSEL 0x11 J17 Slot 1 */ 71 0x8800, 0x0, 0x0, 0x1, mpic, 0x2, 0x1, 72 0x8800, 0x0, 0x0, 0x2, mpic, 0x3, 0x1, 73 0x8800, 0x0, 0x0, 0x3, mpic, 0x4, 0x1, 74 0x8800, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 75 76 /* IDSEL 0x12 J16 Slot 2 */ 77 0x9000, 0x0, 0x0, 0x1, mpic, 0x3, 0x1, 78 0x9000, 0x0, 0x0, 0x2, mpic, 0x4, 0x1, 79 0x9000, 0x0, 0x0, 0x3, mpic, 0x2, 0x1, 80 0x9000, 0x0, 0x0, 0x4, mpic, 0x1, 0x1, 81 }; 82 for (i = 0; i < (7 * 8); i++) { 83 pci_map[i] = cpu_to_be32(tmp[i]); 84 } 85 } 86 87 static void dt_serial_create(void *fdt, unsigned long long offset, 88 const char *soc, const char *mpic, 89 const char *alias, int idx, bool defcon) 90 { 91 char ser[128]; 92 93 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 94 qemu_devtree_add_subnode(fdt, ser); 95 qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); 96 qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); 97 qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); 98 qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); 99 qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); 100 qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); 101 qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 102 qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); 103 104 if (defcon) { 105 qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 106 } 107 } 108 109 static int ppce500_load_device_tree(CPUPPCState *env, 110 PPCE500Params *params, 111 target_phys_addr_t addr, 112 target_phys_addr_t initrd_base, 113 target_phys_addr_t initrd_size) 114 { 115 int ret = -1; 116 uint64_t mem_reg_property[] = { 0, cpu_to_be64(params->ram_size) }; 117 int fdt_size; 118 void *fdt; 119 uint8_t hypercall[16]; 120 uint32_t clock_freq = 400000000; 121 uint32_t tb_freq = 400000000; 122 int i; 123 const char *toplevel_compat = NULL; /* user override */ 124 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 125 char soc[128]; 126 char mpic[128]; 127 uint32_t mpic_ph; 128 char gutil[128]; 129 char pci[128]; 130 uint32_t pci_map[7 * 8]; 131 uint32_t pci_ranges[14] = 132 { 133 0x2000000, 0x0, 0xc0000000, 134 0x0, 0xc0000000, 135 0x0, 0x20000000, 136 137 0x1000000, 0x0, 0x0, 138 0x0, 0xe1000000, 139 0x0, 0x10000, 140 }; 141 QemuOpts *machine_opts; 142 const char *dtb_file = NULL; 143 144 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); 145 if (machine_opts) { 146 dtb_file = qemu_opt_get(machine_opts, "dtb"); 147 toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 148 } 149 150 if (dtb_file) { 151 char *filename; 152 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 153 if (!filename) { 154 goto out; 155 } 156 157 fdt = load_device_tree(filename, &fdt_size); 158 if (!fdt) { 159 goto out; 160 } 161 goto done; 162 } 163 164 fdt = create_device_tree(&fdt_size); 165 if (fdt == NULL) { 166 goto out; 167 } 168 169 /* Manipulate device tree in memory. */ 170 qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); 171 qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); 172 173 qemu_devtree_add_subnode(fdt, "/memory"); 174 qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); 175 qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, 176 sizeof(mem_reg_property)); 177 178 qemu_devtree_add_subnode(fdt, "/chosen"); 179 if (initrd_size) { 180 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", 181 initrd_base); 182 if (ret < 0) { 183 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 184 } 185 186 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", 187 (initrd_base + initrd_size)); 188 if (ret < 0) { 189 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 190 } 191 } 192 193 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", 194 params->kernel_cmdline); 195 if (ret < 0) 196 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 197 198 if (kvm_enabled()) { 199 /* Read out host's frequencies */ 200 clock_freq = kvmppc_get_clockfreq(); 201 tb_freq = kvmppc_get_tbfreq(); 202 203 /* indicate KVM hypercall interface */ 204 qemu_devtree_add_subnode(fdt, "/hypervisor"); 205 qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", 206 "linux,kvm"); 207 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 208 qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", 209 hypercall, sizeof(hypercall)); 210 } 211 212 /* Create CPU nodes */ 213 qemu_devtree_add_subnode(fdt, "/cpus"); 214 qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); 215 qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); 216 217 /* We need to generate the cpu nodes in reverse order, so Linux can pick 218 the first node as boot node and be happy */ 219 for (i = smp_cpus - 1; i >= 0; i--) { 220 char cpu_name[128]; 221 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 222 223 for (env = first_cpu; env != NULL; env = env->next_cpu) { 224 if (env->cpu_index == i) { 225 break; 226 } 227 } 228 229 if (!env) { 230 continue; 231 } 232 233 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index); 234 qemu_devtree_add_subnode(fdt, cpu_name); 235 qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 236 qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 237 qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); 238 qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index); 239 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", 240 env->dcache_line_size); 241 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", 242 env->icache_line_size); 243 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 244 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 245 qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 246 if (env->cpu_index) { 247 qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); 248 qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); 249 qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", 250 cpu_release_addr); 251 } else { 252 qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); 253 } 254 } 255 256 qemu_devtree_add_subnode(fdt, "/aliases"); 257 /* XXX These should go into their respective devices' code */ 258 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 259 qemu_devtree_add_subnode(fdt, soc); 260 qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); 261 qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, 262 sizeof(compatible_sb)); 263 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); 264 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); 265 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, 266 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 267 MPC8544_CCSRBAR_SIZE); 268 /* XXX should contain a reasonable value */ 269 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); 270 271 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, 272 MPC8544_MPIC_REGS_BASE - MPC8544_CCSRBAR_BASE); 273 qemu_devtree_add_subnode(fdt, mpic); 274 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); 275 qemu_devtree_setprop_string(fdt, mpic, "compatible", "chrp,open-pic"); 276 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_BASE - 277 MPC8544_CCSRBAR_BASE, 0x40000); 278 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); 279 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 280 mpic_ph = qemu_devtree_alloc_phandle(fdt); 281 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); 282 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 283 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 284 285 /* 286 * We have to generate ser1 first, because Linux takes the first 287 * device it finds in the dt as serial output device. And we generate 288 * devices in reverse order to the dt. 289 */ 290 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE, 291 soc, mpic, "serial1", 1, false); 292 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE, 293 soc, mpic, "serial0", 0, true); 294 295 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 296 MPC8544_UTIL_BASE - MPC8544_CCSRBAR_BASE); 297 qemu_devtree_add_subnode(fdt, gutil); 298 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 299 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_BASE - 300 MPC8544_CCSRBAR_BASE, 0x1000); 301 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 302 303 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 304 qemu_devtree_add_subnode(fdt, pci); 305 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); 306 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 307 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); 308 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 309 0x0, 0x7); 310 pci_map_create(fdt, pci_map, qemu_devtree_get_phandle(fdt, mpic)); 311 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, sizeof(pci_map)); 312 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 313 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); 314 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); 315 for (i = 0; i < 14; i++) { 316 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 317 } 318 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 319 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 320 MPC8544_PCI_REGS_BASE, 0, 0x1000); 321 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); 322 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); 323 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); 324 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); 325 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); 326 327 params->fixup_devtree(params, fdt); 328 329 if (toplevel_compat) { 330 qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, 331 strlen(toplevel_compat) + 1); 332 } 333 334 done: 335 qemu_devtree_dumpdtb(fdt, fdt_size); 336 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 337 if (ret < 0) { 338 goto out; 339 } 340 g_free(fdt); 341 ret = fdt_size; 342 343 out: 344 345 return ret; 346 } 347 348 /* Create -kernel TLB entries for BookE. */ 349 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) 350 { 351 return 63 - clz64(size >> 10); 352 } 353 354 static void mmubooke_create_initial_mapping(CPUPPCState *env) 355 { 356 struct boot_info *bi = env->load_info; 357 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 358 target_phys_addr_t size, dt_end; 359 int ps; 360 361 /* Our initial TLB entry needs to cover everything from 0 to 362 the device tree top */ 363 dt_end = bi->dt_base + bi->dt_size; 364 ps = booke206_page_size_to_tlb(dt_end) + 1; 365 if (ps & 1) { 366 /* e500v2 can only do even TLB size bits */ 367 ps++; 368 } 369 size = (ps << MAS1_TSIZE_SHIFT); 370 tlb->mas1 = MAS1_VALID | size; 371 tlb->mas2 = 0; 372 tlb->mas7_3 = 0; 373 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 374 375 env->tlb_dirty = true; 376 } 377 378 static void ppce500_cpu_reset_sec(void *opaque) 379 { 380 PowerPCCPU *cpu = opaque; 381 CPUPPCState *env = &cpu->env; 382 383 cpu_reset(CPU(cpu)); 384 385 /* Secondary CPU starts in halted state for now. Needs to change when 386 implementing non-kernel boot. */ 387 env->halted = 1; 388 env->exception_index = EXCP_HLT; 389 } 390 391 static void ppce500_cpu_reset(void *opaque) 392 { 393 PowerPCCPU *cpu = opaque; 394 CPUPPCState *env = &cpu->env; 395 struct boot_info *bi = env->load_info; 396 397 cpu_reset(CPU(cpu)); 398 399 /* Set initial guest state. */ 400 env->halted = 0; 401 env->gpr[1] = (16<<20) - 8; 402 env->gpr[3] = bi->dt_base; 403 env->nip = bi->entry; 404 mmubooke_create_initial_mapping(env); 405 } 406 407 void ppce500_init(PPCE500Params *params) 408 { 409 MemoryRegion *address_space_mem = get_system_memory(); 410 MemoryRegion *ram = g_new(MemoryRegion, 1); 411 PCIBus *pci_bus; 412 CPUPPCState *env = NULL; 413 uint64_t elf_entry; 414 uint64_t elf_lowaddr; 415 target_phys_addr_t entry=0; 416 target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE; 417 target_long kernel_size=0; 418 target_ulong dt_base = 0; 419 target_ulong initrd_base = 0; 420 target_long initrd_size=0; 421 int i=0; 422 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; 423 qemu_irq **irqs, *mpic; 424 DeviceState *dev; 425 CPUPPCState *firstenv = NULL; 426 427 /* Setup CPUs */ 428 if (params->cpu_model == NULL) { 429 params->cpu_model = "e500v2_v30"; 430 } 431 432 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 433 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 434 for (i = 0; i < smp_cpus; i++) { 435 PowerPCCPU *cpu; 436 qemu_irq *input; 437 438 cpu = cpu_ppc_init(params->cpu_model); 439 if (cpu == NULL) { 440 fprintf(stderr, "Unable to initialize CPU!\n"); 441 exit(1); 442 } 443 env = &cpu->env; 444 445 if (!firstenv) { 446 firstenv = env; 447 } 448 449 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 450 input = (qemu_irq *)env->irq_inputs; 451 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 452 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 453 env->spr[SPR_BOOKE_PIR] = env->cpu_index = i; 454 env->mpic_cpu_base = MPC8544_MPIC_REGS_BASE + 0x20000; 455 456 ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500); 457 458 /* Register reset handler */ 459 if (!i) { 460 /* Primary CPU */ 461 struct boot_info *boot_info; 462 boot_info = g_malloc0(sizeof(struct boot_info)); 463 qemu_register_reset(ppce500_cpu_reset, cpu); 464 env->load_info = boot_info; 465 } else { 466 /* Secondary CPUs */ 467 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 468 } 469 } 470 471 env = firstenv; 472 473 /* Fixup Memory size on a alignment boundary */ 474 ram_size &= ~(RAM_SIZES_ALIGN - 1); 475 476 /* Register Memory */ 477 memory_region_init_ram(ram, "mpc8544ds.ram", ram_size); 478 vmstate_register_ram_global(ram); 479 memory_region_add_subregion(address_space_mem, 0, ram); 480 481 /* MPIC */ 482 mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, 483 smp_cpus, irqs, NULL); 484 485 if (!mpic) { 486 cpu_abort(env, "MPIC failed to initialize\n"); 487 } 488 489 /* Serial */ 490 if (serial_hds[0]) { 491 serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE, 492 0, mpic[12+26], 399193, 493 serial_hds[0], DEVICE_BIG_ENDIAN); 494 } 495 496 if (serial_hds[1]) { 497 serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE, 498 0, mpic[12+26], 399193, 499 serial_hds[0], DEVICE_BIG_ENDIAN); 500 } 501 502 /* General Utility device */ 503 sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL); 504 505 /* PCI */ 506 dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE, 507 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]], 508 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]], 509 NULL); 510 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 511 if (!pci_bus) 512 printf("couldn't create PCI controller!\n"); 513 514 isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); 515 516 if (pci_bus) { 517 /* Register network interfaces. */ 518 for (i = 0; i < nb_nics; i++) { 519 pci_nic_init_nofail(&nd_table[i], "virtio", NULL); 520 } 521 } 522 523 /* Register spinning region */ 524 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 525 526 /* Load kernel. */ 527 if (params->kernel_filename) { 528 kernel_size = load_uimage(params->kernel_filename, &entry, 529 &loadaddr, NULL); 530 if (kernel_size < 0) { 531 kernel_size = load_elf(params->kernel_filename, NULL, NULL, 532 &elf_entry, &elf_lowaddr, NULL, 1, 533 ELF_MACHINE, 0); 534 entry = elf_entry; 535 loadaddr = elf_lowaddr; 536 } 537 /* XXX try again as binary */ 538 if (kernel_size < 0) { 539 fprintf(stderr, "qemu: could not load kernel '%s'\n", 540 params->kernel_filename); 541 exit(1); 542 } 543 } 544 545 /* Load initrd. */ 546 if (params->initrd_filename) { 547 initrd_base = (loadaddr + kernel_size + INITRD_LOAD_PAD) & 548 ~INITRD_PAD_MASK; 549 initrd_size = load_image_targphys(params->initrd_filename, initrd_base, 550 ram_size - initrd_base); 551 552 if (initrd_size < 0) { 553 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 554 params->initrd_filename); 555 exit(1); 556 } 557 } 558 559 /* If we're loading a kernel directly, we must load the device tree too. */ 560 if (params->kernel_filename) { 561 struct boot_info *boot_info; 562 int dt_size; 563 564 dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 565 dt_size = ppce500_load_device_tree(env, params, dt_base, initrd_base, 566 initrd_size); 567 if (dt_size < 0) { 568 fprintf(stderr, "couldn't load device tree\n"); 569 exit(1); 570 } 571 572 boot_info = env->load_info; 573 boot_info->entry = entry; 574 boot_info->dt_base = dt_base; 575 boot_info->dt_size = dt_size; 576 } 577 578 if (kvm_enabled()) { 579 kvmppc_init(); 580 } 581 } 582