1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qapi/error.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/openpic_kvm.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/loader.h" 35 #include "elf.h" 36 #include "hw/sysbus.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/host-utils.h" 39 #include "qemu/option.h" 40 #include "hw/pci-host/ppce500.h" 41 #include "qemu/error-report.h" 42 #include "hw/platform-bus.h" 43 #include "hw/net/fsl_etsec/etsec.h" 44 45 #define EPAPR_MAGIC (0x45504150) 46 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 47 #define DTC_LOAD_PAD 0x1800000 48 #define DTC_PAD_MASK 0xFFFFF 49 #define DTB_MAX_SIZE (8 * 1024 * 1024) 50 #define INITRD_LOAD_PAD 0x2000000 51 #define INITRD_PAD_MASK 0xFFFFFF 52 53 #define RAM_SIZES_ALIGN (64UL << 20) 54 55 /* TODO: parameterize */ 56 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 57 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 58 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 59 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 60 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 61 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 62 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 65 #define MPC8XXX_GPIO_IRQ 47 66 67 struct boot_info 68 { 69 uint32_t dt_base; 70 uint32_t dt_size; 71 uint32_t entry; 72 }; 73 74 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 75 int nr_slots, int *len) 76 { 77 int i = 0; 78 int slot; 79 int pci_irq; 80 int host_irq; 81 int last_slot = first_slot + nr_slots; 82 uint32_t *pci_map; 83 84 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 85 pci_map = g_malloc(*len); 86 87 for (slot = first_slot; slot < last_slot; slot++) { 88 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 89 pci_map[i++] = cpu_to_be32(slot << 11); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(0x0); 92 pci_map[i++] = cpu_to_be32(pci_irq + 1); 93 pci_map[i++] = cpu_to_be32(mpic); 94 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 95 pci_map[i++] = cpu_to_be32(host_irq + 1); 96 pci_map[i++] = cpu_to_be32(0x1); 97 } 98 } 99 100 assert((i * sizeof(uint32_t)) == *len); 101 102 return pci_map; 103 } 104 105 static void dt_serial_create(void *fdt, unsigned long long offset, 106 const char *soc, const char *mpic, 107 const char *alias, int idx, bool defcon) 108 { 109 char ser[128]; 110 111 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 112 qemu_fdt_add_subnode(fdt, ser); 113 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 114 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 115 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 116 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 117 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 118 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 119 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 120 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 121 122 if (defcon) { 123 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 124 } 125 } 126 127 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 128 { 129 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 130 int irq0 = MPC8XXX_GPIO_IRQ; 131 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 132 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 133 int gpio_ph; 134 135 qemu_fdt_add_subnode(fdt, node); 136 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 137 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 138 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 139 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 140 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 141 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 142 gpio_ph = qemu_fdt_alloc_phandle(fdt); 143 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 144 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 145 146 /* Power Off Pin */ 147 qemu_fdt_add_subnode(fdt, poweroff); 148 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 149 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 150 151 g_free(node); 152 g_free(poweroff); 153 } 154 155 typedef struct PlatformDevtreeData { 156 void *fdt; 157 const char *mpic; 158 int irq_start; 159 const char *node; 160 PlatformBusDevice *pbus; 161 } PlatformDevtreeData; 162 163 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 164 { 165 eTSEC *etsec = ETSEC_COMMON(sbdev); 166 PlatformBusDevice *pbus = data->pbus; 167 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 168 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 169 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 170 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 171 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 172 gchar *group = g_strdup_printf("%s/queue-group", node); 173 void *fdt = data->fdt; 174 175 assert((int64_t)mmio0 >= 0); 176 assert(irq0 >= 0); 177 assert(irq1 >= 0); 178 assert(irq2 >= 0); 179 180 qemu_fdt_add_subnode(fdt, node); 181 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 182 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 183 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 184 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 185 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 186 187 qemu_fdt_add_subnode(fdt, group); 188 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 189 qemu_fdt_setprop_cells(fdt, group, "interrupts", 190 data->irq_start + irq0, 0x2, 191 data->irq_start + irq1, 0x2, 192 data->irq_start + irq2, 0x2); 193 194 g_free(node); 195 g_free(group); 196 197 return 0; 198 } 199 200 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 201 { 202 PlatformDevtreeData *data = opaque; 203 bool matched = false; 204 205 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 206 create_devtree_etsec(sbdev, data); 207 matched = true; 208 } 209 210 if (!matched) { 211 error_report("Device %s is not supported by this machine yet.", 212 qdev_fw_name(DEVICE(sbdev))); 213 exit(1); 214 } 215 } 216 217 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, 218 const char *mpic) 219 { 220 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); 221 const char platcomp[] = "qemu,platform\0simple-bus"; 222 uint64_t addr = params->platform_bus_base; 223 uint64_t size = params->platform_bus_size; 224 int irq_start = params->platform_bus_first_irq; 225 PlatformBusDevice *pbus; 226 DeviceState *dev; 227 228 /* Create a /platform node that we can put all devices into */ 229 230 qemu_fdt_add_subnode(fdt, node); 231 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 232 233 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 234 address and size */ 235 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 236 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 237 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 238 239 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 240 241 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); 242 pbus = PLATFORM_BUS_DEVICE(dev); 243 244 /* We can only create dt nodes for dynamic devices when they're ready */ 245 if (pbus->done_gathering) { 246 PlatformDevtreeData data = { 247 .fdt = fdt, 248 .mpic = mpic, 249 .irq_start = irq_start, 250 .node = node, 251 .pbus = pbus, 252 }; 253 254 /* Loop through all dynamic sysbus devices and create nodes for them */ 255 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 256 } 257 258 g_free(node); 259 } 260 261 static int ppce500_load_device_tree(MachineState *machine, 262 PPCE500Params *params, 263 hwaddr addr, 264 hwaddr initrd_base, 265 hwaddr initrd_size, 266 hwaddr kernel_base, 267 hwaddr kernel_size, 268 bool dry_run) 269 { 270 CPUPPCState *env = first_cpu->env_ptr; 271 int ret = -1; 272 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 273 int fdt_size; 274 void *fdt; 275 uint8_t hypercall[16]; 276 uint32_t clock_freq = 400000000; 277 uint32_t tb_freq = 400000000; 278 int i; 279 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 280 char soc[128]; 281 char mpic[128]; 282 uint32_t mpic_ph; 283 uint32_t msi_ph; 284 char gutil[128]; 285 char pci[128]; 286 char msi[128]; 287 uint32_t *pci_map = NULL; 288 int len; 289 uint32_t pci_ranges[14] = 290 { 291 0x2000000, 0x0, params->pci_mmio_bus_base, 292 params->pci_mmio_base >> 32, params->pci_mmio_base, 293 0x0, 0x20000000, 294 295 0x1000000, 0x0, 0x0, 296 params->pci_pio_base >> 32, params->pci_pio_base, 297 0x0, 0x10000, 298 }; 299 QemuOpts *machine_opts = qemu_get_machine_opts(); 300 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 301 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 302 303 if (dtb_file) { 304 char *filename; 305 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 306 if (!filename) { 307 goto out; 308 } 309 310 fdt = load_device_tree(filename, &fdt_size); 311 g_free(filename); 312 if (!fdt) { 313 goto out; 314 } 315 goto done; 316 } 317 318 fdt = create_device_tree(&fdt_size); 319 if (fdt == NULL) { 320 goto out; 321 } 322 323 /* Manipulate device tree in memory. */ 324 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 325 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 326 327 qemu_fdt_add_subnode(fdt, "/memory"); 328 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 329 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 330 sizeof(mem_reg_property)); 331 332 qemu_fdt_add_subnode(fdt, "/chosen"); 333 if (initrd_size) { 334 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 335 initrd_base); 336 if (ret < 0) { 337 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 338 } 339 340 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 341 (initrd_base + initrd_size)); 342 if (ret < 0) { 343 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 344 } 345 346 } 347 348 if (kernel_base != -1ULL) { 349 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 350 kernel_base >> 32, kernel_base, 351 kernel_size >> 32, kernel_size); 352 } 353 354 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 355 machine->kernel_cmdline); 356 if (ret < 0) 357 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 358 359 if (kvm_enabled()) { 360 /* Read out host's frequencies */ 361 clock_freq = kvmppc_get_clockfreq(); 362 tb_freq = kvmppc_get_tbfreq(); 363 364 /* indicate KVM hypercall interface */ 365 qemu_fdt_add_subnode(fdt, "/hypervisor"); 366 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 367 "linux,kvm"); 368 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 369 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 370 hypercall, sizeof(hypercall)); 371 /* if KVM supports the idle hcall, set property indicating this */ 372 if (kvmppc_get_hasidle(env)) { 373 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 374 } 375 } 376 377 /* Create CPU nodes */ 378 qemu_fdt_add_subnode(fdt, "/cpus"); 379 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 380 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 381 382 /* We need to generate the cpu nodes in reverse order, so Linux can pick 383 the first node as boot node and be happy */ 384 for (i = smp_cpus - 1; i >= 0; i--) { 385 CPUState *cpu; 386 char cpu_name[128]; 387 uint64_t cpu_release_addr = params->spin_base + (i * 0x20); 388 389 cpu = qemu_get_cpu(i); 390 if (cpu == NULL) { 391 continue; 392 } 393 env = cpu->env_ptr; 394 395 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", i); 396 qemu_fdt_add_subnode(fdt, cpu_name); 397 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 398 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 399 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 400 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 401 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 402 env->dcache_line_size); 403 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 404 env->icache_line_size); 405 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 406 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 407 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 408 if (cpu->cpu_index) { 409 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 410 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 411 "spin-table"); 412 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 413 cpu_release_addr); 414 } else { 415 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 416 } 417 } 418 419 qemu_fdt_add_subnode(fdt, "/aliases"); 420 /* XXX These should go into their respective devices' code */ 421 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); 422 qemu_fdt_add_subnode(fdt, soc); 423 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 424 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 425 sizeof(compatible_sb)); 426 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 427 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 428 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 429 params->ccsrbar_base >> 32, params->ccsrbar_base, 430 MPC8544_CCSRBAR_SIZE); 431 /* XXX should contain a reasonable value */ 432 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 433 434 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 435 qemu_fdt_add_subnode(fdt, mpic); 436 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 437 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 438 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 439 0x40000); 440 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 441 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 442 mpic_ph = qemu_fdt_alloc_phandle(fdt); 443 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 444 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 445 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 446 447 /* 448 * We have to generate ser1 first, because Linux takes the first 449 * device it finds in the dt as serial output device. And we generate 450 * devices in reverse order to the dt. 451 */ 452 if (serial_hds[1]) { 453 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 454 soc, mpic, "serial1", 1, false); 455 } 456 457 if (serial_hds[0]) { 458 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 459 soc, mpic, "serial0", 0, true); 460 } 461 462 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 463 MPC8544_UTIL_OFFSET); 464 qemu_fdt_add_subnode(fdt, gutil); 465 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 466 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 467 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 468 469 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 470 qemu_fdt_add_subnode(fdt, msi); 471 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 472 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 473 msi_ph = qemu_fdt_alloc_phandle(fdt); 474 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 475 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 476 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 477 0xe0, 0x0, 478 0xe1, 0x0, 479 0xe2, 0x0, 480 0xe3, 0x0, 481 0xe4, 0x0, 482 0xe5, 0x0, 483 0xe6, 0x0, 484 0xe7, 0x0); 485 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 486 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 487 488 snprintf(pci, sizeof(pci), "/pci@%llx", 489 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 490 qemu_fdt_add_subnode(fdt, pci); 491 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 492 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 493 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 494 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 495 0x0, 0x7); 496 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 497 params->pci_first_slot, params->pci_nr_slots, 498 &len); 499 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 500 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 501 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 502 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 503 for (i = 0; i < 14; i++) { 504 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 505 } 506 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 507 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 508 qemu_fdt_setprop_cells(fdt, pci, "reg", 509 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 510 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 511 0, 0x1000); 512 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 513 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 514 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 515 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 516 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 517 518 if (params->has_mpc8xxx_gpio) { 519 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 520 } 521 522 if (params->has_platform_bus) { 523 platform_bus_create_devtree(params, fdt, mpic); 524 } 525 526 params->fixup_devtree(params, fdt); 527 528 if (toplevel_compat) { 529 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 530 strlen(toplevel_compat) + 1); 531 } 532 533 done: 534 if (!dry_run) { 535 qemu_fdt_dumpdtb(fdt, fdt_size); 536 cpu_physical_memory_write(addr, fdt, fdt_size); 537 } 538 ret = fdt_size; 539 540 out: 541 g_free(pci_map); 542 543 return ret; 544 } 545 546 typedef struct DeviceTreeParams { 547 MachineState *machine; 548 PPCE500Params params; 549 hwaddr addr; 550 hwaddr initrd_base; 551 hwaddr initrd_size; 552 hwaddr kernel_base; 553 hwaddr kernel_size; 554 Notifier notifier; 555 } DeviceTreeParams; 556 557 static void ppce500_reset_device_tree(void *opaque) 558 { 559 DeviceTreeParams *p = opaque; 560 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base, 561 p->initrd_size, p->kernel_base, p->kernel_size, 562 false); 563 } 564 565 static void ppce500_init_notify(Notifier *notifier, void *data) 566 { 567 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 568 ppce500_reset_device_tree(p); 569 } 570 571 static int ppce500_prep_device_tree(MachineState *machine, 572 PPCE500Params *params, 573 hwaddr addr, 574 hwaddr initrd_base, 575 hwaddr initrd_size, 576 hwaddr kernel_base, 577 hwaddr kernel_size) 578 { 579 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 580 p->machine = machine; 581 p->params = *params; 582 p->addr = addr; 583 p->initrd_base = initrd_base; 584 p->initrd_size = initrd_size; 585 p->kernel_base = kernel_base; 586 p->kernel_size = kernel_size; 587 588 qemu_register_reset(ppce500_reset_device_tree, p); 589 p->notifier.notify = ppce500_init_notify; 590 qemu_add_machine_init_done_notifier(&p->notifier); 591 592 /* Issue the device tree loader once, so that we get the size of the blob */ 593 return ppce500_load_device_tree(machine, params, addr, initrd_base, 594 initrd_size, kernel_base, kernel_size, 595 true); 596 } 597 598 /* Create -kernel TLB entries for BookE. */ 599 hwaddr booke206_page_size_to_tlb(uint64_t size) 600 { 601 return 63 - clz64(size >> 10); 602 } 603 604 static int booke206_initial_map_tsize(CPUPPCState *env) 605 { 606 struct boot_info *bi = env->load_info; 607 hwaddr dt_end; 608 int ps; 609 610 /* Our initial TLB entry needs to cover everything from 0 to 611 the device tree top */ 612 dt_end = bi->dt_base + bi->dt_size; 613 ps = booke206_page_size_to_tlb(dt_end) + 1; 614 if (ps & 1) { 615 /* e500v2 can only do even TLB size bits */ 616 ps++; 617 } 618 return ps; 619 } 620 621 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 622 { 623 int tsize; 624 625 tsize = booke206_initial_map_tsize(env); 626 return (1ULL << 10 << tsize); 627 } 628 629 static void mmubooke_create_initial_mapping(CPUPPCState *env) 630 { 631 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 632 hwaddr size; 633 int ps; 634 635 ps = booke206_initial_map_tsize(env); 636 size = (ps << MAS1_TSIZE_SHIFT); 637 tlb->mas1 = MAS1_VALID | size; 638 tlb->mas2 = 0; 639 tlb->mas7_3 = 0; 640 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 641 642 env->tlb_dirty = true; 643 } 644 645 static void ppce500_cpu_reset_sec(void *opaque) 646 { 647 PowerPCCPU *cpu = opaque; 648 CPUState *cs = CPU(cpu); 649 650 cpu_reset(cs); 651 652 /* Secondary CPU starts in halted state for now. Needs to change when 653 implementing non-kernel boot. */ 654 cs->halted = 1; 655 cs->exception_index = EXCP_HLT; 656 } 657 658 static void ppce500_cpu_reset(void *opaque) 659 { 660 PowerPCCPU *cpu = opaque; 661 CPUState *cs = CPU(cpu); 662 CPUPPCState *env = &cpu->env; 663 struct boot_info *bi = env->load_info; 664 665 cpu_reset(cs); 666 667 /* Set initial guest state. */ 668 cs->halted = 0; 669 env->gpr[1] = (16<<20) - 8; 670 env->gpr[3] = bi->dt_base; 671 env->gpr[4] = 0; 672 env->gpr[5] = 0; 673 env->gpr[6] = EPAPR_MAGIC; 674 env->gpr[7] = mmubooke_initial_mapsize(env); 675 env->gpr[8] = 0; 676 env->gpr[9] = 0; 677 env->nip = bi->entry; 678 mmubooke_create_initial_mapping(env); 679 } 680 681 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 682 qemu_irq **irqs) 683 { 684 DeviceState *dev; 685 SysBusDevice *s; 686 int i, j, k; 687 688 dev = qdev_create(NULL, TYPE_OPENPIC); 689 object_property_add_child(qdev_get_machine(), "pic", OBJECT(dev), 690 &error_fatal); 691 qdev_prop_set_uint32(dev, "model", params->mpic_version); 692 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 693 694 qdev_init_nofail(dev); 695 s = SYS_BUS_DEVICE(dev); 696 697 k = 0; 698 for (i = 0; i < smp_cpus; i++) { 699 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 700 sysbus_connect_irq(s, k++, irqs[i][j]); 701 } 702 } 703 704 return dev; 705 } 706 707 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 708 qemu_irq **irqs, Error **errp) 709 { 710 Error *err = NULL; 711 DeviceState *dev; 712 CPUState *cs; 713 714 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 715 qdev_prop_set_uint32(dev, "model", params->mpic_version); 716 717 object_property_set_bool(OBJECT(dev), true, "realized", &err); 718 if (err) { 719 error_propagate(errp, err); 720 object_unparent(OBJECT(dev)); 721 return NULL; 722 } 723 724 CPU_FOREACH(cs) { 725 if (kvm_openpic_connect_vcpu(dev, cs)) { 726 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 727 __func__); 728 abort(); 729 } 730 } 731 732 return dev; 733 } 734 735 static DeviceState *ppce500_init_mpic(MachineState *machine, 736 PPCE500Params *params, 737 MemoryRegion *ccsr, 738 qemu_irq **irqs) 739 { 740 DeviceState *dev = NULL; 741 SysBusDevice *s; 742 743 if (kvm_enabled()) { 744 Error *err = NULL; 745 746 if (machine_kernel_irqchip_allowed(machine)) { 747 dev = ppce500_init_mpic_kvm(params, irqs, &err); 748 } 749 if (machine_kernel_irqchip_required(machine) && !dev) { 750 error_reportf_err(err, 751 "kernel_irqchip requested but unavailable: "); 752 exit(1); 753 } 754 } 755 756 if (!dev) { 757 dev = ppce500_init_mpic_qemu(params, irqs); 758 } 759 760 s = SYS_BUS_DEVICE(dev); 761 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 762 s->mmio[0].memory); 763 764 return dev; 765 } 766 767 static void ppce500_power_off(void *opaque, int line, int on) 768 { 769 if (on) { 770 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 771 } 772 } 773 774 void ppce500_init(MachineState *machine, PPCE500Params *params) 775 { 776 MemoryRegion *address_space_mem = get_system_memory(); 777 MemoryRegion *ram = g_new(MemoryRegion, 1); 778 PCIBus *pci_bus; 779 CPUPPCState *env = NULL; 780 uint64_t loadaddr; 781 hwaddr kernel_base = -1LL; 782 int kernel_size = 0; 783 hwaddr dt_base = 0; 784 hwaddr initrd_base = 0; 785 int initrd_size = 0; 786 hwaddr cur_base = 0; 787 char *filename; 788 hwaddr bios_entry = 0; 789 target_long bios_size; 790 struct boot_info *boot_info; 791 int dt_size; 792 int i; 793 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 794 * 4 respectively */ 795 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 796 qemu_irq **irqs; 797 DeviceState *dev, *mpicdev; 798 CPUPPCState *firstenv = NULL; 799 MemoryRegion *ccsr_addr_space; 800 SysBusDevice *s; 801 PPCE500CCSRState *ccsr; 802 803 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 804 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 805 for (i = 0; i < smp_cpus; i++) { 806 PowerPCCPU *cpu; 807 CPUState *cs; 808 qemu_irq *input; 809 810 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 811 env = &cpu->env; 812 cs = CPU(cpu); 813 814 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 815 error_report("MMU model %i not supported by this machine", 816 env->mmu_model); 817 exit(1); 818 } 819 820 if (!firstenv) { 821 firstenv = env; 822 } 823 824 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 825 input = (qemu_irq *)env->irq_inputs; 826 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 827 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 828 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 829 env->mpic_iack = params->ccsrbar_base + 830 MPC8544_MPIC_REGS_OFFSET + 0xa0; 831 832 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 833 834 /* Register reset handler */ 835 if (!i) { 836 /* Primary CPU */ 837 struct boot_info *boot_info; 838 boot_info = g_malloc0(sizeof(struct boot_info)); 839 qemu_register_reset(ppce500_cpu_reset, cpu); 840 env->load_info = boot_info; 841 } else { 842 /* Secondary CPUs */ 843 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 844 } 845 } 846 847 env = firstenv; 848 849 /* Fixup Memory size on a alignment boundary */ 850 ram_size &= ~(RAM_SIZES_ALIGN - 1); 851 machine->ram_size = ram_size; 852 853 /* Register Memory */ 854 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 855 memory_region_add_subregion(address_space_mem, 0, ram); 856 857 dev = qdev_create(NULL, "e500-ccsr"); 858 object_property_add_child(qdev_get_machine(), "e500-ccsr", 859 OBJECT(dev), NULL); 860 qdev_init_nofail(dev); 861 ccsr = CCSR(dev); 862 ccsr_addr_space = &ccsr->ccsr_space; 863 memory_region_add_subregion(address_space_mem, params->ccsrbar_base, 864 ccsr_addr_space); 865 866 mpicdev = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); 867 868 /* Serial */ 869 if (serial_hds[0]) { 870 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 871 0, qdev_get_gpio_in(mpicdev, 42), 399193, 872 serial_hds[0], DEVICE_BIG_ENDIAN); 873 } 874 875 if (serial_hds[1]) { 876 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 877 0, qdev_get_gpio_in(mpicdev, 42), 399193, 878 serial_hds[1], DEVICE_BIG_ENDIAN); 879 } 880 881 /* General Utility device */ 882 dev = qdev_create(NULL, "mpc8544-guts"); 883 qdev_init_nofail(dev); 884 s = SYS_BUS_DEVICE(dev); 885 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 886 sysbus_mmio_get_region(s, 0)); 887 888 /* PCI */ 889 dev = qdev_create(NULL, "e500-pcihost"); 890 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 891 &error_abort); 892 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 893 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 894 qdev_init_nofail(dev); 895 s = SYS_BUS_DEVICE(dev); 896 for (i = 0; i < PCI_NUM_PINS; i++) { 897 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 898 } 899 900 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 901 sysbus_mmio_get_region(s, 0)); 902 903 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 904 if (!pci_bus) 905 printf("couldn't create PCI controller!\n"); 906 907 if (pci_bus) { 908 /* Register network interfaces. */ 909 for (i = 0; i < nb_nics; i++) { 910 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 911 } 912 } 913 914 /* Register spinning region */ 915 sysbus_create_simple("e500-spin", params->spin_base, NULL); 916 917 if (cur_base < (32 * 1024 * 1024)) { 918 /* u-boot occupies memory up to 32MB, so load blobs above */ 919 cur_base = (32 * 1024 * 1024); 920 } 921 922 if (params->has_mpc8xxx_gpio) { 923 qemu_irq poweroff_irq; 924 925 dev = qdev_create(NULL, "mpc8xxx_gpio"); 926 s = SYS_BUS_DEVICE(dev); 927 qdev_init_nofail(dev); 928 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 929 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 930 sysbus_mmio_get_region(s, 0)); 931 932 /* Power Off GPIO at Pin 0 */ 933 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 934 qdev_connect_gpio_out(dev, 0, poweroff_irq); 935 } 936 937 /* Platform Bus Device */ 938 if (params->has_platform_bus) { 939 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 940 dev->id = TYPE_PLATFORM_BUS_DEVICE; 941 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs); 942 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size); 943 qdev_init_nofail(dev); 944 s = SYS_BUS_DEVICE(dev); 945 946 for (i = 0; i < params->platform_bus_num_irqs; i++) { 947 int irqn = params->platform_bus_first_irq + i; 948 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 949 } 950 951 memory_region_add_subregion(address_space_mem, 952 params->platform_bus_base, 953 sysbus_mmio_get_region(s, 0)); 954 } 955 956 /* Load kernel. */ 957 if (machine->kernel_filename) { 958 kernel_base = cur_base; 959 kernel_size = load_image_targphys(machine->kernel_filename, 960 cur_base, 961 ram_size - cur_base); 962 if (kernel_size < 0) { 963 error_report("could not load kernel '%s'", 964 machine->kernel_filename); 965 exit(1); 966 } 967 968 cur_base += kernel_size; 969 } 970 971 /* Load initrd. */ 972 if (machine->initrd_filename) { 973 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 974 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 975 ram_size - initrd_base); 976 977 if (initrd_size < 0) { 978 error_report("could not load initial ram disk '%s'", 979 machine->initrd_filename); 980 exit(1); 981 } 982 983 cur_base = initrd_base + initrd_size; 984 } 985 986 /* 987 * Smart firmware defaults ahead! 988 * 989 * We follow the following table to select which payload we execute. 990 * 991 * -kernel | -bios | payload 992 * ---------+-------+--------- 993 * N | Y | u-boot 994 * N | N | u-boot 995 * Y | Y | u-boot 996 * Y | N | kernel 997 * 998 * This ensures backwards compatibility with how we used to expose 999 * -kernel to users but allows them to run through u-boot as well. 1000 */ 1001 if (bios_name == NULL) { 1002 if (machine->kernel_filename) { 1003 bios_name = machine->kernel_filename; 1004 } else { 1005 bios_name = "u-boot.e500"; 1006 } 1007 } 1008 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1009 1010 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 1011 1, PPC_ELF_MACHINE, 0, 0); 1012 if (bios_size < 0) { 1013 /* 1014 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1015 * ePAPR compliant kernel 1016 */ 1017 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1018 NULL, NULL); 1019 if (kernel_size < 0) { 1020 error_report("could not load firmware '%s'", filename); 1021 exit(1); 1022 } 1023 } 1024 g_free(filename); 1025 1026 /* Reserve space for dtb */ 1027 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1028 1029 dt_size = ppce500_prep_device_tree(machine, params, dt_base, 1030 initrd_base, initrd_size, 1031 kernel_base, kernel_size); 1032 if (dt_size < 0) { 1033 error_report("couldn't load device tree"); 1034 exit(1); 1035 } 1036 assert(dt_size < DTB_MAX_SIZE); 1037 1038 boot_info = env->load_info; 1039 boot_info->entry = bios_entry; 1040 boot_info->dt_base = dt_base; 1041 boot_info->dt_size = dt_size; 1042 } 1043 1044 static void e500_ccsr_initfn(Object *obj) 1045 { 1046 PPCE500CCSRState *ccsr = CCSR(obj); 1047 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1048 MPC8544_CCSRBAR_SIZE); 1049 } 1050 1051 static const TypeInfo e500_ccsr_info = { 1052 .name = TYPE_CCSR, 1053 .parent = TYPE_SYS_BUS_DEVICE, 1054 .instance_size = sizeof(PPCE500CCSRState), 1055 .instance_init = e500_ccsr_initfn, 1056 }; 1057 1058 static void e500_register_types(void) 1059 { 1060 type_register_static(&e500_ccsr_info); 1061 } 1062 1063 type_init(e500_register_types) 1064