1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "hw/sysbus.h" 36 #include "exec/address-spaces.h" 37 #include "qemu/host-utils.h" 38 #include "hw/pci-host/ppce500.h" 39 40 #define EPAPR_MAGIC (0x45504150) 41 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 42 #define UIMAGE_LOAD_BASE 0 43 #define DTC_LOAD_PAD 0x1800000 44 #define DTC_PAD_MASK 0xFFFFF 45 #define DTB_MAX_SIZE (8 * 1024 * 1024) 46 #define INITRD_LOAD_PAD 0x2000000 47 #define INITRD_PAD_MASK 0xFFFFFF 48 49 #define RAM_SIZES_ALIGN (64UL << 20) 50 51 /* TODO: parameterize */ 52 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 53 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 54 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 55 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 56 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 57 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 58 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 59 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ 60 MPC8544_PCI_REGS_OFFSET) 61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 62 #define MPC8544_PCI_IO 0xE1000000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8544_SPIN_BASE 0xEF000000ULL 65 66 struct boot_info 67 { 68 uint32_t dt_base; 69 uint32_t dt_size; 70 uint32_t entry; 71 }; 72 73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 74 int nr_slots, int *len) 75 { 76 int i = 0; 77 int slot; 78 int pci_irq; 79 int host_irq; 80 int last_slot = first_slot + nr_slots; 81 uint32_t *pci_map; 82 83 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 84 pci_map = g_malloc(*len); 85 86 for (slot = first_slot; slot < last_slot; slot++) { 87 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 88 pci_map[i++] = cpu_to_be32(slot << 11); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(pci_irq + 1); 92 pci_map[i++] = cpu_to_be32(mpic); 93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 94 pci_map[i++] = cpu_to_be32(host_irq + 1); 95 pci_map[i++] = cpu_to_be32(0x1); 96 } 97 } 98 99 assert((i * sizeof(uint32_t)) == *len); 100 101 return pci_map; 102 } 103 104 static void dt_serial_create(void *fdt, unsigned long long offset, 105 const char *soc, const char *mpic, 106 const char *alias, int idx, bool defcon) 107 { 108 char ser[128]; 109 110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 111 qemu_devtree_add_subnode(fdt, ser); 112 qemu_devtree_setprop_string(fdt, ser, "device_type", "serial"); 113 qemu_devtree_setprop_string(fdt, ser, "compatible", "ns16550"); 114 qemu_devtree_setprop_cells(fdt, ser, "reg", offset, 0x100); 115 qemu_devtree_setprop_cell(fdt, ser, "cell-index", idx); 116 qemu_devtree_setprop_cell(fdt, ser, "clock-frequency", 0); 117 qemu_devtree_setprop_cells(fdt, ser, "interrupts", 42, 2); 118 qemu_devtree_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 119 qemu_devtree_setprop_string(fdt, "/aliases", alias, ser); 120 121 if (defcon) { 122 qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 123 } 124 } 125 126 static int ppce500_load_device_tree(CPUPPCState *env, 127 QEMUMachineInitArgs *args, 128 PPCE500Params *params, 129 hwaddr addr, 130 hwaddr initrd_base, 131 hwaddr initrd_size) 132 { 133 int ret = -1; 134 uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) }; 135 int fdt_size; 136 void *fdt; 137 uint8_t hypercall[16]; 138 uint32_t clock_freq = 400000000; 139 uint32_t tb_freq = 400000000; 140 int i; 141 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 142 char soc[128]; 143 char mpic[128]; 144 uint32_t mpic_ph; 145 uint32_t msi_ph; 146 char gutil[128]; 147 char pci[128]; 148 char msi[128]; 149 uint32_t *pci_map = NULL; 150 int len; 151 uint32_t pci_ranges[14] = 152 { 153 0x2000000, 0x0, 0xc0000000, 154 0x0, 0xc0000000, 155 0x0, 0x20000000, 156 157 0x1000000, 0x0, 0x0, 158 0x0, 0xe1000000, 159 0x0, 0x10000, 160 }; 161 QemuOpts *machine_opts = qemu_get_machine_opts(); 162 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 163 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 164 165 if (dtb_file) { 166 char *filename; 167 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 168 if (!filename) { 169 goto out; 170 } 171 172 fdt = load_device_tree(filename, &fdt_size); 173 if (!fdt) { 174 goto out; 175 } 176 goto done; 177 } 178 179 fdt = create_device_tree(&fdt_size); 180 if (fdt == NULL) { 181 goto out; 182 } 183 184 /* Manipulate device tree in memory. */ 185 qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 2); 186 qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 2); 187 188 qemu_devtree_add_subnode(fdt, "/memory"); 189 qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory"); 190 qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property, 191 sizeof(mem_reg_property)); 192 193 qemu_devtree_add_subnode(fdt, "/chosen"); 194 if (initrd_size) { 195 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", 196 initrd_base); 197 if (ret < 0) { 198 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 199 } 200 201 ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", 202 (initrd_base + initrd_size)); 203 if (ret < 0) { 204 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 205 } 206 } 207 208 ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs", 209 args->kernel_cmdline); 210 if (ret < 0) 211 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 212 213 if (kvm_enabled()) { 214 /* Read out host's frequencies */ 215 clock_freq = kvmppc_get_clockfreq(); 216 tb_freq = kvmppc_get_tbfreq(); 217 218 /* indicate KVM hypercall interface */ 219 qemu_devtree_add_subnode(fdt, "/hypervisor"); 220 qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible", 221 "linux,kvm"); 222 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 223 qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions", 224 hypercall, sizeof(hypercall)); 225 /* if KVM supports the idle hcall, set property indicating this */ 226 if (kvmppc_get_hasidle(env)) { 227 qemu_devtree_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 228 } 229 } 230 231 /* Create CPU nodes */ 232 qemu_devtree_add_subnode(fdt, "/cpus"); 233 qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1); 234 qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0); 235 236 /* We need to generate the cpu nodes in reverse order, so Linux can pick 237 the first node as boot node and be happy */ 238 for (i = smp_cpus - 1; i >= 0; i--) { 239 CPUState *cpu; 240 char cpu_name[128]; 241 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 242 243 cpu = qemu_get_cpu(i); 244 if (cpu == NULL) { 245 continue; 246 } 247 env = cpu->env_ptr; 248 249 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 250 cpu->cpu_index); 251 qemu_devtree_add_subnode(fdt, cpu_name); 252 qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 253 qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 254 qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu"); 255 qemu_devtree_setprop_cell(fdt, cpu_name, "reg", cpu->cpu_index); 256 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size", 257 env->dcache_line_size); 258 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size", 259 env->icache_line_size); 260 qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 261 qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 262 qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 263 if (cpu->cpu_index) { 264 qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled"); 265 qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table"); 266 qemu_devtree_setprop_u64(fdt, cpu_name, "cpu-release-addr", 267 cpu_release_addr); 268 } else { 269 qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay"); 270 } 271 } 272 273 qemu_devtree_add_subnode(fdt, "/aliases"); 274 /* XXX These should go into their respective devices' code */ 275 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 276 qemu_devtree_add_subnode(fdt, soc); 277 qemu_devtree_setprop_string(fdt, soc, "device_type", "soc"); 278 qemu_devtree_setprop(fdt, soc, "compatible", compatible_sb, 279 sizeof(compatible_sb)); 280 qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1); 281 qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1); 282 qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, 283 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 284 MPC8544_CCSRBAR_SIZE); 285 /* XXX should contain a reasonable value */ 286 qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0); 287 288 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 289 qemu_devtree_add_subnode(fdt, mpic); 290 qemu_devtree_setprop_string(fdt, mpic, "device_type", "open-pic"); 291 qemu_devtree_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 292 qemu_devtree_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 293 0x40000); 294 qemu_devtree_setprop_cell(fdt, mpic, "#address-cells", 0); 295 qemu_devtree_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 296 mpic_ph = qemu_devtree_alloc_phandle(fdt); 297 qemu_devtree_setprop_cell(fdt, mpic, "phandle", mpic_ph); 298 qemu_devtree_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 299 qemu_devtree_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 300 301 /* 302 * We have to generate ser1 first, because Linux takes the first 303 * device it finds in the dt as serial output device. And we generate 304 * devices in reverse order to the dt. 305 */ 306 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 307 soc, mpic, "serial1", 1, false); 308 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 309 soc, mpic, "serial0", 0, true); 310 311 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 312 MPC8544_UTIL_OFFSET); 313 qemu_devtree_add_subnode(fdt, gutil); 314 qemu_devtree_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 315 qemu_devtree_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 316 qemu_devtree_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 317 318 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 319 qemu_devtree_add_subnode(fdt, msi); 320 qemu_devtree_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 321 qemu_devtree_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 322 msi_ph = qemu_devtree_alloc_phandle(fdt); 323 qemu_devtree_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 324 qemu_devtree_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 325 qemu_devtree_setprop_cells(fdt, msi, "interrupts", 326 0xe0, 0x0, 327 0xe1, 0x0, 328 0xe2, 0x0, 329 0xe3, 0x0, 330 0xe4, 0x0, 331 0xe5, 0x0, 332 0xe6, 0x0, 333 0xe7, 0x0); 334 qemu_devtree_setprop_cell(fdt, msi, "phandle", msi_ph); 335 qemu_devtree_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 336 337 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 338 qemu_devtree_add_subnode(fdt, pci); 339 qemu_devtree_setprop_cell(fdt, pci, "cell-index", 0); 340 qemu_devtree_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 341 qemu_devtree_setprop_string(fdt, pci, "device_type", "pci"); 342 qemu_devtree_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 343 0x0, 0x7); 344 pci_map = pci_map_create(fdt, qemu_devtree_get_phandle(fdt, mpic), 345 params->pci_first_slot, params->pci_nr_slots, 346 &len); 347 qemu_devtree_setprop(fdt, pci, "interrupt-map", pci_map, len); 348 qemu_devtree_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 349 qemu_devtree_setprop_cells(fdt, pci, "interrupts", 24, 2); 350 qemu_devtree_setprop_cells(fdt, pci, "bus-range", 0, 255); 351 for (i = 0; i < 14; i++) { 352 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 353 } 354 qemu_devtree_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 355 qemu_devtree_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 356 qemu_devtree_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 357 MPC8544_PCI_REGS_BASE, 0, 0x1000); 358 qemu_devtree_setprop_cell(fdt, pci, "clock-frequency", 66666666); 359 qemu_devtree_setprop_cell(fdt, pci, "#interrupt-cells", 1); 360 qemu_devtree_setprop_cell(fdt, pci, "#size-cells", 2); 361 qemu_devtree_setprop_cell(fdt, pci, "#address-cells", 3); 362 qemu_devtree_setprop_string(fdt, "/aliases", "pci0", pci); 363 364 params->fixup_devtree(params, fdt); 365 366 if (toplevel_compat) { 367 qemu_devtree_setprop(fdt, "/", "compatible", toplevel_compat, 368 strlen(toplevel_compat) + 1); 369 } 370 371 done: 372 qemu_devtree_dumpdtb(fdt, fdt_size); 373 ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); 374 if (ret < 0) { 375 goto out; 376 } 377 g_free(fdt); 378 ret = fdt_size; 379 380 out: 381 g_free(pci_map); 382 383 return ret; 384 } 385 386 /* Create -kernel TLB entries for BookE. */ 387 static inline hwaddr booke206_page_size_to_tlb(uint64_t size) 388 { 389 return 63 - clz64(size >> 10); 390 } 391 392 static int booke206_initial_map_tsize(CPUPPCState *env) 393 { 394 struct boot_info *bi = env->load_info; 395 hwaddr dt_end; 396 int ps; 397 398 /* Our initial TLB entry needs to cover everything from 0 to 399 the device tree top */ 400 dt_end = bi->dt_base + bi->dt_size; 401 ps = booke206_page_size_to_tlb(dt_end) + 1; 402 if (ps & 1) { 403 /* e500v2 can only do even TLB size bits */ 404 ps++; 405 } 406 return ps; 407 } 408 409 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 410 { 411 int tsize; 412 413 tsize = booke206_initial_map_tsize(env); 414 return (1ULL << 10 << tsize); 415 } 416 417 static void mmubooke_create_initial_mapping(CPUPPCState *env) 418 { 419 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 420 hwaddr size; 421 int ps; 422 423 ps = booke206_initial_map_tsize(env); 424 size = (ps << MAS1_TSIZE_SHIFT); 425 tlb->mas1 = MAS1_VALID | size; 426 tlb->mas2 = 0; 427 tlb->mas7_3 = 0; 428 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 429 430 env->tlb_dirty = true; 431 } 432 433 static void ppce500_cpu_reset_sec(void *opaque) 434 { 435 PowerPCCPU *cpu = opaque; 436 CPUState *cs = CPU(cpu); 437 CPUPPCState *env = &cpu->env; 438 439 cpu_reset(cs); 440 441 /* Secondary CPU starts in halted state for now. Needs to change when 442 implementing non-kernel boot. */ 443 cs->halted = 1; 444 env->exception_index = EXCP_HLT; 445 } 446 447 static void ppce500_cpu_reset(void *opaque) 448 { 449 PowerPCCPU *cpu = opaque; 450 CPUState *cs = CPU(cpu); 451 CPUPPCState *env = &cpu->env; 452 struct boot_info *bi = env->load_info; 453 454 cpu_reset(cs); 455 456 /* Set initial guest state. */ 457 cs->halted = 0; 458 env->gpr[1] = (16<<20) - 8; 459 env->gpr[3] = bi->dt_base; 460 env->gpr[4] = 0; 461 env->gpr[5] = 0; 462 env->gpr[6] = EPAPR_MAGIC; 463 env->gpr[7] = mmubooke_initial_mapsize(env); 464 env->gpr[8] = 0; 465 env->gpr[9] = 0; 466 env->nip = bi->entry; 467 mmubooke_create_initial_mapping(env); 468 } 469 470 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 471 qemu_irq **irqs) 472 { 473 DeviceState *dev; 474 SysBusDevice *s; 475 int i, j, k; 476 477 dev = qdev_create(NULL, TYPE_OPENPIC); 478 qdev_prop_set_uint32(dev, "model", params->mpic_version); 479 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 480 481 qdev_init_nofail(dev); 482 s = SYS_BUS_DEVICE(dev); 483 484 k = 0; 485 for (i = 0; i < smp_cpus; i++) { 486 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 487 sysbus_connect_irq(s, k++, irqs[i][j]); 488 } 489 } 490 491 return dev; 492 } 493 494 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 495 qemu_irq **irqs) 496 { 497 DeviceState *dev; 498 CPUState *cs; 499 int r; 500 501 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 502 qdev_prop_set_uint32(dev, "model", params->mpic_version); 503 504 r = qdev_init(dev); 505 if (r) { 506 return NULL; 507 } 508 509 for (cs = first_cpu; cs != NULL; cs = cs->next_cpu) { 510 if (kvm_openpic_connect_vcpu(dev, cs)) { 511 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 512 __func__); 513 abort(); 514 } 515 } 516 517 return dev; 518 } 519 520 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr, 521 qemu_irq **irqs) 522 { 523 qemu_irq *mpic; 524 DeviceState *dev = NULL; 525 SysBusDevice *s; 526 int i; 527 528 mpic = g_new(qemu_irq, 256); 529 530 if (kvm_enabled()) { 531 QemuOpts *machine_opts = qemu_get_machine_opts(); 532 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 533 "kernel_irqchip", true); 534 bool irqchip_required = qemu_opt_get_bool(machine_opts, 535 "kernel_irqchip", false); 536 537 if (irqchip_allowed) { 538 dev = ppce500_init_mpic_kvm(params, irqs); 539 } 540 541 if (irqchip_required && !dev) { 542 fprintf(stderr, "%s: irqchip requested but unavailable\n", 543 __func__); 544 abort(); 545 } 546 } 547 548 if (!dev) { 549 dev = ppce500_init_mpic_qemu(params, irqs); 550 } 551 552 for (i = 0; i < 256; i++) { 553 mpic[i] = qdev_get_gpio_in(dev, i); 554 } 555 556 s = SYS_BUS_DEVICE(dev); 557 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 558 s->mmio[0].memory); 559 560 return mpic; 561 } 562 563 void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params) 564 { 565 MemoryRegion *address_space_mem = get_system_memory(); 566 MemoryRegion *ram = g_new(MemoryRegion, 1); 567 PCIBus *pci_bus; 568 CPUPPCState *env = NULL; 569 uint64_t elf_entry; 570 uint64_t elf_lowaddr; 571 hwaddr entry=0; 572 hwaddr loadaddr=UIMAGE_LOAD_BASE; 573 target_long kernel_size=0; 574 target_ulong dt_base = 0; 575 target_ulong initrd_base = 0; 576 target_long initrd_size = 0; 577 target_ulong cur_base = 0; 578 int i; 579 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; 580 qemu_irq **irqs, *mpic; 581 DeviceState *dev; 582 CPUPPCState *firstenv = NULL; 583 MemoryRegion *ccsr_addr_space; 584 SysBusDevice *s; 585 PPCE500CCSRState *ccsr; 586 587 /* Setup CPUs */ 588 if (args->cpu_model == NULL) { 589 args->cpu_model = "e500v2_v30"; 590 } 591 592 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 593 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 594 for (i = 0; i < smp_cpus; i++) { 595 PowerPCCPU *cpu; 596 CPUState *cs; 597 qemu_irq *input; 598 599 cpu = cpu_ppc_init(args->cpu_model); 600 if (cpu == NULL) { 601 fprintf(stderr, "Unable to initialize CPU!\n"); 602 exit(1); 603 } 604 env = &cpu->env; 605 cs = CPU(cpu); 606 607 if (!firstenv) { 608 firstenv = env; 609 } 610 611 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 612 input = (qemu_irq *)env->irq_inputs; 613 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 614 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 615 env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; 616 env->mpic_iack = MPC8544_CCSRBAR_BASE + 617 MPC8544_MPIC_REGS_OFFSET + 0xa0; 618 619 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 620 621 /* Register reset handler */ 622 if (!i) { 623 /* Primary CPU */ 624 struct boot_info *boot_info; 625 boot_info = g_malloc0(sizeof(struct boot_info)); 626 qemu_register_reset(ppce500_cpu_reset, cpu); 627 env->load_info = boot_info; 628 } else { 629 /* Secondary CPUs */ 630 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 631 } 632 } 633 634 env = firstenv; 635 636 /* Fixup Memory size on a alignment boundary */ 637 ram_size &= ~(RAM_SIZES_ALIGN - 1); 638 args->ram_size = ram_size; 639 640 /* Register Memory */ 641 memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); 642 vmstate_register_ram_global(ram); 643 memory_region_add_subregion(address_space_mem, 0, ram); 644 645 dev = qdev_create(NULL, "e500-ccsr"); 646 object_property_add_child(qdev_get_machine(), "e500-ccsr", 647 OBJECT(dev), NULL); 648 qdev_init_nofail(dev); 649 ccsr = CCSR(dev); 650 ccsr_addr_space = &ccsr->ccsr_space; 651 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, 652 ccsr_addr_space); 653 654 mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); 655 656 /* Serial */ 657 if (serial_hds[0]) { 658 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 659 0, mpic[42], 399193, 660 serial_hds[0], DEVICE_BIG_ENDIAN); 661 } 662 663 if (serial_hds[1]) { 664 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 665 0, mpic[42], 399193, 666 serial_hds[1], DEVICE_BIG_ENDIAN); 667 } 668 669 /* General Utility device */ 670 dev = qdev_create(NULL, "mpc8544-guts"); 671 qdev_init_nofail(dev); 672 s = SYS_BUS_DEVICE(dev); 673 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 674 sysbus_mmio_get_region(s, 0)); 675 676 /* PCI */ 677 dev = qdev_create(NULL, "e500-pcihost"); 678 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 679 qdev_init_nofail(dev); 680 s = SYS_BUS_DEVICE(dev); 681 sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); 682 sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); 683 sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); 684 sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); 685 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 686 sysbus_mmio_get_region(s, 0)); 687 688 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 689 if (!pci_bus) 690 printf("couldn't create PCI controller!\n"); 691 692 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); 693 694 if (pci_bus) { 695 /* Register network interfaces. */ 696 for (i = 0; i < nb_nics; i++) { 697 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 698 } 699 } 700 701 /* Register spinning region */ 702 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 703 704 /* Load kernel. */ 705 if (args->kernel_filename) { 706 kernel_size = load_uimage(args->kernel_filename, &entry, 707 &loadaddr, NULL); 708 if (kernel_size < 0) { 709 kernel_size = load_elf(args->kernel_filename, NULL, NULL, 710 &elf_entry, &elf_lowaddr, NULL, 1, 711 ELF_MACHINE, 0); 712 entry = elf_entry; 713 loadaddr = elf_lowaddr; 714 } 715 /* XXX try again as binary */ 716 if (kernel_size < 0) { 717 fprintf(stderr, "qemu: could not load kernel '%s'\n", 718 args->kernel_filename); 719 exit(1); 720 } 721 722 cur_base = loadaddr + kernel_size; 723 724 /* Reserve space for dtb */ 725 dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 726 cur_base += DTB_MAX_SIZE; 727 } 728 729 /* Load initrd. */ 730 if (args->initrd_filename) { 731 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 732 initrd_size = load_image_targphys(args->initrd_filename, initrd_base, 733 ram_size - initrd_base); 734 735 if (initrd_size < 0) { 736 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 737 args->initrd_filename); 738 exit(1); 739 } 740 741 cur_base = initrd_base + initrd_size; 742 } 743 744 /* If we're loading a kernel directly, we must load the device tree too. */ 745 if (args->kernel_filename) { 746 struct boot_info *boot_info; 747 int dt_size; 748 749 dt_size = ppce500_load_device_tree(env, args, params, dt_base, 750 initrd_base, initrd_size); 751 if (dt_size < 0) { 752 fprintf(stderr, "couldn't load device tree\n"); 753 exit(1); 754 } 755 assert(dt_size < DTB_MAX_SIZE); 756 757 boot_info = env->load_info; 758 boot_info->entry = entry; 759 boot_info->dt_base = dt_base; 760 boot_info->dt_size = dt_size; 761 } 762 763 if (kvm_enabled()) { 764 kvmppc_init(); 765 } 766 } 767 768 static int e500_ccsr_initfn(SysBusDevice *dev) 769 { 770 PPCE500CCSRState *ccsr; 771 772 ccsr = CCSR(dev); 773 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 774 MPC8544_CCSRBAR_SIZE); 775 return 0; 776 } 777 778 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 779 { 780 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 781 k->init = e500_ccsr_initfn; 782 } 783 784 static const TypeInfo e500_ccsr_info = { 785 .name = TYPE_CCSR, 786 .parent = TYPE_SYS_BUS_DEVICE, 787 .instance_size = sizeof(PPCE500CCSRState), 788 .class_init = e500_ccsr_class_init, 789 }; 790 791 static void e500_register_types(void) 792 { 793 type_register_static(&e500_ccsr_info); 794 } 795 796 type_init(e500_register_types) 797