xref: /openbmc/qemu/hw/ppc/e500.c (revision 650d103d3ea959212f826acb9d3fe80cf30e347b)
1 /*
2  * QEMU PowerPC e500-based platforms
3  *
4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5  *
6  * Author: Yu Liu,     <yu.liu@freescale.com>
7  *
8  * This file is derived from hw/ppc440_bamboo.c,
9  * the copyright for that material belongs to the original owners.
10  *
11  * This is free software; you can redistribute it and/or modify
12  * it under the terms of  the GNU General  Public License as published by
13  * the Free Software Foundation;  either version 2 of the  License, or
14  * (at your option) any later version.
15  */
16 
17 #include "qemu/osdep.h"
18 #include "qemu-common.h"
19 #include "qemu/units.h"
20 #include "qapi/error.h"
21 #include "e500.h"
22 #include "e500-ccsr.h"
23 #include "net/net.h"
24 #include "qemu/config-file.h"
25 #include "hw/char/serial.h"
26 #include "hw/pci/pci.h"
27 #include "hw/boards.h"
28 #include "sysemu/sysemu.h"
29 #include "sysemu/kvm.h"
30 #include "sysemu/reset.h"
31 #include "kvm_ppc.h"
32 #include "sysemu/device_tree.h"
33 #include "hw/ppc/openpic.h"
34 #include "hw/ppc/openpic_kvm.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/loader.h"
37 #include "elf.h"
38 #include "hw/sysbus.h"
39 #include "exec/address-spaces.h"
40 #include "qemu/host-utils.h"
41 #include "qemu/option.h"
42 #include "hw/pci-host/ppce500.h"
43 #include "qemu/error-report.h"
44 #include "hw/platform-bus.h"
45 #include "hw/net/fsl_etsec/etsec.h"
46 #include "hw/i2c/i2c.h"
47 #include "hw/irq.h"
48 
49 #define EPAPR_MAGIC                (0x45504150)
50 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
51 #define DTC_LOAD_PAD               0x1800000
52 #define DTC_PAD_MASK               0xFFFFF
53 #define DTB_MAX_SIZE               (8 * MiB)
54 #define INITRD_LOAD_PAD            0x2000000
55 #define INITRD_PAD_MASK            0xFFFFFF
56 
57 #define RAM_SIZES_ALIGN            (64 * MiB)
58 
59 /* TODO: parameterize */
60 #define MPC8544_CCSRBAR_SIZE       0x00100000ULL
61 #define MPC8544_MPIC_REGS_OFFSET   0x40000ULL
62 #define MPC8544_MSI_REGS_OFFSET   0x41600ULL
63 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
64 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
65 #define MPC8544_PCI_REGS_OFFSET    0x8000ULL
66 #define MPC8544_PCI_REGS_SIZE      0x1000ULL
67 #define MPC8544_UTIL_OFFSET        0xe0000ULL
68 #define MPC8XXX_GPIO_OFFSET        0x000FF000ULL
69 #define MPC8544_I2C_REGS_OFFSET    0x3000ULL
70 #define MPC8XXX_GPIO_IRQ           47
71 #define MPC8544_I2C_IRQ            43
72 #define RTC_REGS_OFFSET            0x68
73 
74 struct boot_info
75 {
76     uint32_t dt_base;
77     uint32_t dt_size;
78     uint32_t entry;
79 };
80 
81 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
82                                 int nr_slots, int *len)
83 {
84     int i = 0;
85     int slot;
86     int pci_irq;
87     int host_irq;
88     int last_slot = first_slot + nr_slots;
89     uint32_t *pci_map;
90 
91     *len = nr_slots * 4 * 7 * sizeof(uint32_t);
92     pci_map = g_malloc(*len);
93 
94     for (slot = first_slot; slot < last_slot; slot++) {
95         for (pci_irq = 0; pci_irq < 4; pci_irq++) {
96             pci_map[i++] = cpu_to_be32(slot << 11);
97             pci_map[i++] = cpu_to_be32(0x0);
98             pci_map[i++] = cpu_to_be32(0x0);
99             pci_map[i++] = cpu_to_be32(pci_irq + 1);
100             pci_map[i++] = cpu_to_be32(mpic);
101             host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
102             pci_map[i++] = cpu_to_be32(host_irq + 1);
103             pci_map[i++] = cpu_to_be32(0x1);
104         }
105     }
106 
107     assert((i * sizeof(uint32_t)) == *len);
108 
109     return pci_map;
110 }
111 
112 static void dt_serial_create(void *fdt, unsigned long long offset,
113                              const char *soc, const char *mpic,
114                              const char *alias, int idx, bool defcon)
115 {
116     char *ser;
117 
118     ser = g_strdup_printf("%s/serial@%llx", soc, offset);
119     qemu_fdt_add_subnode(fdt, ser);
120     qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
121     qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
122     qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
123     qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
124     qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
125     qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
126     qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
127     qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
128 
129     if (defcon) {
130         /*
131          * "linux,stdout-path" and "stdout" properties are deprecated by linux
132          * kernel. New platforms should only use the "stdout-path" property. Set
133          * the new property and continue using older property to remain
134          * compatible with the existing firmware.
135          */
136         qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
137         qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
138     }
139     g_free(ser);
140 }
141 
142 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
143 {
144     hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
145     int irq0 = MPC8XXX_GPIO_IRQ;
146     gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
147     gchar *poweroff = g_strdup_printf("%s/power-off", soc);
148     int gpio_ph;
149 
150     qemu_fdt_add_subnode(fdt, node);
151     qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
152     qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
153     qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
154     qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
155     qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
156     qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
157     gpio_ph = qemu_fdt_alloc_phandle(fdt);
158     qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
159     qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
160 
161     /* Power Off Pin */
162     qemu_fdt_add_subnode(fdt, poweroff);
163     qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
164     qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
165 
166     g_free(node);
167     g_free(poweroff);
168 }
169 
170 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
171 {
172     int offset = RTC_REGS_OFFSET;
173 
174     gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
175     qemu_fdt_add_subnode(fdt, rtc);
176     qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
177     qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
178     qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
179 
180     g_free(rtc);
181 }
182 
183 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
184                              const char *alias)
185 {
186     hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
187     int irq0 = MPC8544_I2C_IRQ;
188 
189     gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
190     qemu_fdt_add_subnode(fdt, i2c);
191     qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
192     qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
193     qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
194     qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
195     qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
196     qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
197     qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
198 
199     g_free(i2c);
200 }
201 
202 
203 typedef struct PlatformDevtreeData {
204     void *fdt;
205     const char *mpic;
206     int irq_start;
207     const char *node;
208     PlatformBusDevice *pbus;
209 } PlatformDevtreeData;
210 
211 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
212 {
213     eTSEC *etsec = ETSEC_COMMON(sbdev);
214     PlatformBusDevice *pbus = data->pbus;
215     hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
216     int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
217     int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
218     int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
219     gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
220     gchar *group = g_strdup_printf("%s/queue-group", node);
221     void *fdt = data->fdt;
222 
223     assert((int64_t)mmio0 >= 0);
224     assert(irq0 >= 0);
225     assert(irq1 >= 0);
226     assert(irq2 >= 0);
227 
228     qemu_fdt_add_subnode(fdt, node);
229     qemu_fdt_setprop_string(fdt, node, "device_type", "network");
230     qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
231     qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
232     qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
233     qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
234 
235     qemu_fdt_add_subnode(fdt, group);
236     qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
237     qemu_fdt_setprop_cells(fdt, group, "interrupts",
238         data->irq_start + irq0, 0x2,
239         data->irq_start + irq1, 0x2,
240         data->irq_start + irq2, 0x2);
241 
242     g_free(node);
243     g_free(group);
244 
245     return 0;
246 }
247 
248 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
249 {
250     PlatformDevtreeData *data = opaque;
251     bool matched = false;
252 
253     if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
254         create_devtree_etsec(sbdev, data);
255         matched = true;
256     }
257 
258     if (!matched) {
259         error_report("Device %s is not supported by this machine yet.",
260                      qdev_fw_name(DEVICE(sbdev)));
261         exit(1);
262     }
263 }
264 
265 static void platform_bus_create_devtree(PPCE500MachineState *pms,
266                                         void *fdt, const char *mpic)
267 {
268     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
269     gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
270     const char platcomp[] = "qemu,platform\0simple-bus";
271     uint64_t addr = pmc->platform_bus_base;
272     uint64_t size = pmc->platform_bus_size;
273     int irq_start = pmc->platform_bus_first_irq;
274 
275     /* Create a /platform node that we can put all devices into */
276 
277     qemu_fdt_add_subnode(fdt, node);
278     qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
279 
280     /* Our platform bus region is less than 32bit big, so 1 cell is enough for
281        address and size */
282     qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
283     qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
284     qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
285 
286     qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
287 
288     /* Create dt nodes for dynamic devices */
289     PlatformDevtreeData data = {
290         .fdt = fdt,
291         .mpic = mpic,
292         .irq_start = irq_start,
293         .node = node,
294         .pbus = pms->pbus_dev,
295     };
296 
297     /* Loop through all dynamic sysbus devices and create nodes for them */
298     foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
299 
300     g_free(node);
301 }
302 
303 static int ppce500_load_device_tree(PPCE500MachineState *pms,
304                                     hwaddr addr,
305                                     hwaddr initrd_base,
306                                     hwaddr initrd_size,
307                                     hwaddr kernel_base,
308                                     hwaddr kernel_size,
309                                     bool dry_run)
310 {
311     MachineState *machine = MACHINE(pms);
312     unsigned int smp_cpus = machine->smp.cpus;
313     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
314     CPUPPCState *env = first_cpu->env_ptr;
315     int ret = -1;
316     uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
317     int fdt_size;
318     void *fdt;
319     uint8_t hypercall[16];
320     uint32_t clock_freq = 400000000;
321     uint32_t tb_freq = 400000000;
322     int i;
323     char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
324     char *soc;
325     char *mpic;
326     uint32_t mpic_ph;
327     uint32_t msi_ph;
328     char *gutil;
329     char *pci;
330     char *msi;
331     uint32_t *pci_map = NULL;
332     int len;
333     uint32_t pci_ranges[14] =
334         {
335             0x2000000, 0x0, pmc->pci_mmio_bus_base,
336             pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
337             0x0, 0x20000000,
338 
339             0x1000000, 0x0, 0x0,
340             pmc->pci_pio_base >> 32, pmc->pci_pio_base,
341             0x0, 0x10000,
342         };
343     QemuOpts *machine_opts = qemu_get_machine_opts();
344     const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
345     const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
346 
347     if (dtb_file) {
348         char *filename;
349         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
350         if (!filename) {
351             goto out;
352         }
353 
354         fdt = load_device_tree(filename, &fdt_size);
355         g_free(filename);
356         if (!fdt) {
357             goto out;
358         }
359         goto done;
360     }
361 
362     fdt = create_device_tree(&fdt_size);
363     if (fdt == NULL) {
364         goto out;
365     }
366 
367     /* Manipulate device tree in memory. */
368     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
369     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
370 
371     qemu_fdt_add_subnode(fdt, "/memory");
372     qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
373     qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
374                      sizeof(mem_reg_property));
375 
376     qemu_fdt_add_subnode(fdt, "/chosen");
377     if (initrd_size) {
378         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
379                                     initrd_base);
380         if (ret < 0) {
381             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
382         }
383 
384         ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
385                                     (initrd_base + initrd_size));
386         if (ret < 0) {
387             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
388         }
389 
390     }
391 
392     if (kernel_base != -1ULL) {
393         qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
394                                      kernel_base >> 32, kernel_base,
395                                      kernel_size >> 32, kernel_size);
396     }
397 
398     ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
399                                       machine->kernel_cmdline);
400     if (ret < 0)
401         fprintf(stderr, "couldn't set /chosen/bootargs\n");
402 
403     if (kvm_enabled()) {
404         /* Read out host's frequencies */
405         clock_freq = kvmppc_get_clockfreq();
406         tb_freq = kvmppc_get_tbfreq();
407 
408         /* indicate KVM hypercall interface */
409         qemu_fdt_add_subnode(fdt, "/hypervisor");
410         qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
411                                 "linux,kvm");
412         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
413         qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
414                          hypercall, sizeof(hypercall));
415         /* if KVM supports the idle hcall, set property indicating this */
416         if (kvmppc_get_hasidle(env)) {
417             qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
418         }
419     }
420 
421     /* Create CPU nodes */
422     qemu_fdt_add_subnode(fdt, "/cpus");
423     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
424     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
425 
426     /* We need to generate the cpu nodes in reverse order, so Linux can pick
427        the first node as boot node and be happy */
428     for (i = smp_cpus - 1; i >= 0; i--) {
429         CPUState *cpu;
430         char *cpu_name;
431         uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
432 
433         cpu = qemu_get_cpu(i);
434         if (cpu == NULL) {
435             continue;
436         }
437         env = cpu->env_ptr;
438 
439         cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
440         qemu_fdt_add_subnode(fdt, cpu_name);
441         qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
442         qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
443         qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
444         qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
445         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
446                               env->dcache_line_size);
447         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
448                               env->icache_line_size);
449         qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
450         qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
451         qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
452         if (cpu->cpu_index) {
453             qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
454             qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
455                                     "spin-table");
456             qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
457                                  cpu_release_addr);
458         } else {
459             qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
460         }
461         g_free(cpu_name);
462     }
463 
464     qemu_fdt_add_subnode(fdt, "/aliases");
465     /* XXX These should go into their respective devices' code */
466     soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
467     qemu_fdt_add_subnode(fdt, soc);
468     qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
469     qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
470                      sizeof(compatible_sb));
471     qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
472     qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
473     qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
474                            pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
475                            MPC8544_CCSRBAR_SIZE);
476     /* XXX should contain a reasonable value */
477     qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
478 
479     mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
480     qemu_fdt_add_subnode(fdt, mpic);
481     qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
482     qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
483     qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
484                            0x40000);
485     qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
486     qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
487     mpic_ph = qemu_fdt_alloc_phandle(fdt);
488     qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
489     qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
490     qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
491 
492     /*
493      * We have to generate ser1 first, because Linux takes the first
494      * device it finds in the dt as serial output device. And we generate
495      * devices in reverse order to the dt.
496      */
497     if (serial_hd(1)) {
498         dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
499                          soc, mpic, "serial1", 1, false);
500     }
501 
502     if (serial_hd(0)) {
503         dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
504                          soc, mpic, "serial0", 0, true);
505     }
506 
507     /* i2c */
508     dt_i2c_create(fdt, soc, mpic, "i2c");
509 
510     dt_rtc_create(fdt, "i2c", "rtc");
511 
512 
513     gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
514                             MPC8544_UTIL_OFFSET);
515     qemu_fdt_add_subnode(fdt, gutil);
516     qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
517     qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
518     qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
519     g_free(gutil);
520 
521     msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
522     qemu_fdt_add_subnode(fdt, msi);
523     qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
524     qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
525     msi_ph = qemu_fdt_alloc_phandle(fdt);
526     qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
527     qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
528     qemu_fdt_setprop_cells(fdt, msi, "interrupts",
529         0xe0, 0x0,
530         0xe1, 0x0,
531         0xe2, 0x0,
532         0xe3, 0x0,
533         0xe4, 0x0,
534         0xe5, 0x0,
535         0xe6, 0x0,
536         0xe7, 0x0);
537     qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
538     qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
539     g_free(msi);
540 
541     pci = g_strdup_printf("/pci@%llx",
542                           pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
543     qemu_fdt_add_subnode(fdt, pci);
544     qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
545     qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
546     qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
547     qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
548                            0x0, 0x7);
549     pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
550                              pmc->pci_first_slot, pmc->pci_nr_slots,
551                              &len);
552     qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
553     qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
554     qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
555     qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
556     for (i = 0; i < 14; i++) {
557         pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
558     }
559     qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
560     qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
561     qemu_fdt_setprop_cells(fdt, pci, "reg",
562                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
563                            (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
564                            0, 0x1000);
565     qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
566     qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
567     qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
568     qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
569     qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
570     g_free(pci);
571 
572     if (pmc->has_mpc8xxx_gpio) {
573         create_dt_mpc8xxx_gpio(fdt, soc, mpic);
574     }
575     g_free(soc);
576 
577     if (pms->pbus_dev) {
578         platform_bus_create_devtree(pms, fdt, mpic);
579     }
580     g_free(mpic);
581 
582     pmc->fixup_devtree(fdt);
583 
584     if (toplevel_compat) {
585         qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
586                          strlen(toplevel_compat) + 1);
587     }
588 
589 done:
590     if (!dry_run) {
591         qemu_fdt_dumpdtb(fdt, fdt_size);
592         cpu_physical_memory_write(addr, fdt, fdt_size);
593     }
594     ret = fdt_size;
595 
596 out:
597     g_free(pci_map);
598 
599     return ret;
600 }
601 
602 typedef struct DeviceTreeParams {
603     PPCE500MachineState *machine;
604     hwaddr addr;
605     hwaddr initrd_base;
606     hwaddr initrd_size;
607     hwaddr kernel_base;
608     hwaddr kernel_size;
609     Notifier notifier;
610 } DeviceTreeParams;
611 
612 static void ppce500_reset_device_tree(void *opaque)
613 {
614     DeviceTreeParams *p = opaque;
615     ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
616                              p->initrd_size, p->kernel_base, p->kernel_size,
617                              false);
618 }
619 
620 static void ppce500_init_notify(Notifier *notifier, void *data)
621 {
622     DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
623     ppce500_reset_device_tree(p);
624 }
625 
626 static int ppce500_prep_device_tree(PPCE500MachineState *machine,
627                                     hwaddr addr,
628                                     hwaddr initrd_base,
629                                     hwaddr initrd_size,
630                                     hwaddr kernel_base,
631                                     hwaddr kernel_size)
632 {
633     DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
634     p->machine = machine;
635     p->addr = addr;
636     p->initrd_base = initrd_base;
637     p->initrd_size = initrd_size;
638     p->kernel_base = kernel_base;
639     p->kernel_size = kernel_size;
640 
641     qemu_register_reset(ppce500_reset_device_tree, p);
642     p->notifier.notify = ppce500_init_notify;
643     qemu_add_machine_init_done_notifier(&p->notifier);
644 
645     /* Issue the device tree loader once, so that we get the size of the blob */
646     return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
647                                     kernel_base, kernel_size, true);
648 }
649 
650 /* Create -kernel TLB entries for BookE.  */
651 hwaddr booke206_page_size_to_tlb(uint64_t size)
652 {
653     return 63 - clz64(size / KiB);
654 }
655 
656 static int booke206_initial_map_tsize(CPUPPCState *env)
657 {
658     struct boot_info *bi = env->load_info;
659     hwaddr dt_end;
660     int ps;
661 
662     /* Our initial TLB entry needs to cover everything from 0 to
663        the device tree top */
664     dt_end = bi->dt_base + bi->dt_size;
665     ps = booke206_page_size_to_tlb(dt_end) + 1;
666     if (ps & 1) {
667         /* e500v2 can only do even TLB size bits */
668         ps++;
669     }
670     return ps;
671 }
672 
673 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
674 {
675     int tsize;
676 
677     tsize = booke206_initial_map_tsize(env);
678     return (1ULL << 10 << tsize);
679 }
680 
681 static void mmubooke_create_initial_mapping(CPUPPCState *env)
682 {
683     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
684     hwaddr size;
685     int ps;
686 
687     ps = booke206_initial_map_tsize(env);
688     size = (ps << MAS1_TSIZE_SHIFT);
689     tlb->mas1 = MAS1_VALID | size;
690     tlb->mas2 = 0;
691     tlb->mas7_3 = 0;
692     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
693 
694     env->tlb_dirty = true;
695 }
696 
697 static void ppce500_cpu_reset_sec(void *opaque)
698 {
699     PowerPCCPU *cpu = opaque;
700     CPUState *cs = CPU(cpu);
701 
702     cpu_reset(cs);
703 
704     /* Secondary CPU starts in halted state for now. Needs to change when
705        implementing non-kernel boot. */
706     cs->halted = 1;
707     cs->exception_index = EXCP_HLT;
708 }
709 
710 static void ppce500_cpu_reset(void *opaque)
711 {
712     PowerPCCPU *cpu = opaque;
713     CPUState *cs = CPU(cpu);
714     CPUPPCState *env = &cpu->env;
715     struct boot_info *bi = env->load_info;
716 
717     cpu_reset(cs);
718 
719     /* Set initial guest state. */
720     cs->halted = 0;
721     env->gpr[1] = (16 * MiB) - 8;
722     env->gpr[3] = bi->dt_base;
723     env->gpr[4] = 0;
724     env->gpr[5] = 0;
725     env->gpr[6] = EPAPR_MAGIC;
726     env->gpr[7] = mmubooke_initial_mapsize(env);
727     env->gpr[8] = 0;
728     env->gpr[9] = 0;
729     env->nip = bi->entry;
730     mmubooke_create_initial_mapping(env);
731 }
732 
733 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
734                                            IrqLines  *irqs)
735 {
736     DeviceState *dev;
737     SysBusDevice *s;
738     int i, j, k;
739     MachineState *machine = MACHINE(pms);
740     unsigned int smp_cpus = machine->smp.cpus;
741     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
742 
743     dev = qdev_create(NULL, TYPE_OPENPIC);
744     object_property_add_child(OBJECT(machine), "pic", OBJECT(dev),
745                               &error_fatal);
746     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
747     qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
748 
749     qdev_init_nofail(dev);
750     s = SYS_BUS_DEVICE(dev);
751 
752     k = 0;
753     for (i = 0; i < smp_cpus; i++) {
754         for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
755             sysbus_connect_irq(s, k++, irqs[i].irq[j]);
756         }
757     }
758 
759     return dev;
760 }
761 
762 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
763                                           IrqLines *irqs, Error **errp)
764 {
765     Error *err = NULL;
766     DeviceState *dev;
767     CPUState *cs;
768 
769     dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
770     qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
771 
772     object_property_set_bool(OBJECT(dev), true, "realized", &err);
773     if (err) {
774         error_propagate(errp, err);
775         object_unparent(OBJECT(dev));
776         return NULL;
777     }
778 
779     CPU_FOREACH(cs) {
780         if (kvm_openpic_connect_vcpu(dev, cs)) {
781             fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
782                     __func__);
783             abort();
784         }
785     }
786 
787     return dev;
788 }
789 
790 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
791                                       MemoryRegion *ccsr,
792                                       IrqLines *irqs)
793 {
794     MachineState *machine = MACHINE(pms);
795     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
796     DeviceState *dev = NULL;
797     SysBusDevice *s;
798 
799     if (kvm_enabled()) {
800         Error *err = NULL;
801 
802         if (machine_kernel_irqchip_allowed(machine)) {
803             dev = ppce500_init_mpic_kvm(pmc, irqs, &err);
804         }
805         if (machine_kernel_irqchip_required(machine) && !dev) {
806             error_reportf_err(err,
807                               "kernel_irqchip requested but unavailable: ");
808             exit(1);
809         }
810     }
811 
812     if (!dev) {
813         dev = ppce500_init_mpic_qemu(pms, irqs);
814     }
815 
816     s = SYS_BUS_DEVICE(dev);
817     memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
818                                 s->mmio[0].memory);
819 
820     return dev;
821 }
822 
823 static void ppce500_power_off(void *opaque, int line, int on)
824 {
825     if (on) {
826         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
827     }
828 }
829 
830 void ppce500_init(MachineState *machine)
831 {
832     MemoryRegion *address_space_mem = get_system_memory();
833     MemoryRegion *ram = g_new(MemoryRegion, 1);
834     PPCE500MachineState *pms = PPCE500_MACHINE(machine);
835     const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
836     PCIBus *pci_bus;
837     CPUPPCState *env = NULL;
838     uint64_t loadaddr;
839     hwaddr kernel_base = -1LL;
840     int kernel_size = 0;
841     hwaddr dt_base = 0;
842     hwaddr initrd_base = 0;
843     int initrd_size = 0;
844     hwaddr cur_base = 0;
845     char *filename;
846     const char *payload_name;
847     bool kernel_as_payload;
848     hwaddr bios_entry = 0;
849     target_long payload_size;
850     struct boot_info *boot_info;
851     int dt_size;
852     int i;
853     unsigned int smp_cpus = machine->smp.cpus;
854     /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
855      * 4 respectively */
856     unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
857     IrqLines *irqs;
858     DeviceState *dev, *mpicdev;
859     CPUPPCState *firstenv = NULL;
860     MemoryRegion *ccsr_addr_space;
861     SysBusDevice *s;
862     PPCE500CCSRState *ccsr;
863     I2CBus *i2c;
864 
865     irqs = g_new0(IrqLines, smp_cpus);
866     for (i = 0; i < smp_cpus; i++) {
867         PowerPCCPU *cpu;
868         CPUState *cs;
869         qemu_irq *input;
870 
871         cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
872         env = &cpu->env;
873         cs = CPU(cpu);
874 
875         if (env->mmu_model != POWERPC_MMU_BOOKE206) {
876             error_report("MMU model %i not supported by this machine",
877                          env->mmu_model);
878             exit(1);
879         }
880 
881         if (!firstenv) {
882             firstenv = env;
883         }
884 
885         input = (qemu_irq *)env->irq_inputs;
886         irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
887         irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
888         env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
889         env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
890 
891         ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
892 
893         /* Register reset handler */
894         if (!i) {
895             /* Primary CPU */
896             struct boot_info *boot_info;
897             boot_info = g_malloc0(sizeof(struct boot_info));
898             qemu_register_reset(ppce500_cpu_reset, cpu);
899             env->load_info = boot_info;
900         } else {
901             /* Secondary CPUs */
902             qemu_register_reset(ppce500_cpu_reset_sec, cpu);
903         }
904     }
905 
906     env = firstenv;
907 
908     /* Fixup Memory size on a alignment boundary */
909     ram_size &= ~(RAM_SIZES_ALIGN - 1);
910     machine->ram_size = ram_size;
911 
912     /* Register Memory */
913     memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
914     memory_region_add_subregion(address_space_mem, 0, ram);
915 
916     dev = qdev_create(NULL, "e500-ccsr");
917     object_property_add_child(qdev_get_machine(), "e500-ccsr",
918                               OBJECT(dev), NULL);
919     qdev_init_nofail(dev);
920     ccsr = CCSR(dev);
921     ccsr_addr_space = &ccsr->ccsr_space;
922     memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
923                                 ccsr_addr_space);
924 
925     mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
926 
927     /* Serial */
928     if (serial_hd(0)) {
929         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
930                        0, qdev_get_gpio_in(mpicdev, 42), 399193,
931                        serial_hd(0), DEVICE_BIG_ENDIAN);
932     }
933 
934     if (serial_hd(1)) {
935         serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
936                        0, qdev_get_gpio_in(mpicdev, 42), 399193,
937                        serial_hd(1), DEVICE_BIG_ENDIAN);
938     }
939         /* I2C */
940     dev = qdev_create(NULL, "mpc-i2c");
941     s = SYS_BUS_DEVICE(dev);
942     qdev_init_nofail(dev);
943     sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
944     memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
945                                 sysbus_mmio_get_region(s, 0));
946     i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c");
947     i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET);
948 
949 
950     /* General Utility device */
951     dev = qdev_create(NULL, "mpc8544-guts");
952     qdev_init_nofail(dev);
953     s = SYS_BUS_DEVICE(dev);
954     memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
955                                 sysbus_mmio_get_region(s, 0));
956 
957     /* PCI */
958     dev = qdev_create(NULL, "e500-pcihost");
959     object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev),
960                               &error_abort);
961     qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
962     qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
963     qdev_init_nofail(dev);
964     s = SYS_BUS_DEVICE(dev);
965     for (i = 0; i < PCI_NUM_PINS; i++) {
966         sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
967     }
968 
969     memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
970                                 sysbus_mmio_get_region(s, 0));
971 
972     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
973     if (!pci_bus)
974         printf("couldn't create PCI controller!\n");
975 
976     if (pci_bus) {
977         /* Register network interfaces. */
978         for (i = 0; i < nb_nics; i++) {
979             pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL);
980         }
981     }
982 
983     /* Register spinning region */
984     sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
985 
986     if (pmc->has_mpc8xxx_gpio) {
987         qemu_irq poweroff_irq;
988 
989         dev = qdev_create(NULL, "mpc8xxx_gpio");
990         s = SYS_BUS_DEVICE(dev);
991         qdev_init_nofail(dev);
992         sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
993         memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
994                                     sysbus_mmio_get_region(s, 0));
995 
996         /* Power Off GPIO at Pin 0 */
997         poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
998         qdev_connect_gpio_out(dev, 0, poweroff_irq);
999     }
1000 
1001     /* Platform Bus Device */
1002     if (pmc->has_platform_bus) {
1003         dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1004         dev->id = TYPE_PLATFORM_BUS_DEVICE;
1005         qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1006         qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
1007         qdev_init_nofail(dev);
1008         pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
1009 
1010         s = SYS_BUS_DEVICE(pms->pbus_dev);
1011         for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1012             int irqn = pmc->platform_bus_first_irq + i;
1013             sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
1014         }
1015 
1016         memory_region_add_subregion(address_space_mem,
1017                                     pmc->platform_bus_base,
1018                                     sysbus_mmio_get_region(s, 0));
1019     }
1020 
1021     /*
1022      * Smart firmware defaults ahead!
1023      *
1024      * We follow the following table to select which payload we execute.
1025      *
1026      *  -kernel | -bios | payload
1027      * ---------+-------+---------
1028      *     N    |   Y   | u-boot
1029      *     N    |   N   | u-boot
1030      *     Y    |   Y   | u-boot
1031      *     Y    |   N   | kernel
1032      *
1033      * This ensures backwards compatibility with how we used to expose
1034      * -kernel to users but allows them to run through u-boot as well.
1035      */
1036     kernel_as_payload = false;
1037     if (bios_name == NULL) {
1038         if (machine->kernel_filename) {
1039             payload_name = machine->kernel_filename;
1040             kernel_as_payload = true;
1041         } else {
1042             payload_name = "u-boot.e500";
1043         }
1044     } else {
1045         payload_name = bios_name;
1046     }
1047 
1048     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
1049 
1050     payload_size = load_elf(filename, NULL, NULL, NULL,
1051                             &bios_entry, &loadaddr, NULL,
1052                             1, PPC_ELF_MACHINE, 0, 0);
1053     if (payload_size < 0) {
1054         /*
1055          * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1056          * ePAPR compliant kernel
1057          */
1058         loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
1059         payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1060                                    NULL, NULL);
1061         if (payload_size < 0) {
1062             error_report("could not load firmware '%s'", filename);
1063             exit(1);
1064         }
1065     }
1066 
1067     g_free(filename);
1068 
1069     if (kernel_as_payload) {
1070         kernel_base = loadaddr;
1071         kernel_size = payload_size;
1072     }
1073 
1074     cur_base = loadaddr + payload_size;
1075     if (cur_base < 32 * MiB) {
1076         /* u-boot occupies memory up to 32MB, so load blobs above */
1077         cur_base = 32 * MiB;
1078     }
1079 
1080     /* Load bare kernel only if no bios/u-boot has been provided */
1081     if (machine->kernel_filename && !kernel_as_payload) {
1082         kernel_base = cur_base;
1083         kernel_size = load_image_targphys(machine->kernel_filename,
1084                                           cur_base,
1085                                           ram_size - cur_base);
1086         if (kernel_size < 0) {
1087             error_report("could not load kernel '%s'",
1088                          machine->kernel_filename);
1089             exit(1);
1090         }
1091 
1092         cur_base += kernel_size;
1093     }
1094 
1095     /* Load initrd. */
1096     if (machine->initrd_filename) {
1097         initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1098         initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1099                                           ram_size - initrd_base);
1100 
1101         if (initrd_size < 0) {
1102             error_report("could not load initial ram disk '%s'",
1103                          machine->initrd_filename);
1104             exit(1);
1105         }
1106 
1107         cur_base = initrd_base + initrd_size;
1108     }
1109 
1110     /*
1111      * Reserve space for dtb behind the kernel image because Linux has a bug
1112      * where it can only handle the dtb if it's within the first 64MB of where
1113      * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1114      * ensures enough space between kernel and initrd.
1115      */
1116     dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1117     if (dt_base + DTB_MAX_SIZE > ram_size) {
1118             error_report("not enough memory for device tree");
1119             exit(1);
1120     }
1121 
1122     dt_size = ppce500_prep_device_tree(pms, dt_base,
1123                                        initrd_base, initrd_size,
1124                                        kernel_base, kernel_size);
1125     if (dt_size < 0) {
1126         error_report("couldn't load device tree");
1127         exit(1);
1128     }
1129     assert(dt_size < DTB_MAX_SIZE);
1130 
1131     boot_info = env->load_info;
1132     boot_info->entry = bios_entry;
1133     boot_info->dt_base = dt_base;
1134     boot_info->dt_size = dt_size;
1135 }
1136 
1137 static void e500_ccsr_initfn(Object *obj)
1138 {
1139     PPCE500CCSRState *ccsr = CCSR(obj);
1140     memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1141                        MPC8544_CCSRBAR_SIZE);
1142 }
1143 
1144 static const TypeInfo e500_ccsr_info = {
1145     .name          = TYPE_CCSR,
1146     .parent        = TYPE_SYS_BUS_DEVICE,
1147     .instance_size = sizeof(PPCE500CCSRState),
1148     .instance_init = e500_ccsr_initfn,
1149 };
1150 
1151 static const TypeInfo ppce500_info = {
1152     .name          = TYPE_PPCE500_MACHINE,
1153     .parent        = TYPE_MACHINE,
1154     .abstract      = true,
1155     .instance_size = sizeof(PPCE500MachineState),
1156     .class_size    = sizeof(PPCE500MachineClass),
1157 };
1158 
1159 static void e500_register_types(void)
1160 {
1161     type_register_static(&e500_ccsr_info);
1162     type_register_static(&ppce500_info);
1163 }
1164 
1165 type_init(e500_register_types)
1166