1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "hw/sysbus.h" 36 #include "exec/address-spaces.h" 37 #include "qemu/host-utils.h" 38 #include "hw/pci-host/ppce500.h" 39 #include "qemu/error-report.h" 40 #include "hw/platform-bus.h" 41 #include "hw/net/fsl_etsec/etsec.h" 42 43 #define EPAPR_MAGIC (0x45504150) 44 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 45 #define DTC_LOAD_PAD 0x1800000 46 #define DTC_PAD_MASK 0xFFFFF 47 #define DTB_MAX_SIZE (8 * 1024 * 1024) 48 #define INITRD_LOAD_PAD 0x2000000 49 #define INITRD_PAD_MASK 0xFFFFFF 50 51 #define RAM_SIZES_ALIGN (64UL << 20) 52 53 /* TODO: parameterize */ 54 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 55 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 56 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 57 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 58 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 59 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 60 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 61 #define MPC8544_UTIL_OFFSET 0xe0000ULL 62 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 63 #define MPC8XXX_GPIO_IRQ 47 64 65 struct boot_info 66 { 67 uint32_t dt_base; 68 uint32_t dt_size; 69 uint32_t entry; 70 }; 71 72 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 73 int nr_slots, int *len) 74 { 75 int i = 0; 76 int slot; 77 int pci_irq; 78 int host_irq; 79 int last_slot = first_slot + nr_slots; 80 uint32_t *pci_map; 81 82 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 83 pci_map = g_malloc(*len); 84 85 for (slot = first_slot; slot < last_slot; slot++) { 86 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 87 pci_map[i++] = cpu_to_be32(slot << 11); 88 pci_map[i++] = cpu_to_be32(0x0); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(pci_irq + 1); 91 pci_map[i++] = cpu_to_be32(mpic); 92 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 93 pci_map[i++] = cpu_to_be32(host_irq + 1); 94 pci_map[i++] = cpu_to_be32(0x1); 95 } 96 } 97 98 assert((i * sizeof(uint32_t)) == *len); 99 100 return pci_map; 101 } 102 103 static void dt_serial_create(void *fdt, unsigned long long offset, 104 const char *soc, const char *mpic, 105 const char *alias, int idx, bool defcon) 106 { 107 char ser[128]; 108 109 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 110 qemu_fdt_add_subnode(fdt, ser); 111 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 112 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 113 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 114 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 115 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 116 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 117 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 118 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 119 120 if (defcon) { 121 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 122 } 123 } 124 125 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 126 { 127 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 128 int irq0 = MPC8XXX_GPIO_IRQ; 129 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 130 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 131 int gpio_ph; 132 133 qemu_fdt_add_subnode(fdt, node); 134 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 135 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 136 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 137 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 138 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 139 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 140 gpio_ph = qemu_fdt_alloc_phandle(fdt); 141 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 142 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 143 144 /* Power Off Pin */ 145 qemu_fdt_add_subnode(fdt, poweroff); 146 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 147 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 148 149 g_free(node); 150 g_free(poweroff); 151 } 152 153 typedef struct PlatformDevtreeData { 154 void *fdt; 155 const char *mpic; 156 int irq_start; 157 const char *node; 158 PlatformBusDevice *pbus; 159 } PlatformDevtreeData; 160 161 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 162 { 163 eTSEC *etsec = ETSEC_COMMON(sbdev); 164 PlatformBusDevice *pbus = data->pbus; 165 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 166 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 167 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 168 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 169 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 170 gchar *group = g_strdup_printf("%s/queue-group", node); 171 void *fdt = data->fdt; 172 173 assert((int64_t)mmio0 >= 0); 174 assert(irq0 >= 0); 175 assert(irq1 >= 0); 176 assert(irq2 >= 0); 177 178 qemu_fdt_add_subnode(fdt, node); 179 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 180 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 181 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 182 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 183 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 184 185 qemu_fdt_add_subnode(fdt, group); 186 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 187 qemu_fdt_setprop_cells(fdt, group, "interrupts", 188 data->irq_start + irq0, 0x2, 189 data->irq_start + irq1, 0x2, 190 data->irq_start + irq2, 0x2); 191 192 g_free(node); 193 g_free(group); 194 195 return 0; 196 } 197 198 static int sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 199 { 200 PlatformDevtreeData *data = opaque; 201 bool matched = false; 202 203 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 204 create_devtree_etsec(sbdev, data); 205 matched = true; 206 } 207 208 if (!matched) { 209 error_report("Device %s is not supported by this machine yet.", 210 qdev_fw_name(DEVICE(sbdev))); 211 exit(1); 212 } 213 214 return 0; 215 } 216 217 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, 218 const char *mpic) 219 { 220 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); 221 const char platcomp[] = "qemu,platform\0simple-bus"; 222 uint64_t addr = params->platform_bus_base; 223 uint64_t size = params->platform_bus_size; 224 int irq_start = params->platform_bus_first_irq; 225 PlatformBusDevice *pbus; 226 DeviceState *dev; 227 228 /* Create a /platform node that we can put all devices into */ 229 230 qemu_fdt_add_subnode(fdt, node); 231 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 232 233 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 234 address and size */ 235 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 236 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 237 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 238 239 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 240 241 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); 242 pbus = PLATFORM_BUS_DEVICE(dev); 243 244 /* We can only create dt nodes for dynamic devices when they're ready */ 245 if (pbus->done_gathering) { 246 PlatformDevtreeData data = { 247 .fdt = fdt, 248 .mpic = mpic, 249 .irq_start = irq_start, 250 .node = node, 251 .pbus = pbus, 252 }; 253 254 /* Loop through all dynamic sysbus devices and create nodes for them */ 255 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 256 } 257 258 g_free(node); 259 } 260 261 static int ppce500_load_device_tree(MachineState *machine, 262 PPCE500Params *params, 263 hwaddr addr, 264 hwaddr initrd_base, 265 hwaddr initrd_size, 266 hwaddr kernel_base, 267 hwaddr kernel_size, 268 bool dry_run) 269 { 270 CPUPPCState *env = first_cpu->env_ptr; 271 int ret = -1; 272 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 273 int fdt_size; 274 void *fdt; 275 uint8_t hypercall[16]; 276 uint32_t clock_freq = 400000000; 277 uint32_t tb_freq = 400000000; 278 int i; 279 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 280 char soc[128]; 281 char mpic[128]; 282 uint32_t mpic_ph; 283 uint32_t msi_ph; 284 char gutil[128]; 285 char pci[128]; 286 char msi[128]; 287 uint32_t *pci_map = NULL; 288 int len; 289 uint32_t pci_ranges[14] = 290 { 291 0x2000000, 0x0, params->pci_mmio_bus_base, 292 params->pci_mmio_base >> 32, params->pci_mmio_base, 293 0x0, 0x20000000, 294 295 0x1000000, 0x0, 0x0, 296 params->pci_pio_base >> 32, params->pci_pio_base, 297 0x0, 0x10000, 298 }; 299 QemuOpts *machine_opts = qemu_get_machine_opts(); 300 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 301 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 302 303 if (dtb_file) { 304 char *filename; 305 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 306 if (!filename) { 307 goto out; 308 } 309 310 fdt = load_device_tree(filename, &fdt_size); 311 g_free(filename); 312 if (!fdt) { 313 goto out; 314 } 315 goto done; 316 } 317 318 fdt = create_device_tree(&fdt_size); 319 if (fdt == NULL) { 320 goto out; 321 } 322 323 /* Manipulate device tree in memory. */ 324 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 325 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 326 327 qemu_fdt_add_subnode(fdt, "/memory"); 328 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 329 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 330 sizeof(mem_reg_property)); 331 332 qemu_fdt_add_subnode(fdt, "/chosen"); 333 if (initrd_size) { 334 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 335 initrd_base); 336 if (ret < 0) { 337 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 338 } 339 340 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 341 (initrd_base + initrd_size)); 342 if (ret < 0) { 343 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 344 } 345 346 } 347 348 if (kernel_base != -1ULL) { 349 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 350 kernel_base >> 32, kernel_base, 351 kernel_size >> 32, kernel_size); 352 } 353 354 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 355 machine->kernel_cmdline); 356 if (ret < 0) 357 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 358 359 if (kvm_enabled()) { 360 /* Read out host's frequencies */ 361 clock_freq = kvmppc_get_clockfreq(); 362 tb_freq = kvmppc_get_tbfreq(); 363 364 /* indicate KVM hypercall interface */ 365 qemu_fdt_add_subnode(fdt, "/hypervisor"); 366 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 367 "linux,kvm"); 368 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 369 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 370 hypercall, sizeof(hypercall)); 371 /* if KVM supports the idle hcall, set property indicating this */ 372 if (kvmppc_get_hasidle(env)) { 373 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 374 } 375 } 376 377 /* Create CPU nodes */ 378 qemu_fdt_add_subnode(fdt, "/cpus"); 379 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 380 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 381 382 /* We need to generate the cpu nodes in reverse order, so Linux can pick 383 the first node as boot node and be happy */ 384 for (i = smp_cpus - 1; i >= 0; i--) { 385 CPUState *cpu; 386 PowerPCCPU *pcpu; 387 char cpu_name[128]; 388 uint64_t cpu_release_addr = params->spin_base + (i * 0x20); 389 390 cpu = qemu_get_cpu(i); 391 if (cpu == NULL) { 392 continue; 393 } 394 env = cpu->env_ptr; 395 pcpu = POWERPC_CPU(cpu); 396 397 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 398 ppc_get_vcpu_dt_id(pcpu)); 399 qemu_fdt_add_subnode(fdt, cpu_name); 400 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 401 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 402 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 403 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 404 ppc_get_vcpu_dt_id(pcpu)); 405 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 406 env->dcache_line_size); 407 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 408 env->icache_line_size); 409 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 410 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 411 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 412 if (cpu->cpu_index) { 413 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 414 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 415 "spin-table"); 416 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 417 cpu_release_addr); 418 } else { 419 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 420 } 421 } 422 423 qemu_fdt_add_subnode(fdt, "/aliases"); 424 /* XXX These should go into their respective devices' code */ 425 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); 426 qemu_fdt_add_subnode(fdt, soc); 427 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 428 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 429 sizeof(compatible_sb)); 430 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 431 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 432 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 433 params->ccsrbar_base >> 32, params->ccsrbar_base, 434 MPC8544_CCSRBAR_SIZE); 435 /* XXX should contain a reasonable value */ 436 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 437 438 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 439 qemu_fdt_add_subnode(fdt, mpic); 440 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 441 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 442 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 443 0x40000); 444 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 445 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 446 mpic_ph = qemu_fdt_alloc_phandle(fdt); 447 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 448 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 449 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 450 451 /* 452 * We have to generate ser1 first, because Linux takes the first 453 * device it finds in the dt as serial output device. And we generate 454 * devices in reverse order to the dt. 455 */ 456 if (serial_hds[1]) { 457 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 458 soc, mpic, "serial1", 1, false); 459 } 460 461 if (serial_hds[0]) { 462 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 463 soc, mpic, "serial0", 0, true); 464 } 465 466 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 467 MPC8544_UTIL_OFFSET); 468 qemu_fdt_add_subnode(fdt, gutil); 469 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 470 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 471 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 472 473 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 474 qemu_fdt_add_subnode(fdt, msi); 475 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 476 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 477 msi_ph = qemu_fdt_alloc_phandle(fdt); 478 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 479 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 480 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 481 0xe0, 0x0, 482 0xe1, 0x0, 483 0xe2, 0x0, 484 0xe3, 0x0, 485 0xe4, 0x0, 486 0xe5, 0x0, 487 0xe6, 0x0, 488 0xe7, 0x0); 489 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 490 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 491 492 snprintf(pci, sizeof(pci), "/pci@%llx", 493 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 494 qemu_fdt_add_subnode(fdt, pci); 495 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 496 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 497 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 498 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 499 0x0, 0x7); 500 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 501 params->pci_first_slot, params->pci_nr_slots, 502 &len); 503 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 504 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 505 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 506 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 507 for (i = 0; i < 14; i++) { 508 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 509 } 510 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 511 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 512 qemu_fdt_setprop_cells(fdt, pci, "reg", 513 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 514 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 515 0, 0x1000); 516 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 517 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 518 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 519 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 520 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 521 522 if (params->has_mpc8xxx_gpio) { 523 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 524 } 525 526 if (params->has_platform_bus) { 527 platform_bus_create_devtree(params, fdt, mpic); 528 } 529 530 params->fixup_devtree(params, fdt); 531 532 if (toplevel_compat) { 533 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 534 strlen(toplevel_compat) + 1); 535 } 536 537 done: 538 if (!dry_run) { 539 qemu_fdt_dumpdtb(fdt, fdt_size); 540 cpu_physical_memory_write(addr, fdt, fdt_size); 541 } 542 ret = fdt_size; 543 544 out: 545 g_free(pci_map); 546 547 return ret; 548 } 549 550 typedef struct DeviceTreeParams { 551 MachineState *machine; 552 PPCE500Params params; 553 hwaddr addr; 554 hwaddr initrd_base; 555 hwaddr initrd_size; 556 hwaddr kernel_base; 557 hwaddr kernel_size; 558 Notifier notifier; 559 } DeviceTreeParams; 560 561 static void ppce500_reset_device_tree(void *opaque) 562 { 563 DeviceTreeParams *p = opaque; 564 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base, 565 p->initrd_size, p->kernel_base, p->kernel_size, 566 false); 567 } 568 569 static void ppce500_init_notify(Notifier *notifier, void *data) 570 { 571 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 572 ppce500_reset_device_tree(p); 573 } 574 575 static int ppce500_prep_device_tree(MachineState *machine, 576 PPCE500Params *params, 577 hwaddr addr, 578 hwaddr initrd_base, 579 hwaddr initrd_size, 580 hwaddr kernel_base, 581 hwaddr kernel_size) 582 { 583 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 584 p->machine = machine; 585 p->params = *params; 586 p->addr = addr; 587 p->initrd_base = initrd_base; 588 p->initrd_size = initrd_size; 589 p->kernel_base = kernel_base; 590 p->kernel_size = kernel_size; 591 592 qemu_register_reset(ppce500_reset_device_tree, p); 593 p->notifier.notify = ppce500_init_notify; 594 qemu_add_machine_init_done_notifier(&p->notifier); 595 596 /* Issue the device tree loader once, so that we get the size of the blob */ 597 return ppce500_load_device_tree(machine, params, addr, initrd_base, 598 initrd_size, kernel_base, kernel_size, 599 true); 600 } 601 602 /* Create -kernel TLB entries for BookE. */ 603 static inline hwaddr booke206_page_size_to_tlb(uint64_t size) 604 { 605 return 63 - clz64(size >> 10); 606 } 607 608 static int booke206_initial_map_tsize(CPUPPCState *env) 609 { 610 struct boot_info *bi = env->load_info; 611 hwaddr dt_end; 612 int ps; 613 614 /* Our initial TLB entry needs to cover everything from 0 to 615 the device tree top */ 616 dt_end = bi->dt_base + bi->dt_size; 617 ps = booke206_page_size_to_tlb(dt_end) + 1; 618 if (ps & 1) { 619 /* e500v2 can only do even TLB size bits */ 620 ps++; 621 } 622 return ps; 623 } 624 625 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 626 { 627 int tsize; 628 629 tsize = booke206_initial_map_tsize(env); 630 return (1ULL << 10 << tsize); 631 } 632 633 static void mmubooke_create_initial_mapping(CPUPPCState *env) 634 { 635 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 636 hwaddr size; 637 int ps; 638 639 ps = booke206_initial_map_tsize(env); 640 size = (ps << MAS1_TSIZE_SHIFT); 641 tlb->mas1 = MAS1_VALID | size; 642 tlb->mas2 = 0; 643 tlb->mas7_3 = 0; 644 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 645 646 env->tlb_dirty = true; 647 } 648 649 static void ppce500_cpu_reset_sec(void *opaque) 650 { 651 PowerPCCPU *cpu = opaque; 652 CPUState *cs = CPU(cpu); 653 654 cpu_reset(cs); 655 656 /* Secondary CPU starts in halted state for now. Needs to change when 657 implementing non-kernel boot. */ 658 cs->halted = 1; 659 cs->exception_index = EXCP_HLT; 660 } 661 662 static void ppce500_cpu_reset(void *opaque) 663 { 664 PowerPCCPU *cpu = opaque; 665 CPUState *cs = CPU(cpu); 666 CPUPPCState *env = &cpu->env; 667 struct boot_info *bi = env->load_info; 668 669 cpu_reset(cs); 670 671 /* Set initial guest state. */ 672 cs->halted = 0; 673 env->gpr[1] = (16<<20) - 8; 674 env->gpr[3] = bi->dt_base; 675 env->gpr[4] = 0; 676 env->gpr[5] = 0; 677 env->gpr[6] = EPAPR_MAGIC; 678 env->gpr[7] = mmubooke_initial_mapsize(env); 679 env->gpr[8] = 0; 680 env->gpr[9] = 0; 681 env->nip = bi->entry; 682 mmubooke_create_initial_mapping(env); 683 } 684 685 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 686 qemu_irq **irqs) 687 { 688 DeviceState *dev; 689 SysBusDevice *s; 690 int i, j, k; 691 692 dev = qdev_create(NULL, TYPE_OPENPIC); 693 qdev_prop_set_uint32(dev, "model", params->mpic_version); 694 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 695 696 qdev_init_nofail(dev); 697 s = SYS_BUS_DEVICE(dev); 698 699 k = 0; 700 for (i = 0; i < smp_cpus; i++) { 701 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 702 sysbus_connect_irq(s, k++, irqs[i][j]); 703 } 704 } 705 706 return dev; 707 } 708 709 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 710 qemu_irq **irqs, Error **errp) 711 { 712 Error *err = NULL; 713 DeviceState *dev; 714 CPUState *cs; 715 716 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 717 qdev_prop_set_uint32(dev, "model", params->mpic_version); 718 719 object_property_set_bool(OBJECT(dev), true, "realized", &err); 720 if (err) { 721 error_propagate(errp, err); 722 object_unparent(OBJECT(dev)); 723 return NULL; 724 } 725 726 CPU_FOREACH(cs) { 727 if (kvm_openpic_connect_vcpu(dev, cs)) { 728 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 729 __func__); 730 abort(); 731 } 732 } 733 734 return dev; 735 } 736 737 static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params, 738 MemoryRegion *ccsr, qemu_irq **irqs) 739 { 740 qemu_irq *mpic; 741 DeviceState *dev = NULL; 742 SysBusDevice *s; 743 int i; 744 745 mpic = g_new0(qemu_irq, 256); 746 747 if (kvm_enabled()) { 748 Error *err = NULL; 749 750 if (machine_kernel_irqchip_allowed(machine)) { 751 dev = ppce500_init_mpic_kvm(params, irqs, &err); 752 } 753 if (machine_kernel_irqchip_required(machine) && !dev) { 754 error_report("kernel_irqchip requested but unavailable: %s", 755 error_get_pretty(err)); 756 exit(1); 757 } 758 } 759 760 if (!dev) { 761 dev = ppce500_init_mpic_qemu(params, irqs); 762 } 763 764 for (i = 0; i < 256; i++) { 765 mpic[i] = qdev_get_gpio_in(dev, i); 766 } 767 768 s = SYS_BUS_DEVICE(dev); 769 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 770 s->mmio[0].memory); 771 772 return mpic; 773 } 774 775 static void ppce500_power_off(void *opaque, int line, int on) 776 { 777 if (on) { 778 qemu_system_shutdown_request(); 779 } 780 } 781 782 void ppce500_init(MachineState *machine, PPCE500Params *params) 783 { 784 MemoryRegion *address_space_mem = get_system_memory(); 785 MemoryRegion *ram = g_new(MemoryRegion, 1); 786 PCIBus *pci_bus; 787 CPUPPCState *env = NULL; 788 uint64_t loadaddr; 789 hwaddr kernel_base = -1LL; 790 int kernel_size = 0; 791 hwaddr dt_base = 0; 792 hwaddr initrd_base = 0; 793 int initrd_size = 0; 794 hwaddr cur_base = 0; 795 char *filename; 796 hwaddr bios_entry = 0; 797 target_long bios_size; 798 struct boot_info *boot_info; 799 int dt_size; 800 int i; 801 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 802 * 4 respectively */ 803 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 804 qemu_irq **irqs, *mpic; 805 DeviceState *dev; 806 CPUPPCState *firstenv = NULL; 807 MemoryRegion *ccsr_addr_space; 808 SysBusDevice *s; 809 PPCE500CCSRState *ccsr; 810 811 /* Setup CPUs */ 812 if (machine->cpu_model == NULL) { 813 machine->cpu_model = "e500v2_v30"; 814 } 815 816 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 817 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 818 for (i = 0; i < smp_cpus; i++) { 819 PowerPCCPU *cpu; 820 CPUState *cs; 821 qemu_irq *input; 822 823 cpu = cpu_ppc_init(machine->cpu_model); 824 if (cpu == NULL) { 825 fprintf(stderr, "Unable to initialize CPU!\n"); 826 exit(1); 827 } 828 env = &cpu->env; 829 cs = CPU(cpu); 830 831 if (!firstenv) { 832 firstenv = env; 833 } 834 835 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 836 input = (qemu_irq *)env->irq_inputs; 837 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 838 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 839 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 840 env->mpic_iack = params->ccsrbar_base + 841 MPC8544_MPIC_REGS_OFFSET + 0xa0; 842 843 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 844 845 /* Register reset handler */ 846 if (!i) { 847 /* Primary CPU */ 848 struct boot_info *boot_info; 849 boot_info = g_malloc0(sizeof(struct boot_info)); 850 qemu_register_reset(ppce500_cpu_reset, cpu); 851 env->load_info = boot_info; 852 } else { 853 /* Secondary CPUs */ 854 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 855 } 856 } 857 858 env = firstenv; 859 860 /* Fixup Memory size on a alignment boundary */ 861 ram_size &= ~(RAM_SIZES_ALIGN - 1); 862 machine->ram_size = ram_size; 863 864 /* Register Memory */ 865 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 866 memory_region_add_subregion(address_space_mem, 0, ram); 867 868 dev = qdev_create(NULL, "e500-ccsr"); 869 object_property_add_child(qdev_get_machine(), "e500-ccsr", 870 OBJECT(dev), NULL); 871 qdev_init_nofail(dev); 872 ccsr = CCSR(dev); 873 ccsr_addr_space = &ccsr->ccsr_space; 874 memory_region_add_subregion(address_space_mem, params->ccsrbar_base, 875 ccsr_addr_space); 876 877 mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); 878 879 /* Serial */ 880 if (serial_hds[0]) { 881 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 882 0, mpic[42], 399193, 883 serial_hds[0], DEVICE_BIG_ENDIAN); 884 } 885 886 if (serial_hds[1]) { 887 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 888 0, mpic[42], 399193, 889 serial_hds[1], DEVICE_BIG_ENDIAN); 890 } 891 892 /* General Utility device */ 893 dev = qdev_create(NULL, "mpc8544-guts"); 894 qdev_init_nofail(dev); 895 s = SYS_BUS_DEVICE(dev); 896 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 897 sysbus_mmio_get_region(s, 0)); 898 899 /* PCI */ 900 dev = qdev_create(NULL, "e500-pcihost"); 901 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 902 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 903 qdev_init_nofail(dev); 904 s = SYS_BUS_DEVICE(dev); 905 for (i = 0; i < PCI_NUM_PINS; i++) { 906 sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]); 907 } 908 909 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 910 sysbus_mmio_get_region(s, 0)); 911 912 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 913 if (!pci_bus) 914 printf("couldn't create PCI controller!\n"); 915 916 if (pci_bus) { 917 /* Register network interfaces. */ 918 for (i = 0; i < nb_nics; i++) { 919 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 920 } 921 } 922 923 /* Register spinning region */ 924 sysbus_create_simple("e500-spin", params->spin_base, NULL); 925 926 if (cur_base < (32 * 1024 * 1024)) { 927 /* u-boot occupies memory up to 32MB, so load blobs above */ 928 cur_base = (32 * 1024 * 1024); 929 } 930 931 if (params->has_mpc8xxx_gpio) { 932 qemu_irq poweroff_irq; 933 934 dev = qdev_create(NULL, "mpc8xxx_gpio"); 935 s = SYS_BUS_DEVICE(dev); 936 qdev_init_nofail(dev); 937 sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]); 938 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 939 sysbus_mmio_get_region(s, 0)); 940 941 /* Power Off GPIO at Pin 0 */ 942 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 943 qdev_connect_gpio_out(dev, 0, poweroff_irq); 944 } 945 946 /* Platform Bus Device */ 947 if (params->has_platform_bus) { 948 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 949 dev->id = TYPE_PLATFORM_BUS_DEVICE; 950 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs); 951 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size); 952 qdev_init_nofail(dev); 953 s = SYS_BUS_DEVICE(dev); 954 955 for (i = 0; i < params->platform_bus_num_irqs; i++) { 956 int irqn = params->platform_bus_first_irq + i; 957 sysbus_connect_irq(s, i, mpic[irqn]); 958 } 959 960 memory_region_add_subregion(address_space_mem, 961 params->platform_bus_base, 962 sysbus_mmio_get_region(s, 0)); 963 } 964 965 /* Load kernel. */ 966 if (machine->kernel_filename) { 967 kernel_base = cur_base; 968 kernel_size = load_image_targphys(machine->kernel_filename, 969 cur_base, 970 ram_size - cur_base); 971 if (kernel_size < 0) { 972 fprintf(stderr, "qemu: could not load kernel '%s'\n", 973 machine->kernel_filename); 974 exit(1); 975 } 976 977 cur_base += kernel_size; 978 } 979 980 /* Load initrd. */ 981 if (machine->initrd_filename) { 982 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 983 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 984 ram_size - initrd_base); 985 986 if (initrd_size < 0) { 987 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 988 machine->initrd_filename); 989 exit(1); 990 } 991 992 cur_base = initrd_base + initrd_size; 993 } 994 995 /* 996 * Smart firmware defaults ahead! 997 * 998 * We follow the following table to select which payload we execute. 999 * 1000 * -kernel | -bios | payload 1001 * ---------+-------+--------- 1002 * N | Y | u-boot 1003 * N | N | u-boot 1004 * Y | Y | u-boot 1005 * Y | N | kernel 1006 * 1007 * This ensures backwards compatibility with how we used to expose 1008 * -kernel to users but allows them to run through u-boot as well. 1009 */ 1010 if (bios_name == NULL) { 1011 if (machine->kernel_filename) { 1012 bios_name = machine->kernel_filename; 1013 } else { 1014 bios_name = "u-boot.e500"; 1015 } 1016 } 1017 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1018 1019 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 1020 1, PPC_ELF_MACHINE, 0); 1021 if (bios_size < 0) { 1022 /* 1023 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1024 * ePAPR compliant kernel 1025 */ 1026 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1027 NULL, NULL); 1028 if (kernel_size < 0) { 1029 fprintf(stderr, "qemu: could not load firmware '%s'\n", filename); 1030 exit(1); 1031 } 1032 } 1033 g_free(filename); 1034 1035 /* Reserve space for dtb */ 1036 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1037 1038 dt_size = ppce500_prep_device_tree(machine, params, dt_base, 1039 initrd_base, initrd_size, 1040 kernel_base, kernel_size); 1041 if (dt_size < 0) { 1042 fprintf(stderr, "couldn't load device tree\n"); 1043 exit(1); 1044 } 1045 assert(dt_size < DTB_MAX_SIZE); 1046 1047 boot_info = env->load_info; 1048 boot_info->entry = bios_entry; 1049 boot_info->dt_base = dt_base; 1050 boot_info->dt_size = dt_size; 1051 } 1052 1053 static int e500_ccsr_initfn(SysBusDevice *dev) 1054 { 1055 PPCE500CCSRState *ccsr; 1056 1057 ccsr = CCSR(dev); 1058 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 1059 MPC8544_CCSRBAR_SIZE); 1060 return 0; 1061 } 1062 1063 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 1064 { 1065 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1066 k->init = e500_ccsr_initfn; 1067 } 1068 1069 static const TypeInfo e500_ccsr_info = { 1070 .name = TYPE_CCSR, 1071 .parent = TYPE_SYS_BUS_DEVICE, 1072 .instance_size = sizeof(PPCE500CCSRState), 1073 .class_init = e500_ccsr_class_init, 1074 }; 1075 1076 static void e500_register_types(void) 1077 { 1078 type_register_static(&e500_ccsr_info); 1079 } 1080 1081 type_init(e500_register_types) 1082