1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu/datadir.h" 19 #include "qemu/units.h" 20 #include "qemu/guest-random.h" 21 #include "qapi/error.h" 22 #include "e500.h" 23 #include "e500-ccsr.h" 24 #include "net/net.h" 25 #include "qemu/config-file.h" 26 #include "hw/block/flash.h" 27 #include "hw/char/serial.h" 28 #include "hw/pci/pci.h" 29 #include "sysemu/block-backend-io.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/kvm.h" 32 #include "sysemu/reset.h" 33 #include "sysemu/runstate.h" 34 #include "kvm_ppc.h" 35 #include "sysemu/device_tree.h" 36 #include "hw/ppc/openpic.h" 37 #include "hw/ppc/openpic_kvm.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/qdev-properties.h" 40 #include "hw/loader.h" 41 #include "elf.h" 42 #include "hw/sysbus.h" 43 #include "qemu/host-utils.h" 44 #include "qemu/option.h" 45 #include "hw/pci-host/ppce500.h" 46 #include "qemu/error-report.h" 47 #include "hw/platform-bus.h" 48 #include "hw/net/fsl_etsec/etsec.h" 49 #include "hw/i2c/i2c.h" 50 #include "hw/irq.h" 51 #include "hw/sd/sdhci.h" 52 #include "hw/misc/unimp.h" 53 54 #define EPAPR_MAGIC (0x45504150) 55 #define DTC_LOAD_PAD 0x1800000 56 #define DTC_PAD_MASK 0xFFFFF 57 #define DTB_MAX_SIZE (8 * MiB) 58 #define INITRD_LOAD_PAD 0x2000000 59 #define INITRD_PAD_MASK 0xFFFFFF 60 61 #define RAM_SIZES_ALIGN (64 * MiB) 62 63 /* TODO: parameterize */ 64 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 65 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 66 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 67 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 68 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 69 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 70 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 71 #define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL 72 #define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL 73 #define MPC8544_UTIL_OFFSET 0xe0000ULL 74 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 75 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 76 #define MPC8XXX_GPIO_IRQ 47 77 #define MPC8544_I2C_IRQ 43 78 #define MPC85XX_ESDHC_IRQ 72 79 #define RTC_REGS_OFFSET 0x68 80 81 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 82 83 struct boot_info 84 { 85 uint32_t dt_base; 86 uint32_t dt_size; 87 uint32_t entry; 88 }; 89 90 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 91 int nr_slots, int *len) 92 { 93 int i = 0; 94 int slot; 95 int pci_irq; 96 int host_irq; 97 int last_slot = first_slot + nr_slots; 98 uint32_t *pci_map; 99 100 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 101 pci_map = g_malloc(*len); 102 103 for (slot = first_slot; slot < last_slot; slot++) { 104 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 105 pci_map[i++] = cpu_to_be32(slot << 11); 106 pci_map[i++] = cpu_to_be32(0x0); 107 pci_map[i++] = cpu_to_be32(0x0); 108 pci_map[i++] = cpu_to_be32(pci_irq + 1); 109 pci_map[i++] = cpu_to_be32(mpic); 110 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 111 pci_map[i++] = cpu_to_be32(host_irq + 1); 112 pci_map[i++] = cpu_to_be32(0x1); 113 } 114 } 115 116 assert((i * sizeof(uint32_t)) == *len); 117 118 return pci_map; 119 } 120 121 static void dt_serial_create(void *fdt, unsigned long long offset, 122 const char *soc, const char *mpic, 123 const char *alias, int idx, bool defcon) 124 { 125 char *ser; 126 127 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 128 qemu_fdt_add_subnode(fdt, ser); 129 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 130 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 131 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 132 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 133 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 134 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 135 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 136 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 137 138 if (defcon) { 139 /* 140 * "linux,stdout-path" and "stdout" properties are deprecated by linux 141 * kernel. New platforms should only use the "stdout-path" property. Set 142 * the new property and continue using older property to remain 143 * compatible with the existing firmware. 144 */ 145 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 146 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 147 } 148 g_free(ser); 149 } 150 151 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 152 { 153 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 154 int irq0 = MPC8XXX_GPIO_IRQ; 155 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 156 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 157 int gpio_ph; 158 159 qemu_fdt_add_subnode(fdt, node); 160 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 161 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 162 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 163 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 164 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 165 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 166 gpio_ph = qemu_fdt_alloc_phandle(fdt); 167 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 168 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 169 170 /* Power Off Pin */ 171 qemu_fdt_add_subnode(fdt, poweroff); 172 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 173 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 174 175 g_free(node); 176 g_free(poweroff); 177 } 178 179 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 180 { 181 int offset = RTC_REGS_OFFSET; 182 183 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 184 qemu_fdt_add_subnode(fdt, rtc); 185 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 186 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 187 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 188 189 g_free(rtc); 190 } 191 192 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 193 const char *alias) 194 { 195 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 196 int irq0 = MPC8544_I2C_IRQ; 197 198 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 199 qemu_fdt_add_subnode(fdt, i2c); 200 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 201 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 202 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 203 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 204 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 205 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 206 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 207 208 g_free(i2c); 209 } 210 211 static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic) 212 { 213 hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET; 214 hwaddr size = MPC85XX_ESDHC_REGS_SIZE; 215 int irq = MPC85XX_ESDHC_IRQ; 216 g_autofree char *name = NULL; 217 218 name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio); 219 qemu_fdt_add_subnode(fdt, name); 220 qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0); 221 qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic); 222 qemu_fdt_setprop_cells(fdt, name, "bus-width", 4); 223 qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2); 224 qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size); 225 qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc"); 226 } 227 228 typedef struct PlatformDevtreeData { 229 void *fdt; 230 const char *mpic; 231 int irq_start; 232 const char *node; 233 PlatformBusDevice *pbus; 234 } PlatformDevtreeData; 235 236 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 237 { 238 eTSEC *etsec = ETSEC_COMMON(sbdev); 239 PlatformBusDevice *pbus = data->pbus; 240 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 241 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 242 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 243 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 244 gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0); 245 gchar *group = g_strdup_printf("%s/queue-group", node); 246 void *fdt = data->fdt; 247 248 assert((int64_t)mmio0 >= 0); 249 assert(irq0 >= 0); 250 assert(irq1 >= 0); 251 assert(irq2 >= 0); 252 253 qemu_fdt_add_subnode(fdt, node); 254 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); 255 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 256 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 257 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 258 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 259 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 260 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 261 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 262 263 qemu_fdt_add_subnode(fdt, group); 264 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 265 qemu_fdt_setprop_cells(fdt, group, "interrupts", 266 data->irq_start + irq0, 0x2, 267 data->irq_start + irq1, 0x2, 268 data->irq_start + irq2, 0x2); 269 270 g_free(node); 271 g_free(group); 272 273 return 0; 274 } 275 276 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 277 { 278 PlatformDevtreeData *data = opaque; 279 bool matched = false; 280 281 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 282 create_devtree_etsec(sbdev, data); 283 matched = true; 284 } 285 286 if (!matched) { 287 error_report("Device %s is not supported by this machine yet.", 288 qdev_fw_name(DEVICE(sbdev))); 289 exit(1); 290 } 291 } 292 293 static void create_devtree_flash(SysBusDevice *sbdev, 294 PlatformDevtreeData *data) 295 { 296 g_autofree char *name = NULL; 297 uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev), 298 "num-blocks", 299 &error_fatal); 300 uint64_t sector_length = object_property_get_uint(OBJECT(sbdev), 301 "sector-length", 302 &error_fatal); 303 uint64_t bank_width = object_property_get_uint(OBJECT(sbdev), 304 "width", 305 &error_fatal); 306 hwaddr flashbase = 0; 307 hwaddr flashsize = num_blocks * sector_length; 308 void *fdt = data->fdt; 309 310 name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase); 311 qemu_fdt_add_subnode(fdt, name); 312 qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash"); 313 qemu_fdt_setprop_sized_cells(fdt, name, "reg", 314 1, flashbase, 1, flashsize); 315 qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width); 316 } 317 318 static void platform_bus_create_devtree(PPCE500MachineState *pms, 319 void *fdt, const char *mpic) 320 { 321 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 322 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 323 const char platcomp[] = "qemu,platform\0simple-bus"; 324 uint64_t addr = pmc->platform_bus_base; 325 uint64_t size = pmc->platform_bus_size; 326 int irq_start = pmc->platform_bus_first_irq; 327 SysBusDevice *sbdev; 328 bool ambiguous; 329 330 /* Create a /platform node that we can put all devices into */ 331 332 qemu_fdt_add_subnode(fdt, node); 333 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 334 335 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 336 address and size */ 337 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 338 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 339 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 340 341 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 342 343 /* Create dt nodes for dynamic devices */ 344 PlatformDevtreeData data = { 345 .fdt = fdt, 346 .mpic = mpic, 347 .irq_start = irq_start, 348 .node = node, 349 .pbus = pms->pbus_dev, 350 }; 351 352 /* Loop through all dynamic sysbus devices and create nodes for them */ 353 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 354 355 sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01, 356 &ambiguous)); 357 if (sbdev) { 358 assert(!ambiguous); 359 create_devtree_flash(sbdev, &data); 360 } 361 362 g_free(node); 363 } 364 365 static int ppce500_load_device_tree(PPCE500MachineState *pms, 366 hwaddr addr, 367 hwaddr initrd_base, 368 hwaddr initrd_size, 369 hwaddr kernel_base, 370 hwaddr kernel_size, 371 bool dry_run) 372 { 373 MachineState *machine = MACHINE(pms); 374 unsigned int smp_cpus = machine->smp.cpus; 375 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 376 CPUPPCState *env = first_cpu->env_ptr; 377 int ret = -1; 378 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 379 int fdt_size; 380 void *fdt; 381 uint8_t hypercall[16]; 382 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 383 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 384 int i; 385 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 386 char *soc; 387 char *mpic; 388 uint32_t mpic_ph; 389 uint32_t msi_ph; 390 char *gutil; 391 char *pci; 392 char *msi; 393 uint32_t *pci_map = NULL; 394 int len; 395 uint32_t pci_ranges[14] = 396 { 397 0x2000000, 0x0, pmc->pci_mmio_bus_base, 398 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 399 0x0, 0x20000000, 400 401 0x1000000, 0x0, 0x0, 402 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 403 0x0, 0x10000, 404 }; 405 const char *dtb_file = machine->dtb; 406 const char *toplevel_compat = machine->dt_compatible; 407 uint8_t rng_seed[32]; 408 409 if (dtb_file) { 410 char *filename; 411 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 412 if (!filename) { 413 goto out; 414 } 415 416 fdt = load_device_tree(filename, &fdt_size); 417 g_free(filename); 418 if (!fdt) { 419 goto out; 420 } 421 goto done; 422 } 423 424 fdt = create_device_tree(&fdt_size); 425 if (fdt == NULL) { 426 goto out; 427 } 428 429 /* Manipulate device tree in memory. */ 430 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 431 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 432 433 qemu_fdt_add_subnode(fdt, "/memory"); 434 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 435 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 436 sizeof(mem_reg_property)); 437 438 qemu_fdt_add_subnode(fdt, "/chosen"); 439 if (initrd_size) { 440 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 441 initrd_base); 442 if (ret < 0) { 443 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 444 } 445 446 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 447 (initrd_base + initrd_size)); 448 if (ret < 0) { 449 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 450 } 451 452 } 453 454 if (kernel_base != -1ULL) { 455 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 456 kernel_base >> 32, kernel_base, 457 kernel_size >> 32, kernel_size); 458 } 459 460 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 461 machine->kernel_cmdline); 462 if (ret < 0) 463 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 464 465 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 466 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 467 468 if (kvm_enabled()) { 469 /* Read out host's frequencies */ 470 clock_freq = kvmppc_get_clockfreq(); 471 tb_freq = kvmppc_get_tbfreq(); 472 473 /* indicate KVM hypercall interface */ 474 qemu_fdt_add_subnode(fdt, "/hypervisor"); 475 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 476 "linux,kvm"); 477 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 478 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 479 hypercall, sizeof(hypercall)); 480 /* if KVM supports the idle hcall, set property indicating this */ 481 if (kvmppc_get_hasidle(env)) { 482 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 483 } 484 } 485 486 /* Create CPU nodes */ 487 qemu_fdt_add_subnode(fdt, "/cpus"); 488 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 489 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 490 491 /* We need to generate the cpu nodes in reverse order, so Linux can pick 492 the first node as boot node and be happy */ 493 for (i = smp_cpus - 1; i >= 0; i--) { 494 CPUState *cpu; 495 char *cpu_name; 496 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 497 498 cpu = qemu_get_cpu(i); 499 if (cpu == NULL) { 500 continue; 501 } 502 env = cpu->env_ptr; 503 504 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 505 qemu_fdt_add_subnode(fdt, cpu_name); 506 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 507 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 508 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 509 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 510 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 511 env->dcache_line_size); 512 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 513 env->icache_line_size); 514 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 515 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 516 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 517 if (cpu->cpu_index) { 518 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 519 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 520 "spin-table"); 521 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 522 cpu_release_addr); 523 } else { 524 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 525 } 526 g_free(cpu_name); 527 } 528 529 qemu_fdt_add_subnode(fdt, "/aliases"); 530 /* XXX These should go into their respective devices' code */ 531 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 532 qemu_fdt_add_subnode(fdt, soc); 533 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 534 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 535 sizeof(compatible_sb)); 536 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 537 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 538 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 539 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 540 MPC8544_CCSRBAR_SIZE); 541 /* XXX should contain a reasonable value */ 542 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 543 544 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 545 qemu_fdt_add_subnode(fdt, mpic); 546 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 547 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 548 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 549 0x40000); 550 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 551 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 552 mpic_ph = qemu_fdt_alloc_phandle(fdt); 553 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 554 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 555 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 556 557 /* 558 * We have to generate ser1 first, because Linux takes the first 559 * device it finds in the dt as serial output device. And we generate 560 * devices in reverse order to the dt. 561 */ 562 if (serial_hd(1)) { 563 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 564 soc, mpic, "serial1", 1, false); 565 } 566 567 if (serial_hd(0)) { 568 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 569 soc, mpic, "serial0", 0, true); 570 } 571 572 /* i2c */ 573 dt_i2c_create(fdt, soc, mpic, "i2c"); 574 575 dt_rtc_create(fdt, "i2c", "rtc"); 576 577 /* sdhc */ 578 if (pmc->has_esdhc) { 579 dt_sdhc_create(fdt, soc, mpic); 580 } 581 582 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 583 MPC8544_UTIL_OFFSET); 584 qemu_fdt_add_subnode(fdt, gutil); 585 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 586 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 587 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 588 g_free(gutil); 589 590 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 591 qemu_fdt_add_subnode(fdt, msi); 592 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 593 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 594 msi_ph = qemu_fdt_alloc_phandle(fdt); 595 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 596 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 597 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 598 0xe0, 0x0, 599 0xe1, 0x0, 600 0xe2, 0x0, 601 0xe3, 0x0, 602 0xe4, 0x0, 603 0xe5, 0x0, 604 0xe6, 0x0, 605 0xe7, 0x0); 606 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 607 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 608 g_free(msi); 609 610 pci = g_strdup_printf("/pci@%llx", 611 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 612 qemu_fdt_add_subnode(fdt, pci); 613 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 614 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 615 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 616 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 617 0x0, 0x7); 618 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 619 pmc->pci_first_slot, pmc->pci_nr_slots, 620 &len); 621 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 622 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 623 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 624 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 625 for (i = 0; i < 14; i++) { 626 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 627 } 628 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 629 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 630 qemu_fdt_setprop_cells(fdt, pci, "reg", 631 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 632 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 633 0, 0x1000); 634 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 635 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 636 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 637 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 638 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 639 g_free(pci); 640 641 if (pmc->has_mpc8xxx_gpio) { 642 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 643 } 644 g_free(soc); 645 646 platform_bus_create_devtree(pms, fdt, mpic); 647 648 g_free(mpic); 649 650 pmc->fixup_devtree(fdt); 651 652 if (toplevel_compat) { 653 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 654 strlen(toplevel_compat) + 1); 655 } 656 657 done: 658 if (!dry_run) { 659 qemu_fdt_dumpdtb(fdt, fdt_size); 660 cpu_physical_memory_write(addr, fdt, fdt_size); 661 662 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ 663 g_free(machine->fdt); 664 machine->fdt = fdt; 665 } else { 666 g_free(fdt); 667 } 668 ret = fdt_size; 669 670 out: 671 g_free(pci_map); 672 673 return ret; 674 } 675 676 typedef struct DeviceTreeParams { 677 PPCE500MachineState *machine; 678 hwaddr addr; 679 hwaddr initrd_base; 680 hwaddr initrd_size; 681 hwaddr kernel_base; 682 hwaddr kernel_size; 683 Notifier notifier; 684 } DeviceTreeParams; 685 686 static void ppce500_reset_device_tree(void *opaque) 687 { 688 DeviceTreeParams *p = opaque; 689 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 690 p->initrd_size, p->kernel_base, p->kernel_size, 691 false); 692 } 693 694 static void ppce500_init_notify(Notifier *notifier, void *data) 695 { 696 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 697 ppce500_reset_device_tree(p); 698 } 699 700 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 701 hwaddr addr, 702 hwaddr initrd_base, 703 hwaddr initrd_size, 704 hwaddr kernel_base, 705 hwaddr kernel_size) 706 { 707 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 708 p->machine = machine; 709 p->addr = addr; 710 p->initrd_base = initrd_base; 711 p->initrd_size = initrd_size; 712 p->kernel_base = kernel_base; 713 p->kernel_size = kernel_size; 714 715 qemu_register_reset(ppce500_reset_device_tree, p); 716 p->notifier.notify = ppce500_init_notify; 717 qemu_add_machine_init_done_notifier(&p->notifier); 718 719 /* Issue the device tree loader once, so that we get the size of the blob */ 720 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 721 kernel_base, kernel_size, true); 722 } 723 724 hwaddr booke206_page_size_to_tlb(uint64_t size) 725 { 726 return 63 - clz64(size / KiB); 727 } 728 729 static int booke206_initial_map_tsize(CPUPPCState *env) 730 { 731 struct boot_info *bi = env->load_info; 732 hwaddr dt_end; 733 int ps; 734 735 /* Our initial TLB entry needs to cover everything from 0 to 736 the device tree top */ 737 dt_end = bi->dt_base + bi->dt_size; 738 ps = booke206_page_size_to_tlb(dt_end) + 1; 739 if (ps & 1) { 740 /* e500v2 can only do even TLB size bits */ 741 ps++; 742 } 743 return ps; 744 } 745 746 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 747 { 748 int tsize; 749 750 tsize = booke206_initial_map_tsize(env); 751 return (1ULL << 10 << tsize); 752 } 753 754 /* Create -kernel TLB entries for BookE. */ 755 static void mmubooke_create_initial_mapping(CPUPPCState *env) 756 { 757 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 758 hwaddr size; 759 int ps; 760 761 ps = booke206_initial_map_tsize(env); 762 size = (ps << MAS1_TSIZE_SHIFT); 763 tlb->mas1 = MAS1_VALID | size; 764 tlb->mas2 = 0; 765 tlb->mas7_3 = 0; 766 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 767 768 #ifdef CONFIG_KVM 769 env->tlb_dirty = true; 770 #endif 771 } 772 773 static void ppce500_cpu_reset_sec(void *opaque) 774 { 775 PowerPCCPU *cpu = opaque; 776 CPUState *cs = CPU(cpu); 777 778 cpu_reset(cs); 779 780 cs->exception_index = EXCP_HLT; 781 } 782 783 static void ppce500_cpu_reset(void *opaque) 784 { 785 PowerPCCPU *cpu = opaque; 786 CPUState *cs = CPU(cpu); 787 CPUPPCState *env = &cpu->env; 788 struct boot_info *bi = env->load_info; 789 790 cpu_reset(cs); 791 792 /* Set initial guest state. */ 793 cs->halted = 0; 794 env->gpr[1] = (16 * MiB) - 8; 795 env->gpr[3] = bi->dt_base; 796 env->gpr[4] = 0; 797 env->gpr[5] = 0; 798 env->gpr[6] = EPAPR_MAGIC; 799 env->gpr[7] = mmubooke_initial_mapsize(env); 800 env->gpr[8] = 0; 801 env->gpr[9] = 0; 802 env->nip = bi->entry; 803 mmubooke_create_initial_mapping(env); 804 } 805 806 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 807 IrqLines *irqs) 808 { 809 DeviceState *dev; 810 SysBusDevice *s; 811 int i, j, k; 812 MachineState *machine = MACHINE(pms); 813 unsigned int smp_cpus = machine->smp.cpus; 814 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 815 816 dev = qdev_new(TYPE_OPENPIC); 817 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 818 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 819 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 820 821 s = SYS_BUS_DEVICE(dev); 822 sysbus_realize_and_unref(s, &error_fatal); 823 824 k = 0; 825 for (i = 0; i < smp_cpus; i++) { 826 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 827 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 828 } 829 } 830 831 return dev; 832 } 833 834 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 835 IrqLines *irqs, Error **errp) 836 { 837 DeviceState *dev; 838 CPUState *cs; 839 840 dev = qdev_new(TYPE_KVM_OPENPIC); 841 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 842 843 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 844 object_unparent(OBJECT(dev)); 845 return NULL; 846 } 847 848 CPU_FOREACH(cs) { 849 if (kvm_openpic_connect_vcpu(dev, cs)) { 850 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 851 __func__); 852 abort(); 853 } 854 } 855 856 return dev; 857 } 858 859 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 860 MemoryRegion *ccsr, 861 IrqLines *irqs) 862 { 863 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 864 DeviceState *dev = NULL; 865 SysBusDevice *s; 866 867 if (kvm_enabled()) { 868 Error *err = NULL; 869 870 if (kvm_kernel_irqchip_allowed()) { 871 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 872 } 873 if (kvm_kernel_irqchip_required() && !dev) { 874 error_reportf_err(err, 875 "kernel_irqchip requested but unavailable: "); 876 exit(1); 877 } 878 } 879 880 if (!dev) { 881 dev = ppce500_init_mpic_qemu(pms, irqs); 882 } 883 884 s = SYS_BUS_DEVICE(dev); 885 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 886 s->mmio[0].memory); 887 888 return dev; 889 } 890 891 static void ppce500_power_off(void *opaque, int line, int on) 892 { 893 if (on) { 894 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 895 } 896 } 897 898 void ppce500_init(MachineState *machine) 899 { 900 MemoryRegion *address_space_mem = get_system_memory(); 901 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 902 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 903 MachineClass *mc = MACHINE_CLASS(pmc); 904 PCIBus *pci_bus; 905 CPUPPCState *env = NULL; 906 uint64_t loadaddr; 907 hwaddr kernel_base = -1LL; 908 int kernel_size = 0; 909 hwaddr dt_base = 0; 910 hwaddr initrd_base = 0; 911 int initrd_size = 0; 912 hwaddr cur_base = 0; 913 char *filename; 914 const char *payload_name; 915 bool kernel_as_payload; 916 hwaddr bios_entry = 0; 917 target_long payload_size; 918 struct boot_info *boot_info = NULL; 919 int dt_size; 920 int i; 921 unsigned int smp_cpus = machine->smp.cpus; 922 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 923 * 4 respectively */ 924 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 925 IrqLines *irqs; 926 DeviceState *dev, *mpicdev; 927 DriveInfo *dinfo; 928 CPUPPCState *firstenv = NULL; 929 MemoryRegion *ccsr_addr_space; 930 SysBusDevice *s; 931 PPCE500CCSRState *ccsr; 932 I2CBus *i2c; 933 934 irqs = g_new0(IrqLines, smp_cpus); 935 for (i = 0; i < smp_cpus; i++) { 936 PowerPCCPU *cpu; 937 CPUState *cs; 938 939 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 940 env = &cpu->env; 941 cs = CPU(cpu); 942 943 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 944 error_report("MMU model %i not supported by this machine", 945 env->mmu_model); 946 exit(1); 947 } 948 949 /* 950 * Secondary CPU starts in halted state for now. Needs to change 951 * when implementing non-kernel boot. 952 */ 953 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 954 &error_fatal); 955 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 956 957 if (!firstenv) { 958 firstenv = env; 959 } 960 961 irqs[i].irq[OPENPIC_OUTPUT_INT] = 962 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT); 963 irqs[i].irq[OPENPIC_OUTPUT_CINT] = 964 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT); 965 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 966 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 967 968 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 969 970 /* Register reset handler */ 971 if (!i) { 972 /* Primary CPU */ 973 boot_info = g_new0(struct boot_info, 1); 974 qemu_register_reset(ppce500_cpu_reset, cpu); 975 env->load_info = boot_info; 976 } else { 977 /* Secondary CPUs */ 978 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 979 } 980 } 981 982 env = firstenv; 983 984 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 985 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 986 exit(EXIT_FAILURE); 987 } 988 989 /* Register Memory */ 990 memory_region_add_subregion(address_space_mem, 0, machine->ram); 991 992 dev = qdev_new("e500-ccsr"); 993 object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev)); 994 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 995 ccsr = CCSR(dev); 996 ccsr_addr_space = &ccsr->ccsr_space; 997 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 998 ccsr_addr_space); 999 1000 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 1001 g_free(irqs); 1002 1003 /* Serial */ 1004 if (serial_hd(0)) { 1005 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 1006 0, qdev_get_gpio_in(mpicdev, 42), 399193, 1007 serial_hd(0), DEVICE_BIG_ENDIAN); 1008 } 1009 1010 if (serial_hd(1)) { 1011 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 1012 0, qdev_get_gpio_in(mpicdev, 42), 399193, 1013 serial_hd(1), DEVICE_BIG_ENDIAN); 1014 } 1015 1016 /* I2C */ 1017 dev = qdev_new("mpc-i2c"); 1018 s = SYS_BUS_DEVICE(dev); 1019 sysbus_realize_and_unref(s, &error_fatal); 1020 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 1021 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 1022 sysbus_mmio_get_region(s, 0)); 1023 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 1024 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 1025 1026 /* eSDHC */ 1027 if (pmc->has_esdhc) { 1028 dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE); 1029 qdev_prop_set_string(dev, "name", "esdhc"); 1030 qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE); 1031 s = SYS_BUS_DEVICE(dev); 1032 sysbus_realize_and_unref(s, &error_fatal); 1033 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, 1034 sysbus_mmio_get_region(s, 0)); 1035 1036 /* 1037 * Compatible with: 1038 * - SD Host Controller Specification Version 2.0 Part A2 1039 * (See MPC8569E Reference Manual) 1040 */ 1041 dev = qdev_new(TYPE_SYSBUS_SDHCI); 1042 qdev_prop_set_uint8(dev, "sd-spec-version", 2); 1043 qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN); 1044 s = SYS_BUS_DEVICE(dev); 1045 sysbus_realize_and_unref(s, &error_fatal); 1046 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ)); 1047 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET, 1048 sysbus_mmio_get_region(s, 0)); 1049 } 1050 1051 /* General Utility device */ 1052 dev = qdev_new("mpc8544-guts"); 1053 s = SYS_BUS_DEVICE(dev); 1054 sysbus_realize_and_unref(s, &error_fatal); 1055 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 1056 sysbus_mmio_get_region(s, 0)); 1057 1058 /* PCI */ 1059 dev = qdev_new("e500-pcihost"); 1060 object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev)); 1061 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 1062 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 1063 s = SYS_BUS_DEVICE(dev); 1064 sysbus_realize_and_unref(s, &error_fatal); 1065 for (i = 0; i < PCI_NUM_PINS; i++) { 1066 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 1067 } 1068 1069 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 1070 sysbus_mmio_get_region(s, 0)); 1071 1072 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 1073 if (!pci_bus) 1074 printf("couldn't create PCI controller!\n"); 1075 1076 if (pci_bus) { 1077 /* Register network interfaces. */ 1078 for (i = 0; i < nb_nics; i++) { 1079 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 1080 } 1081 } 1082 1083 /* Register spinning region */ 1084 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 1085 1086 if (pmc->has_mpc8xxx_gpio) { 1087 qemu_irq poweroff_irq; 1088 1089 dev = qdev_new("mpc8xxx_gpio"); 1090 s = SYS_BUS_DEVICE(dev); 1091 sysbus_realize_and_unref(s, &error_fatal); 1092 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 1093 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 1094 sysbus_mmio_get_region(s, 0)); 1095 1096 /* Power Off GPIO at Pin 0 */ 1097 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1098 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1099 } 1100 1101 /* Platform Bus Device */ 1102 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1103 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1104 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1105 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1106 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1107 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1108 1109 s = SYS_BUS_DEVICE(pms->pbus_dev); 1110 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1111 int irqn = pmc->platform_bus_first_irq + i; 1112 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1113 } 1114 1115 memory_region_add_subregion(address_space_mem, 1116 pmc->platform_bus_base, 1117 &pms->pbus_dev->mmio); 1118 1119 dinfo = drive_get(IF_PFLASH, 0, 0); 1120 if (dinfo) { 1121 BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 1122 BlockDriverState *bs = blk_bs(blk); 1123 uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio); 1124 uint64_t size = bdrv_getlength(bs); 1125 uint32_t sector_len = 64 * KiB; 1126 1127 if (!is_power_of_2(size)) { 1128 error_report("Size of pflash file must be a power of two."); 1129 exit(1); 1130 } 1131 1132 if (size > mmio_size) { 1133 error_report("Size of pflash file must not be bigger than %" PRIu64 1134 " bytes.", mmio_size); 1135 exit(1); 1136 } 1137 1138 if (!QEMU_IS_ALIGNED(size, sector_len)) { 1139 error_report("Size of pflash file must be a multiple of %" PRIu32 1140 ".", sector_len); 1141 exit(1); 1142 } 1143 1144 dev = qdev_new(TYPE_PFLASH_CFI01); 1145 qdev_prop_set_drive(dev, "drive", blk); 1146 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); 1147 qdev_prop_set_uint64(dev, "sector-length", sector_len); 1148 qdev_prop_set_uint8(dev, "width", 2); 1149 qdev_prop_set_bit(dev, "big-endian", true); 1150 qdev_prop_set_uint16(dev, "id0", 0x89); 1151 qdev_prop_set_uint16(dev, "id1", 0x18); 1152 qdev_prop_set_uint16(dev, "id2", 0x0000); 1153 qdev_prop_set_uint16(dev, "id3", 0x0); 1154 qdev_prop_set_string(dev, "name", "e500.flash"); 1155 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1156 1157 memory_region_add_subregion(&pms->pbus_dev->mmio, 0, 1158 pflash_cfi01_get_memory(PFLASH_CFI01(dev))); 1159 } 1160 1161 /* 1162 * Smart firmware defaults ahead! 1163 * 1164 * We follow the following table to select which payload we execute. 1165 * 1166 * -kernel | -bios | payload 1167 * ---------+-------+--------- 1168 * N | Y | u-boot 1169 * N | N | u-boot 1170 * Y | Y | u-boot 1171 * Y | N | kernel 1172 * 1173 * This ensures backwards compatibility with how we used to expose 1174 * -kernel to users but allows them to run through u-boot as well. 1175 */ 1176 kernel_as_payload = false; 1177 if (machine->firmware == NULL) { 1178 if (machine->kernel_filename) { 1179 payload_name = machine->kernel_filename; 1180 kernel_as_payload = true; 1181 } else { 1182 payload_name = "u-boot.e500"; 1183 } 1184 } else { 1185 payload_name = machine->firmware; 1186 } 1187 1188 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1189 if (!filename) { 1190 error_report("could not find firmware/kernel file '%s'", payload_name); 1191 exit(1); 1192 } 1193 1194 payload_size = load_elf(filename, NULL, NULL, NULL, 1195 &bios_entry, &loadaddr, NULL, NULL, 1196 1, PPC_ELF_MACHINE, 0, 0); 1197 if (payload_size < 0) { 1198 /* 1199 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1200 * ePAPR compliant kernel 1201 */ 1202 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1203 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1204 NULL, NULL); 1205 if (payload_size < 0) { 1206 error_report("could not load firmware '%s'", filename); 1207 exit(1); 1208 } 1209 } 1210 1211 g_free(filename); 1212 1213 if (kernel_as_payload) { 1214 kernel_base = loadaddr; 1215 kernel_size = payload_size; 1216 } 1217 1218 cur_base = loadaddr + payload_size; 1219 if (cur_base < 32 * MiB) { 1220 /* u-boot occupies memory up to 32MB, so load blobs above */ 1221 cur_base = 32 * MiB; 1222 } 1223 1224 /* Load bare kernel only if no bios/u-boot has been provided */ 1225 if (machine->kernel_filename && !kernel_as_payload) { 1226 kernel_base = cur_base; 1227 kernel_size = load_image_targphys(machine->kernel_filename, 1228 cur_base, 1229 machine->ram_size - cur_base); 1230 if (kernel_size < 0) { 1231 error_report("could not load kernel '%s'", 1232 machine->kernel_filename); 1233 exit(1); 1234 } 1235 1236 cur_base += kernel_size; 1237 } 1238 1239 /* Load initrd. */ 1240 if (machine->initrd_filename) { 1241 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1242 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1243 machine->ram_size - initrd_base); 1244 1245 if (initrd_size < 0) { 1246 error_report("could not load initial ram disk '%s'", 1247 machine->initrd_filename); 1248 exit(1); 1249 } 1250 1251 cur_base = initrd_base + initrd_size; 1252 } 1253 1254 /* 1255 * Reserve space for dtb behind the kernel image because Linux has a bug 1256 * where it can only handle the dtb if it's within the first 64MB of where 1257 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1258 * ensures enough space between kernel and initrd. 1259 */ 1260 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1261 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1262 error_report("not enough memory for device tree"); 1263 exit(1); 1264 } 1265 1266 dt_size = ppce500_prep_device_tree(pms, dt_base, 1267 initrd_base, initrd_size, 1268 kernel_base, kernel_size); 1269 if (dt_size < 0) { 1270 error_report("couldn't load device tree"); 1271 exit(1); 1272 } 1273 assert(dt_size < DTB_MAX_SIZE); 1274 1275 boot_info->entry = bios_entry; 1276 boot_info->dt_base = dt_base; 1277 boot_info->dt_size = dt_size; 1278 } 1279 1280 static void e500_ccsr_initfn(Object *obj) 1281 { 1282 PPCE500CCSRState *ccsr = CCSR(obj); 1283 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1284 MPC8544_CCSRBAR_SIZE); 1285 } 1286 1287 static const TypeInfo e500_ccsr_info = { 1288 .name = TYPE_CCSR, 1289 .parent = TYPE_SYS_BUS_DEVICE, 1290 .instance_size = sizeof(PPCE500CCSRState), 1291 .instance_init = e500_ccsr_initfn, 1292 }; 1293 1294 static const TypeInfo ppce500_info = { 1295 .name = TYPE_PPCE500_MACHINE, 1296 .parent = TYPE_MACHINE, 1297 .abstract = true, 1298 .instance_size = sizeof(PPCE500MachineState), 1299 .class_size = sizeof(PPCE500MachineClass), 1300 }; 1301 1302 static void e500_register_types(void) 1303 { 1304 type_register_static(&e500_ccsr_info); 1305 type_register_static(&ppce500_info); 1306 } 1307 1308 type_init(e500_register_types) 1309