1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qapi/error.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/openpic_kvm.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/loader.h" 35 #include "elf.h" 36 #include "hw/sysbus.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/host-utils.h" 39 #include "qemu/option.h" 40 #include "hw/pci-host/ppce500.h" 41 #include "qemu/error-report.h" 42 #include "hw/platform-bus.h" 43 #include "hw/net/fsl_etsec/etsec.h" 44 45 #define EPAPR_MAGIC (0x45504150) 46 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 47 #define DTC_LOAD_PAD 0x1800000 48 #define DTC_PAD_MASK 0xFFFFF 49 #define DTB_MAX_SIZE (8 * 1024 * 1024) 50 #define INITRD_LOAD_PAD 0x2000000 51 #define INITRD_PAD_MASK 0xFFFFFF 52 53 #define RAM_SIZES_ALIGN (64UL << 20) 54 55 /* TODO: parameterize */ 56 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 57 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 58 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 59 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 60 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 61 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 62 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 65 #define MPC8XXX_GPIO_IRQ 47 66 67 struct boot_info 68 { 69 uint32_t dt_base; 70 uint32_t dt_size; 71 uint32_t entry; 72 }; 73 74 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 75 int nr_slots, int *len) 76 { 77 int i = 0; 78 int slot; 79 int pci_irq; 80 int host_irq; 81 int last_slot = first_slot + nr_slots; 82 uint32_t *pci_map; 83 84 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 85 pci_map = g_malloc(*len); 86 87 for (slot = first_slot; slot < last_slot; slot++) { 88 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 89 pci_map[i++] = cpu_to_be32(slot << 11); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(0x0); 92 pci_map[i++] = cpu_to_be32(pci_irq + 1); 93 pci_map[i++] = cpu_to_be32(mpic); 94 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 95 pci_map[i++] = cpu_to_be32(host_irq + 1); 96 pci_map[i++] = cpu_to_be32(0x1); 97 } 98 } 99 100 assert((i * sizeof(uint32_t)) == *len); 101 102 return pci_map; 103 } 104 105 static void dt_serial_create(void *fdt, unsigned long long offset, 106 const char *soc, const char *mpic, 107 const char *alias, int idx, bool defcon) 108 { 109 char *ser; 110 111 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 112 qemu_fdt_add_subnode(fdt, ser); 113 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 114 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 115 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 116 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 117 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 118 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 119 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 120 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 121 122 if (defcon) { 123 /* 124 * "linux,stdout-path" and "stdout" properties are deprecated by linux 125 * kernel. New platforms should only use the "stdout-path" property. Set 126 * the new property and continue using older property to remain 127 * compatible with the existing firmware. 128 */ 129 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 130 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 131 } 132 g_free(ser); 133 } 134 135 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 136 { 137 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 138 int irq0 = MPC8XXX_GPIO_IRQ; 139 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 140 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 141 int gpio_ph; 142 143 qemu_fdt_add_subnode(fdt, node); 144 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 145 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 146 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 147 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 148 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 149 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 150 gpio_ph = qemu_fdt_alloc_phandle(fdt); 151 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 152 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 153 154 /* Power Off Pin */ 155 qemu_fdt_add_subnode(fdt, poweroff); 156 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 157 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 158 159 g_free(node); 160 g_free(poweroff); 161 } 162 163 typedef struct PlatformDevtreeData { 164 void *fdt; 165 const char *mpic; 166 int irq_start; 167 const char *node; 168 PlatformBusDevice *pbus; 169 } PlatformDevtreeData; 170 171 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 172 { 173 eTSEC *etsec = ETSEC_COMMON(sbdev); 174 PlatformBusDevice *pbus = data->pbus; 175 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 176 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 177 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 178 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 179 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 180 gchar *group = g_strdup_printf("%s/queue-group", node); 181 void *fdt = data->fdt; 182 183 assert((int64_t)mmio0 >= 0); 184 assert(irq0 >= 0); 185 assert(irq1 >= 0); 186 assert(irq2 >= 0); 187 188 qemu_fdt_add_subnode(fdt, node); 189 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 190 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 191 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 192 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 193 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 194 195 qemu_fdt_add_subnode(fdt, group); 196 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 197 qemu_fdt_setprop_cells(fdt, group, "interrupts", 198 data->irq_start + irq0, 0x2, 199 data->irq_start + irq1, 0x2, 200 data->irq_start + irq2, 0x2); 201 202 g_free(node); 203 g_free(group); 204 205 return 0; 206 } 207 208 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 209 { 210 PlatformDevtreeData *data = opaque; 211 bool matched = false; 212 213 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 214 create_devtree_etsec(sbdev, data); 215 matched = true; 216 } 217 218 if (!matched) { 219 error_report("Device %s is not supported by this machine yet.", 220 qdev_fw_name(DEVICE(sbdev))); 221 exit(1); 222 } 223 } 224 225 static void platform_bus_create_devtree(const PPCE500MachineClass *pmc, 226 void *fdt, const char *mpic) 227 { 228 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 229 const char platcomp[] = "qemu,platform\0simple-bus"; 230 uint64_t addr = pmc->platform_bus_base; 231 uint64_t size = pmc->platform_bus_size; 232 int irq_start = pmc->platform_bus_first_irq; 233 PlatformBusDevice *pbus; 234 DeviceState *dev; 235 236 /* Create a /platform node that we can put all devices into */ 237 238 qemu_fdt_add_subnode(fdt, node); 239 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 240 241 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 242 address and size */ 243 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 244 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 245 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 246 247 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 248 249 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); 250 pbus = PLATFORM_BUS_DEVICE(dev); 251 252 /* We can only create dt nodes for dynamic devices when they're ready */ 253 if (pbus->done_gathering) { 254 PlatformDevtreeData data = { 255 .fdt = fdt, 256 .mpic = mpic, 257 .irq_start = irq_start, 258 .node = node, 259 .pbus = pbus, 260 }; 261 262 /* Loop through all dynamic sysbus devices and create nodes for them */ 263 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 264 } 265 266 g_free(node); 267 } 268 269 static int ppce500_load_device_tree(PPCE500MachineState *pms, 270 hwaddr addr, 271 hwaddr initrd_base, 272 hwaddr initrd_size, 273 hwaddr kernel_base, 274 hwaddr kernel_size, 275 bool dry_run) 276 { 277 MachineState *machine = MACHINE(pms); 278 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 279 CPUPPCState *env = first_cpu->env_ptr; 280 int ret = -1; 281 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 282 int fdt_size; 283 void *fdt; 284 uint8_t hypercall[16]; 285 uint32_t clock_freq = 400000000; 286 uint32_t tb_freq = 400000000; 287 int i; 288 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 289 char *soc; 290 char *mpic; 291 uint32_t mpic_ph; 292 uint32_t msi_ph; 293 char *gutil; 294 char *pci; 295 char *msi; 296 uint32_t *pci_map = NULL; 297 int len; 298 uint32_t pci_ranges[14] = 299 { 300 0x2000000, 0x0, pmc->pci_mmio_bus_base, 301 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 302 0x0, 0x20000000, 303 304 0x1000000, 0x0, 0x0, 305 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 306 0x0, 0x10000, 307 }; 308 QemuOpts *machine_opts = qemu_get_machine_opts(); 309 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 310 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 311 312 if (dtb_file) { 313 char *filename; 314 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 315 if (!filename) { 316 goto out; 317 } 318 319 fdt = load_device_tree(filename, &fdt_size); 320 g_free(filename); 321 if (!fdt) { 322 goto out; 323 } 324 goto done; 325 } 326 327 fdt = create_device_tree(&fdt_size); 328 if (fdt == NULL) { 329 goto out; 330 } 331 332 /* Manipulate device tree in memory. */ 333 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 334 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 335 336 qemu_fdt_add_subnode(fdt, "/memory"); 337 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 338 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 339 sizeof(mem_reg_property)); 340 341 qemu_fdt_add_subnode(fdt, "/chosen"); 342 if (initrd_size) { 343 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 344 initrd_base); 345 if (ret < 0) { 346 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 347 } 348 349 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 350 (initrd_base + initrd_size)); 351 if (ret < 0) { 352 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 353 } 354 355 } 356 357 if (kernel_base != -1ULL) { 358 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 359 kernel_base >> 32, kernel_base, 360 kernel_size >> 32, kernel_size); 361 } 362 363 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 364 machine->kernel_cmdline); 365 if (ret < 0) 366 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 367 368 if (kvm_enabled()) { 369 /* Read out host's frequencies */ 370 clock_freq = kvmppc_get_clockfreq(); 371 tb_freq = kvmppc_get_tbfreq(); 372 373 /* indicate KVM hypercall interface */ 374 qemu_fdt_add_subnode(fdt, "/hypervisor"); 375 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 376 "linux,kvm"); 377 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 378 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 379 hypercall, sizeof(hypercall)); 380 /* if KVM supports the idle hcall, set property indicating this */ 381 if (kvmppc_get_hasidle(env)) { 382 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 383 } 384 } 385 386 /* Create CPU nodes */ 387 qemu_fdt_add_subnode(fdt, "/cpus"); 388 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 389 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 390 391 /* We need to generate the cpu nodes in reverse order, so Linux can pick 392 the first node as boot node and be happy */ 393 for (i = smp_cpus - 1; i >= 0; i--) { 394 CPUState *cpu; 395 char *cpu_name; 396 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 397 398 cpu = qemu_get_cpu(i); 399 if (cpu == NULL) { 400 continue; 401 } 402 env = cpu->env_ptr; 403 404 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 405 qemu_fdt_add_subnode(fdt, cpu_name); 406 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 407 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 408 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 409 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 410 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 411 env->dcache_line_size); 412 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 413 env->icache_line_size); 414 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 415 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 416 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 417 if (cpu->cpu_index) { 418 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 419 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 420 "spin-table"); 421 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 422 cpu_release_addr); 423 } else { 424 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 425 } 426 g_free(cpu_name); 427 } 428 429 qemu_fdt_add_subnode(fdt, "/aliases"); 430 /* XXX These should go into their respective devices' code */ 431 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 432 qemu_fdt_add_subnode(fdt, soc); 433 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 434 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 435 sizeof(compatible_sb)); 436 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 437 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 438 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 439 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 440 MPC8544_CCSRBAR_SIZE); 441 /* XXX should contain a reasonable value */ 442 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 443 444 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 445 qemu_fdt_add_subnode(fdt, mpic); 446 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 447 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 448 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 449 0x40000); 450 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 451 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 452 mpic_ph = qemu_fdt_alloc_phandle(fdt); 453 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 454 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 455 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 456 457 /* 458 * We have to generate ser1 first, because Linux takes the first 459 * device it finds in the dt as serial output device. And we generate 460 * devices in reverse order to the dt. 461 */ 462 if (serial_hd(1)) { 463 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 464 soc, mpic, "serial1", 1, false); 465 } 466 467 if (serial_hd(0)) { 468 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 469 soc, mpic, "serial0", 0, true); 470 } 471 472 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 473 MPC8544_UTIL_OFFSET); 474 qemu_fdt_add_subnode(fdt, gutil); 475 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 476 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 477 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 478 g_free(gutil); 479 480 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 481 qemu_fdt_add_subnode(fdt, msi); 482 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 483 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 484 msi_ph = qemu_fdt_alloc_phandle(fdt); 485 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 486 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 487 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 488 0xe0, 0x0, 489 0xe1, 0x0, 490 0xe2, 0x0, 491 0xe3, 0x0, 492 0xe4, 0x0, 493 0xe5, 0x0, 494 0xe6, 0x0, 495 0xe7, 0x0); 496 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 497 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 498 g_free(msi); 499 500 pci = g_strdup_printf("/pci@%llx", 501 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 502 qemu_fdt_add_subnode(fdt, pci); 503 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 504 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 505 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 506 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 507 0x0, 0x7); 508 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 509 pmc->pci_first_slot, pmc->pci_nr_slots, 510 &len); 511 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 512 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 513 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 514 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 515 for (i = 0; i < 14; i++) { 516 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 517 } 518 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 519 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 520 qemu_fdt_setprop_cells(fdt, pci, "reg", 521 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 522 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 523 0, 0x1000); 524 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 525 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 526 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 527 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 528 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 529 g_free(pci); 530 531 if (pmc->has_mpc8xxx_gpio) { 532 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 533 } 534 g_free(soc); 535 536 if (pmc->has_platform_bus) { 537 platform_bus_create_devtree(pmc, fdt, mpic); 538 } 539 g_free(mpic); 540 541 pmc->fixup_devtree(fdt); 542 543 if (toplevel_compat) { 544 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 545 strlen(toplevel_compat) + 1); 546 } 547 548 done: 549 if (!dry_run) { 550 qemu_fdt_dumpdtb(fdt, fdt_size); 551 cpu_physical_memory_write(addr, fdt, fdt_size); 552 } 553 ret = fdt_size; 554 555 out: 556 g_free(pci_map); 557 558 return ret; 559 } 560 561 typedef struct DeviceTreeParams { 562 PPCE500MachineState *machine; 563 hwaddr addr; 564 hwaddr initrd_base; 565 hwaddr initrd_size; 566 hwaddr kernel_base; 567 hwaddr kernel_size; 568 Notifier notifier; 569 } DeviceTreeParams; 570 571 static void ppce500_reset_device_tree(void *opaque) 572 { 573 DeviceTreeParams *p = opaque; 574 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 575 p->initrd_size, p->kernel_base, p->kernel_size, 576 false); 577 } 578 579 static void ppce500_init_notify(Notifier *notifier, void *data) 580 { 581 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 582 ppce500_reset_device_tree(p); 583 } 584 585 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 586 hwaddr addr, 587 hwaddr initrd_base, 588 hwaddr initrd_size, 589 hwaddr kernel_base, 590 hwaddr kernel_size) 591 { 592 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 593 p->machine = machine; 594 p->addr = addr; 595 p->initrd_base = initrd_base; 596 p->initrd_size = initrd_size; 597 p->kernel_base = kernel_base; 598 p->kernel_size = kernel_size; 599 600 qemu_register_reset(ppce500_reset_device_tree, p); 601 p->notifier.notify = ppce500_init_notify; 602 qemu_add_machine_init_done_notifier(&p->notifier); 603 604 /* Issue the device tree loader once, so that we get the size of the blob */ 605 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 606 kernel_base, kernel_size, true); 607 } 608 609 /* Create -kernel TLB entries for BookE. */ 610 hwaddr booke206_page_size_to_tlb(uint64_t size) 611 { 612 return 63 - clz64(size >> 10); 613 } 614 615 static int booke206_initial_map_tsize(CPUPPCState *env) 616 { 617 struct boot_info *bi = env->load_info; 618 hwaddr dt_end; 619 int ps; 620 621 /* Our initial TLB entry needs to cover everything from 0 to 622 the device tree top */ 623 dt_end = bi->dt_base + bi->dt_size; 624 ps = booke206_page_size_to_tlb(dt_end) + 1; 625 if (ps & 1) { 626 /* e500v2 can only do even TLB size bits */ 627 ps++; 628 } 629 return ps; 630 } 631 632 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 633 { 634 int tsize; 635 636 tsize = booke206_initial_map_tsize(env); 637 return (1ULL << 10 << tsize); 638 } 639 640 static void mmubooke_create_initial_mapping(CPUPPCState *env) 641 { 642 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 643 hwaddr size; 644 int ps; 645 646 ps = booke206_initial_map_tsize(env); 647 size = (ps << MAS1_TSIZE_SHIFT); 648 tlb->mas1 = MAS1_VALID | size; 649 tlb->mas2 = 0; 650 tlb->mas7_3 = 0; 651 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 652 653 env->tlb_dirty = true; 654 } 655 656 static void ppce500_cpu_reset_sec(void *opaque) 657 { 658 PowerPCCPU *cpu = opaque; 659 CPUState *cs = CPU(cpu); 660 661 cpu_reset(cs); 662 663 /* Secondary CPU starts in halted state for now. Needs to change when 664 implementing non-kernel boot. */ 665 cs->halted = 1; 666 cs->exception_index = EXCP_HLT; 667 } 668 669 static void ppce500_cpu_reset(void *opaque) 670 { 671 PowerPCCPU *cpu = opaque; 672 CPUState *cs = CPU(cpu); 673 CPUPPCState *env = &cpu->env; 674 struct boot_info *bi = env->load_info; 675 676 cpu_reset(cs); 677 678 /* Set initial guest state. */ 679 cs->halted = 0; 680 env->gpr[1] = (16<<20) - 8; 681 env->gpr[3] = bi->dt_base; 682 env->gpr[4] = 0; 683 env->gpr[5] = 0; 684 env->gpr[6] = EPAPR_MAGIC; 685 env->gpr[7] = mmubooke_initial_mapsize(env); 686 env->gpr[8] = 0; 687 env->gpr[9] = 0; 688 env->nip = bi->entry; 689 mmubooke_create_initial_mapping(env); 690 } 691 692 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 693 qemu_irq **irqs) 694 { 695 DeviceState *dev; 696 SysBusDevice *s; 697 int i, j, k; 698 MachineState *machine = MACHINE(pms); 699 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 700 701 dev = qdev_create(NULL, TYPE_OPENPIC); 702 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 703 &error_fatal); 704 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 705 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 706 707 qdev_init_nofail(dev); 708 s = SYS_BUS_DEVICE(dev); 709 710 k = 0; 711 for (i = 0; i < smp_cpus; i++) { 712 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 713 sysbus_connect_irq(s, k++, irqs[i][j]); 714 } 715 } 716 717 return dev; 718 } 719 720 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 721 qemu_irq **irqs, Error **errp) 722 { 723 Error *err = NULL; 724 DeviceState *dev; 725 CPUState *cs; 726 727 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 728 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 729 730 object_property_set_bool(OBJECT(dev), true, "realized", &err); 731 if (err) { 732 error_propagate(errp, err); 733 object_unparent(OBJECT(dev)); 734 return NULL; 735 } 736 737 CPU_FOREACH(cs) { 738 if (kvm_openpic_connect_vcpu(dev, cs)) { 739 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 740 __func__); 741 abort(); 742 } 743 } 744 745 return dev; 746 } 747 748 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 749 MemoryRegion *ccsr, 750 qemu_irq **irqs) 751 { 752 MachineState *machine = MACHINE(pms); 753 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 754 DeviceState *dev = NULL; 755 SysBusDevice *s; 756 757 if (kvm_enabled()) { 758 Error *err = NULL; 759 760 if (machine_kernel_irqchip_allowed(machine)) { 761 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 762 } 763 if (machine_kernel_irqchip_required(machine) && !dev) { 764 error_reportf_err(err, 765 "kernel_irqchip requested but unavailable: "); 766 exit(1); 767 } 768 } 769 770 if (!dev) { 771 dev = ppce500_init_mpic_qemu(pms, irqs); 772 } 773 774 s = SYS_BUS_DEVICE(dev); 775 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 776 s->mmio[0].memory); 777 778 return dev; 779 } 780 781 static void ppce500_power_off(void *opaque, int line, int on) 782 { 783 if (on) { 784 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 785 } 786 } 787 788 void ppce500_init(MachineState *machine) 789 { 790 MemoryRegion *address_space_mem = get_system_memory(); 791 MemoryRegion *ram = g_new(MemoryRegion, 1); 792 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 793 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 794 PCIBus *pci_bus; 795 CPUPPCState *env = NULL; 796 uint64_t loadaddr; 797 hwaddr kernel_base = -1LL; 798 int kernel_size = 0; 799 hwaddr dt_base = 0; 800 hwaddr initrd_base = 0; 801 int initrd_size = 0; 802 hwaddr cur_base = 0; 803 char *filename; 804 const char *payload_name; 805 bool kernel_as_payload; 806 hwaddr bios_entry = 0; 807 target_long payload_size; 808 struct boot_info *boot_info; 809 int dt_size; 810 int i; 811 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 812 * 4 respectively */ 813 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 814 qemu_irq **irqs; 815 DeviceState *dev, *mpicdev; 816 CPUPPCState *firstenv = NULL; 817 MemoryRegion *ccsr_addr_space; 818 SysBusDevice *s; 819 PPCE500CCSRState *ccsr; 820 821 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 822 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 823 for (i = 0; i < smp_cpus; i++) { 824 PowerPCCPU *cpu; 825 CPUState *cs; 826 qemu_irq *input; 827 828 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 829 env = &cpu->env; 830 cs = CPU(cpu); 831 832 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 833 error_report("MMU model %i not supported by this machine", 834 env->mmu_model); 835 exit(1); 836 } 837 838 if (!firstenv) { 839 firstenv = env; 840 } 841 842 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 843 input = (qemu_irq *)env->irq_inputs; 844 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 845 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 846 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 847 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 848 849 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 850 851 /* Register reset handler */ 852 if (!i) { 853 /* Primary CPU */ 854 struct boot_info *boot_info; 855 boot_info = g_malloc0(sizeof(struct boot_info)); 856 qemu_register_reset(ppce500_cpu_reset, cpu); 857 env->load_info = boot_info; 858 } else { 859 /* Secondary CPUs */ 860 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 861 } 862 } 863 864 env = firstenv; 865 866 /* Fixup Memory size on a alignment boundary */ 867 ram_size &= ~(RAM_SIZES_ALIGN - 1); 868 machine->ram_size = ram_size; 869 870 /* Register Memory */ 871 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 872 memory_region_add_subregion(address_space_mem, 0, ram); 873 874 dev = qdev_create(NULL, "e500-ccsr"); 875 object_property_add_child(qdev_get_machine(), "e500-ccsr", 876 OBJECT(dev), NULL); 877 qdev_init_nofail(dev); 878 ccsr = CCSR(dev); 879 ccsr_addr_space = &ccsr->ccsr_space; 880 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 881 ccsr_addr_space); 882 883 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 884 885 /* Serial */ 886 if (serial_hd(0)) { 887 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 888 0, qdev_get_gpio_in(mpicdev, 42), 399193, 889 serial_hd(0), DEVICE_BIG_ENDIAN); 890 } 891 892 if (serial_hd(1)) { 893 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 894 0, qdev_get_gpio_in(mpicdev, 42), 399193, 895 serial_hd(1), DEVICE_BIG_ENDIAN); 896 } 897 898 /* General Utility device */ 899 dev = qdev_create(NULL, "mpc8544-guts"); 900 qdev_init_nofail(dev); 901 s = SYS_BUS_DEVICE(dev); 902 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 903 sysbus_mmio_get_region(s, 0)); 904 905 /* PCI */ 906 dev = qdev_create(NULL, "e500-pcihost"); 907 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 908 &error_abort); 909 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 910 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 911 qdev_init_nofail(dev); 912 s = SYS_BUS_DEVICE(dev); 913 for (i = 0; i < PCI_NUM_PINS; i++) { 914 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 915 } 916 917 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 918 sysbus_mmio_get_region(s, 0)); 919 920 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 921 if (!pci_bus) 922 printf("couldn't create PCI controller!\n"); 923 924 if (pci_bus) { 925 /* Register network interfaces. */ 926 for (i = 0; i < nb_nics; i++) { 927 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 928 } 929 } 930 931 /* Register spinning region */ 932 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 933 934 if (pmc->has_mpc8xxx_gpio) { 935 qemu_irq poweroff_irq; 936 937 dev = qdev_create(NULL, "mpc8xxx_gpio"); 938 s = SYS_BUS_DEVICE(dev); 939 qdev_init_nofail(dev); 940 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 941 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 942 sysbus_mmio_get_region(s, 0)); 943 944 /* Power Off GPIO at Pin 0 */ 945 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 946 qdev_connect_gpio_out(dev, 0, poweroff_irq); 947 } 948 949 /* Platform Bus Device */ 950 if (pmc->has_platform_bus) { 951 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 952 dev->id = TYPE_PLATFORM_BUS_DEVICE; 953 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 954 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 955 qdev_init_nofail(dev); 956 s = SYS_BUS_DEVICE(dev); 957 958 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 959 int irqn = pmc->platform_bus_first_irq + i; 960 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 961 } 962 963 memory_region_add_subregion(address_space_mem, 964 pmc->platform_bus_base, 965 sysbus_mmio_get_region(s, 0)); 966 } 967 968 /* 969 * Smart firmware defaults ahead! 970 * 971 * We follow the following table to select which payload we execute. 972 * 973 * -kernel | -bios | payload 974 * ---------+-------+--------- 975 * N | Y | u-boot 976 * N | N | u-boot 977 * Y | Y | u-boot 978 * Y | N | kernel 979 * 980 * This ensures backwards compatibility with how we used to expose 981 * -kernel to users but allows them to run through u-boot as well. 982 */ 983 kernel_as_payload = false; 984 if (bios_name == NULL) { 985 if (machine->kernel_filename) { 986 payload_name = machine->kernel_filename; 987 kernel_as_payload = true; 988 } else { 989 payload_name = "u-boot.e500"; 990 } 991 } else { 992 payload_name = bios_name; 993 } 994 995 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 996 997 payload_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 998 1, PPC_ELF_MACHINE, 0, 0); 999 if (payload_size < 0) { 1000 /* 1001 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1002 * ePAPR compliant kernel 1003 */ 1004 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1005 NULL, NULL); 1006 if (payload_size < 0) { 1007 error_report("qemu: could not load firmware '%s'", filename); 1008 exit(1); 1009 } 1010 } 1011 1012 g_free(filename); 1013 1014 if (kernel_as_payload) { 1015 kernel_base = loadaddr; 1016 kernel_size = payload_size; 1017 } 1018 1019 cur_base = loadaddr + payload_size; 1020 if (cur_base < (32 * 1024 * 1024)) { 1021 /* u-boot occupies memory up to 32MB, so load blobs above */ 1022 cur_base = (32 * 1024 * 1024); 1023 } 1024 1025 /* Load bare kernel only if no bios/u-boot has been provided */ 1026 if (machine->kernel_filename && !kernel_as_payload) { 1027 kernel_base = cur_base; 1028 kernel_size = load_image_targphys(machine->kernel_filename, 1029 cur_base, 1030 ram_size - cur_base); 1031 if (kernel_size < 0) { 1032 error_report("could not load kernel '%s'", 1033 machine->kernel_filename); 1034 exit(1); 1035 } 1036 1037 cur_base += kernel_size; 1038 } 1039 1040 /* Load initrd. */ 1041 if (machine->initrd_filename) { 1042 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1043 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1044 ram_size - initrd_base); 1045 1046 if (initrd_size < 0) { 1047 error_report("could not load initial ram disk '%s'", 1048 machine->initrd_filename); 1049 exit(1); 1050 } 1051 1052 cur_base = initrd_base + initrd_size; 1053 } 1054 1055 /* 1056 * Reserve space for dtb behind the kernel image because Linux has a bug 1057 * where it can only handle the dtb if it's within the first 64MB of where 1058 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1059 * ensures enough space between kernel and initrd. 1060 */ 1061 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1062 if (dt_base + DTB_MAX_SIZE > ram_size) { 1063 error_report("qemu: not enough memory for device tree"); 1064 exit(1); 1065 } 1066 1067 dt_size = ppce500_prep_device_tree(pms, dt_base, 1068 initrd_base, initrd_size, 1069 kernel_base, kernel_size); 1070 if (dt_size < 0) { 1071 error_report("couldn't load device tree"); 1072 exit(1); 1073 } 1074 assert(dt_size < DTB_MAX_SIZE); 1075 1076 boot_info = env->load_info; 1077 boot_info->entry = bios_entry; 1078 boot_info->dt_base = dt_base; 1079 boot_info->dt_size = dt_size; 1080 } 1081 1082 static void e500_ccsr_initfn(Object *obj) 1083 { 1084 PPCE500CCSRState *ccsr = CCSR(obj); 1085 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1086 MPC8544_CCSRBAR_SIZE); 1087 } 1088 1089 static const TypeInfo e500_ccsr_info = { 1090 .name = TYPE_CCSR, 1091 .parent = TYPE_SYS_BUS_DEVICE, 1092 .instance_size = sizeof(PPCE500CCSRState), 1093 .instance_init = e500_ccsr_initfn, 1094 }; 1095 1096 static const TypeInfo ppce500_info = { 1097 .name = TYPE_PPCE500_MACHINE, 1098 .parent = TYPE_MACHINE, 1099 .abstract = true, 1100 .class_size = sizeof(PPCE500MachineClass), 1101 }; 1102 1103 static void e500_register_types(void) 1104 { 1105 type_register_static(&e500_ccsr_info); 1106 type_register_static(&ppce500_info); 1107 } 1108 1109 type_init(e500_register_types) 1110