1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/datadir.h" 20 #include "qemu/units.h" 21 #include "qapi/error.h" 22 #include "e500.h" 23 #include "e500-ccsr.h" 24 #include "net/net.h" 25 #include "qemu/config-file.h" 26 #include "hw/char/serial.h" 27 #include "hw/pci/pci.h" 28 #include "hw/boards.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/kvm.h" 31 #include "sysemu/reset.h" 32 #include "sysemu/runstate.h" 33 #include "kvm_ppc.h" 34 #include "sysemu/device_tree.h" 35 #include "hw/ppc/openpic.h" 36 #include "hw/ppc/openpic_kvm.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/qdev-properties.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "hw/sysbus.h" 42 #include "exec/address-spaces.h" 43 #include "qemu/host-utils.h" 44 #include "qemu/option.h" 45 #include "hw/pci-host/ppce500.h" 46 #include "qemu/error-report.h" 47 #include "hw/platform-bus.h" 48 #include "hw/net/fsl_etsec/etsec.h" 49 #include "hw/i2c/i2c.h" 50 #include "hw/irq.h" 51 52 #define EPAPR_MAGIC (0x45504150) 53 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 54 #define DTC_LOAD_PAD 0x1800000 55 #define DTC_PAD_MASK 0xFFFFF 56 #define DTB_MAX_SIZE (8 * MiB) 57 #define INITRD_LOAD_PAD 0x2000000 58 #define INITRD_PAD_MASK 0xFFFFFF 59 60 #define RAM_SIZES_ALIGN (64 * MiB) 61 62 /* TODO: parameterize */ 63 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 64 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 65 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 66 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 67 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 68 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 69 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 70 #define MPC8544_UTIL_OFFSET 0xe0000ULL 71 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 72 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 73 #define MPC8XXX_GPIO_IRQ 47 74 #define MPC8544_I2C_IRQ 43 75 #define RTC_REGS_OFFSET 0x68 76 77 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 78 79 struct boot_info 80 { 81 uint32_t dt_base; 82 uint32_t dt_size; 83 uint32_t entry; 84 }; 85 86 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 87 int nr_slots, int *len) 88 { 89 int i = 0; 90 int slot; 91 int pci_irq; 92 int host_irq; 93 int last_slot = first_slot + nr_slots; 94 uint32_t *pci_map; 95 96 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 97 pci_map = g_malloc(*len); 98 99 for (slot = first_slot; slot < last_slot; slot++) { 100 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 101 pci_map[i++] = cpu_to_be32(slot << 11); 102 pci_map[i++] = cpu_to_be32(0x0); 103 pci_map[i++] = cpu_to_be32(0x0); 104 pci_map[i++] = cpu_to_be32(pci_irq + 1); 105 pci_map[i++] = cpu_to_be32(mpic); 106 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 107 pci_map[i++] = cpu_to_be32(host_irq + 1); 108 pci_map[i++] = cpu_to_be32(0x1); 109 } 110 } 111 112 assert((i * sizeof(uint32_t)) == *len); 113 114 return pci_map; 115 } 116 117 static void dt_serial_create(void *fdt, unsigned long long offset, 118 const char *soc, const char *mpic, 119 const char *alias, int idx, bool defcon) 120 { 121 char *ser; 122 123 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 124 qemu_fdt_add_subnode(fdt, ser); 125 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 126 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 127 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 128 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 129 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 130 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 131 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 132 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 133 134 if (defcon) { 135 /* 136 * "linux,stdout-path" and "stdout" properties are deprecated by linux 137 * kernel. New platforms should only use the "stdout-path" property. Set 138 * the new property and continue using older property to remain 139 * compatible with the existing firmware. 140 */ 141 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 142 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 143 } 144 g_free(ser); 145 } 146 147 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 148 { 149 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 150 int irq0 = MPC8XXX_GPIO_IRQ; 151 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 152 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 153 int gpio_ph; 154 155 qemu_fdt_add_subnode(fdt, node); 156 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 157 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 158 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 159 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 160 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 161 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 162 gpio_ph = qemu_fdt_alloc_phandle(fdt); 163 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 164 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 165 166 /* Power Off Pin */ 167 qemu_fdt_add_subnode(fdt, poweroff); 168 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 169 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 170 171 g_free(node); 172 g_free(poweroff); 173 } 174 175 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 176 { 177 int offset = RTC_REGS_OFFSET; 178 179 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 180 qemu_fdt_add_subnode(fdt, rtc); 181 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 182 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 183 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 184 185 g_free(rtc); 186 } 187 188 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 189 const char *alias) 190 { 191 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 192 int irq0 = MPC8544_I2C_IRQ; 193 194 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 195 qemu_fdt_add_subnode(fdt, i2c); 196 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 197 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 198 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 199 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 200 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 201 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 202 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 203 204 g_free(i2c); 205 } 206 207 208 typedef struct PlatformDevtreeData { 209 void *fdt; 210 const char *mpic; 211 int irq_start; 212 const char *node; 213 PlatformBusDevice *pbus; 214 } PlatformDevtreeData; 215 216 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 217 { 218 eTSEC *etsec = ETSEC_COMMON(sbdev); 219 PlatformBusDevice *pbus = data->pbus; 220 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 221 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 222 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 223 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 224 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 225 gchar *group = g_strdup_printf("%s/queue-group", node); 226 void *fdt = data->fdt; 227 228 assert((int64_t)mmio0 >= 0); 229 assert(irq0 >= 0); 230 assert(irq1 >= 0); 231 assert(irq2 >= 0); 232 233 qemu_fdt_add_subnode(fdt, node); 234 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); 235 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 236 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 237 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 238 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 239 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 240 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 241 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 242 243 qemu_fdt_add_subnode(fdt, group); 244 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 245 qemu_fdt_setprop_cells(fdt, group, "interrupts", 246 data->irq_start + irq0, 0x2, 247 data->irq_start + irq1, 0x2, 248 data->irq_start + irq2, 0x2); 249 250 g_free(node); 251 g_free(group); 252 253 return 0; 254 } 255 256 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 257 { 258 PlatformDevtreeData *data = opaque; 259 bool matched = false; 260 261 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 262 create_devtree_etsec(sbdev, data); 263 matched = true; 264 } 265 266 if (!matched) { 267 error_report("Device %s is not supported by this machine yet.", 268 qdev_fw_name(DEVICE(sbdev))); 269 exit(1); 270 } 271 } 272 273 static void platform_bus_create_devtree(PPCE500MachineState *pms, 274 void *fdt, const char *mpic) 275 { 276 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 277 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 278 const char platcomp[] = "qemu,platform\0simple-bus"; 279 uint64_t addr = pmc->platform_bus_base; 280 uint64_t size = pmc->platform_bus_size; 281 int irq_start = pmc->platform_bus_first_irq; 282 283 /* Create a /platform node that we can put all devices into */ 284 285 qemu_fdt_add_subnode(fdt, node); 286 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 287 288 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 289 address and size */ 290 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 291 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 292 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 293 294 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 295 296 /* Create dt nodes for dynamic devices */ 297 PlatformDevtreeData data = { 298 .fdt = fdt, 299 .mpic = mpic, 300 .irq_start = irq_start, 301 .node = node, 302 .pbus = pms->pbus_dev, 303 }; 304 305 /* Loop through all dynamic sysbus devices and create nodes for them */ 306 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 307 308 g_free(node); 309 } 310 311 static int ppce500_load_device_tree(PPCE500MachineState *pms, 312 hwaddr addr, 313 hwaddr initrd_base, 314 hwaddr initrd_size, 315 hwaddr kernel_base, 316 hwaddr kernel_size, 317 bool dry_run) 318 { 319 MachineState *machine = MACHINE(pms); 320 unsigned int smp_cpus = machine->smp.cpus; 321 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 322 CPUPPCState *env = first_cpu->env_ptr; 323 int ret = -1; 324 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 325 int fdt_size; 326 void *fdt; 327 uint8_t hypercall[16]; 328 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 329 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 330 int i; 331 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 332 char *soc; 333 char *mpic; 334 uint32_t mpic_ph; 335 uint32_t msi_ph; 336 char *gutil; 337 char *pci; 338 char *msi; 339 uint32_t *pci_map = NULL; 340 int len; 341 uint32_t pci_ranges[14] = 342 { 343 0x2000000, 0x0, pmc->pci_mmio_bus_base, 344 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 345 0x0, 0x20000000, 346 347 0x1000000, 0x0, 0x0, 348 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 349 0x0, 0x10000, 350 }; 351 const char *dtb_file = machine->dtb; 352 const char *toplevel_compat = machine->dt_compatible; 353 354 if (dtb_file) { 355 char *filename; 356 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 357 if (!filename) { 358 goto out; 359 } 360 361 fdt = load_device_tree(filename, &fdt_size); 362 g_free(filename); 363 if (!fdt) { 364 goto out; 365 } 366 goto done; 367 } 368 369 fdt = create_device_tree(&fdt_size); 370 if (fdt == NULL) { 371 goto out; 372 } 373 374 /* Manipulate device tree in memory. */ 375 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 376 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 377 378 qemu_fdt_add_subnode(fdt, "/memory"); 379 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 380 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 381 sizeof(mem_reg_property)); 382 383 qemu_fdt_add_subnode(fdt, "/chosen"); 384 if (initrd_size) { 385 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 386 initrd_base); 387 if (ret < 0) { 388 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 389 } 390 391 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 392 (initrd_base + initrd_size)); 393 if (ret < 0) { 394 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 395 } 396 397 } 398 399 if (kernel_base != -1ULL) { 400 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 401 kernel_base >> 32, kernel_base, 402 kernel_size >> 32, kernel_size); 403 } 404 405 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 406 machine->kernel_cmdline); 407 if (ret < 0) 408 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 409 410 if (kvm_enabled()) { 411 /* Read out host's frequencies */ 412 clock_freq = kvmppc_get_clockfreq(); 413 tb_freq = kvmppc_get_tbfreq(); 414 415 /* indicate KVM hypercall interface */ 416 qemu_fdt_add_subnode(fdt, "/hypervisor"); 417 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 418 "linux,kvm"); 419 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 420 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 421 hypercall, sizeof(hypercall)); 422 /* if KVM supports the idle hcall, set property indicating this */ 423 if (kvmppc_get_hasidle(env)) { 424 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 425 } 426 } 427 428 /* Create CPU nodes */ 429 qemu_fdt_add_subnode(fdt, "/cpus"); 430 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 431 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 432 433 /* We need to generate the cpu nodes in reverse order, so Linux can pick 434 the first node as boot node and be happy */ 435 for (i = smp_cpus - 1; i >= 0; i--) { 436 CPUState *cpu; 437 char *cpu_name; 438 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 439 440 cpu = qemu_get_cpu(i); 441 if (cpu == NULL) { 442 continue; 443 } 444 env = cpu->env_ptr; 445 446 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 447 qemu_fdt_add_subnode(fdt, cpu_name); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 450 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 451 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 452 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 453 env->dcache_line_size); 454 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 455 env->icache_line_size); 456 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 457 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 458 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 459 if (cpu->cpu_index) { 460 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 461 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 462 "spin-table"); 463 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 464 cpu_release_addr); 465 } else { 466 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 467 } 468 g_free(cpu_name); 469 } 470 471 qemu_fdt_add_subnode(fdt, "/aliases"); 472 /* XXX These should go into their respective devices' code */ 473 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 474 qemu_fdt_add_subnode(fdt, soc); 475 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 476 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 477 sizeof(compatible_sb)); 478 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 479 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 480 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 481 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 482 MPC8544_CCSRBAR_SIZE); 483 /* XXX should contain a reasonable value */ 484 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 485 486 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 487 qemu_fdt_add_subnode(fdt, mpic); 488 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 489 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 490 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 491 0x40000); 492 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 493 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 494 mpic_ph = qemu_fdt_alloc_phandle(fdt); 495 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 496 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 497 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 498 499 /* 500 * We have to generate ser1 first, because Linux takes the first 501 * device it finds in the dt as serial output device. And we generate 502 * devices in reverse order to the dt. 503 */ 504 if (serial_hd(1)) { 505 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 506 soc, mpic, "serial1", 1, false); 507 } 508 509 if (serial_hd(0)) { 510 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 511 soc, mpic, "serial0", 0, true); 512 } 513 514 /* i2c */ 515 dt_i2c_create(fdt, soc, mpic, "i2c"); 516 517 dt_rtc_create(fdt, "i2c", "rtc"); 518 519 520 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 521 MPC8544_UTIL_OFFSET); 522 qemu_fdt_add_subnode(fdt, gutil); 523 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 524 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 525 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 526 g_free(gutil); 527 528 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 529 qemu_fdt_add_subnode(fdt, msi); 530 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 531 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 532 msi_ph = qemu_fdt_alloc_phandle(fdt); 533 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 534 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 535 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 536 0xe0, 0x0, 537 0xe1, 0x0, 538 0xe2, 0x0, 539 0xe3, 0x0, 540 0xe4, 0x0, 541 0xe5, 0x0, 542 0xe6, 0x0, 543 0xe7, 0x0); 544 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 545 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 546 g_free(msi); 547 548 pci = g_strdup_printf("/pci@%llx", 549 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 550 qemu_fdt_add_subnode(fdt, pci); 551 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 552 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 553 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 554 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 555 0x0, 0x7); 556 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 557 pmc->pci_first_slot, pmc->pci_nr_slots, 558 &len); 559 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 560 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 561 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 562 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 563 for (i = 0; i < 14; i++) { 564 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 565 } 566 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 567 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 568 qemu_fdt_setprop_cells(fdt, pci, "reg", 569 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 570 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 571 0, 0x1000); 572 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 573 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 574 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 575 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 576 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 577 g_free(pci); 578 579 if (pmc->has_mpc8xxx_gpio) { 580 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 581 } 582 g_free(soc); 583 584 if (pms->pbus_dev) { 585 platform_bus_create_devtree(pms, fdt, mpic); 586 } 587 g_free(mpic); 588 589 pmc->fixup_devtree(fdt); 590 591 if (toplevel_compat) { 592 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 593 strlen(toplevel_compat) + 1); 594 } 595 596 done: 597 if (!dry_run) { 598 qemu_fdt_dumpdtb(fdt, fdt_size); 599 cpu_physical_memory_write(addr, fdt, fdt_size); 600 } 601 ret = fdt_size; 602 g_free(fdt); 603 604 out: 605 g_free(pci_map); 606 607 return ret; 608 } 609 610 typedef struct DeviceTreeParams { 611 PPCE500MachineState *machine; 612 hwaddr addr; 613 hwaddr initrd_base; 614 hwaddr initrd_size; 615 hwaddr kernel_base; 616 hwaddr kernel_size; 617 Notifier notifier; 618 } DeviceTreeParams; 619 620 static void ppce500_reset_device_tree(void *opaque) 621 { 622 DeviceTreeParams *p = opaque; 623 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 624 p->initrd_size, p->kernel_base, p->kernel_size, 625 false); 626 } 627 628 static void ppce500_init_notify(Notifier *notifier, void *data) 629 { 630 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 631 ppce500_reset_device_tree(p); 632 } 633 634 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 635 hwaddr addr, 636 hwaddr initrd_base, 637 hwaddr initrd_size, 638 hwaddr kernel_base, 639 hwaddr kernel_size) 640 { 641 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 642 p->machine = machine; 643 p->addr = addr; 644 p->initrd_base = initrd_base; 645 p->initrd_size = initrd_size; 646 p->kernel_base = kernel_base; 647 p->kernel_size = kernel_size; 648 649 qemu_register_reset(ppce500_reset_device_tree, p); 650 p->notifier.notify = ppce500_init_notify; 651 qemu_add_machine_init_done_notifier(&p->notifier); 652 653 /* Issue the device tree loader once, so that we get the size of the blob */ 654 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 655 kernel_base, kernel_size, true); 656 } 657 658 /* Create -kernel TLB entries for BookE. */ 659 hwaddr booke206_page_size_to_tlb(uint64_t size) 660 { 661 return 63 - clz64(size / KiB); 662 } 663 664 static int booke206_initial_map_tsize(CPUPPCState *env) 665 { 666 struct boot_info *bi = env->load_info; 667 hwaddr dt_end; 668 int ps; 669 670 /* Our initial TLB entry needs to cover everything from 0 to 671 the device tree top */ 672 dt_end = bi->dt_base + bi->dt_size; 673 ps = booke206_page_size_to_tlb(dt_end) + 1; 674 if (ps & 1) { 675 /* e500v2 can only do even TLB size bits */ 676 ps++; 677 } 678 return ps; 679 } 680 681 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 682 { 683 int tsize; 684 685 tsize = booke206_initial_map_tsize(env); 686 return (1ULL << 10 << tsize); 687 } 688 689 static void mmubooke_create_initial_mapping(CPUPPCState *env) 690 { 691 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 692 hwaddr size; 693 int ps; 694 695 ps = booke206_initial_map_tsize(env); 696 size = (ps << MAS1_TSIZE_SHIFT); 697 tlb->mas1 = MAS1_VALID | size; 698 tlb->mas2 = 0; 699 tlb->mas7_3 = 0; 700 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 701 702 env->tlb_dirty = true; 703 } 704 705 static void ppce500_cpu_reset_sec(void *opaque) 706 { 707 PowerPCCPU *cpu = opaque; 708 CPUState *cs = CPU(cpu); 709 710 cpu_reset(cs); 711 712 cs->exception_index = EXCP_HLT; 713 } 714 715 static void ppce500_cpu_reset(void *opaque) 716 { 717 PowerPCCPU *cpu = opaque; 718 CPUState *cs = CPU(cpu); 719 CPUPPCState *env = &cpu->env; 720 struct boot_info *bi = env->load_info; 721 722 cpu_reset(cs); 723 724 /* Set initial guest state. */ 725 cs->halted = 0; 726 env->gpr[1] = (16 * MiB) - 8; 727 env->gpr[3] = bi->dt_base; 728 env->gpr[4] = 0; 729 env->gpr[5] = 0; 730 env->gpr[6] = EPAPR_MAGIC; 731 env->gpr[7] = mmubooke_initial_mapsize(env); 732 env->gpr[8] = 0; 733 env->gpr[9] = 0; 734 env->nip = bi->entry; 735 mmubooke_create_initial_mapping(env); 736 } 737 738 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 739 IrqLines *irqs) 740 { 741 DeviceState *dev; 742 SysBusDevice *s; 743 int i, j, k; 744 MachineState *machine = MACHINE(pms); 745 unsigned int smp_cpus = machine->smp.cpus; 746 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 747 748 dev = qdev_new(TYPE_OPENPIC); 749 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 750 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 751 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 752 753 s = SYS_BUS_DEVICE(dev); 754 sysbus_realize_and_unref(s, &error_fatal); 755 756 k = 0; 757 for (i = 0; i < smp_cpus; i++) { 758 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 759 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 760 } 761 } 762 763 return dev; 764 } 765 766 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 767 IrqLines *irqs, Error **errp) 768 { 769 DeviceState *dev; 770 CPUState *cs; 771 772 dev = qdev_new(TYPE_KVM_OPENPIC); 773 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 774 775 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 776 object_unparent(OBJECT(dev)); 777 return NULL; 778 } 779 780 CPU_FOREACH(cs) { 781 if (kvm_openpic_connect_vcpu(dev, cs)) { 782 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 783 __func__); 784 abort(); 785 } 786 } 787 788 return dev; 789 } 790 791 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 792 MemoryRegion *ccsr, 793 IrqLines *irqs) 794 { 795 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 796 DeviceState *dev = NULL; 797 SysBusDevice *s; 798 799 if (kvm_enabled()) { 800 Error *err = NULL; 801 802 if (kvm_kernel_irqchip_allowed()) { 803 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 804 } 805 if (kvm_kernel_irqchip_required() && !dev) { 806 error_reportf_err(err, 807 "kernel_irqchip requested but unavailable: "); 808 exit(1); 809 } 810 } 811 812 if (!dev) { 813 dev = ppce500_init_mpic_qemu(pms, irqs); 814 } 815 816 s = SYS_BUS_DEVICE(dev); 817 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 818 s->mmio[0].memory); 819 820 return dev; 821 } 822 823 static void ppce500_power_off(void *opaque, int line, int on) 824 { 825 if (on) { 826 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 827 } 828 } 829 830 void ppce500_init(MachineState *machine) 831 { 832 MemoryRegion *address_space_mem = get_system_memory(); 833 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 834 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 835 PCIBus *pci_bus; 836 CPUPPCState *env = NULL; 837 uint64_t loadaddr; 838 hwaddr kernel_base = -1LL; 839 int kernel_size = 0; 840 hwaddr dt_base = 0; 841 hwaddr initrd_base = 0; 842 int initrd_size = 0; 843 hwaddr cur_base = 0; 844 char *filename; 845 const char *payload_name; 846 bool kernel_as_payload; 847 hwaddr bios_entry = 0; 848 target_long payload_size; 849 struct boot_info *boot_info; 850 int dt_size; 851 int i; 852 unsigned int smp_cpus = machine->smp.cpus; 853 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 854 * 4 respectively */ 855 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 856 IrqLines *irqs; 857 DeviceState *dev, *mpicdev; 858 CPUPPCState *firstenv = NULL; 859 MemoryRegion *ccsr_addr_space; 860 SysBusDevice *s; 861 PPCE500CCSRState *ccsr; 862 I2CBus *i2c; 863 864 irqs = g_new0(IrqLines, smp_cpus); 865 for (i = 0; i < smp_cpus; i++) { 866 PowerPCCPU *cpu; 867 CPUState *cs; 868 qemu_irq *input; 869 870 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 871 env = &cpu->env; 872 cs = CPU(cpu); 873 874 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 875 error_report("MMU model %i not supported by this machine", 876 env->mmu_model); 877 exit(1); 878 } 879 880 /* 881 * Secondary CPU starts in halted state for now. Needs to change 882 * when implementing non-kernel boot. 883 */ 884 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 885 &error_fatal); 886 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 887 888 if (!firstenv) { 889 firstenv = env; 890 } 891 892 input = (qemu_irq *)env->irq_inputs; 893 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 894 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 895 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 896 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 897 898 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 899 900 /* Register reset handler */ 901 if (!i) { 902 /* Primary CPU */ 903 struct boot_info *boot_info; 904 boot_info = g_malloc0(sizeof(struct boot_info)); 905 qemu_register_reset(ppce500_cpu_reset, cpu); 906 env->load_info = boot_info; 907 } else { 908 /* Secondary CPUs */ 909 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 910 } 911 } 912 913 env = firstenv; 914 915 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 916 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 917 exit(EXIT_FAILURE); 918 } 919 920 /* Register Memory */ 921 memory_region_add_subregion(address_space_mem, 0, machine->ram); 922 923 dev = qdev_new("e500-ccsr"); 924 object_property_add_child(qdev_get_machine(), "e500-ccsr", 925 OBJECT(dev)); 926 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 927 ccsr = CCSR(dev); 928 ccsr_addr_space = &ccsr->ccsr_space; 929 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 930 ccsr_addr_space); 931 932 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 933 g_free(irqs); 934 935 /* Serial */ 936 if (serial_hd(0)) { 937 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 938 0, qdev_get_gpio_in(mpicdev, 42), 399193, 939 serial_hd(0), DEVICE_BIG_ENDIAN); 940 } 941 942 if (serial_hd(1)) { 943 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 944 0, qdev_get_gpio_in(mpicdev, 42), 399193, 945 serial_hd(1), DEVICE_BIG_ENDIAN); 946 } 947 /* I2C */ 948 dev = qdev_new("mpc-i2c"); 949 s = SYS_BUS_DEVICE(dev); 950 sysbus_realize_and_unref(s, &error_fatal); 951 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 952 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 953 sysbus_mmio_get_region(s, 0)); 954 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 955 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 956 957 958 /* General Utility device */ 959 dev = qdev_new("mpc8544-guts"); 960 s = SYS_BUS_DEVICE(dev); 961 sysbus_realize_and_unref(s, &error_fatal); 962 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 963 sysbus_mmio_get_region(s, 0)); 964 965 /* PCI */ 966 dev = qdev_new("e500-pcihost"); 967 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 968 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 969 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 970 s = SYS_BUS_DEVICE(dev); 971 sysbus_realize_and_unref(s, &error_fatal); 972 for (i = 0; i < PCI_NUM_PINS; i++) { 973 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 974 } 975 976 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 977 sysbus_mmio_get_region(s, 0)); 978 979 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 980 if (!pci_bus) 981 printf("couldn't create PCI controller!\n"); 982 983 if (pci_bus) { 984 /* Register network interfaces. */ 985 for (i = 0; i < nb_nics; i++) { 986 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 987 } 988 } 989 990 /* Register spinning region */ 991 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 992 993 if (pmc->has_mpc8xxx_gpio) { 994 qemu_irq poweroff_irq; 995 996 dev = qdev_new("mpc8xxx_gpio"); 997 s = SYS_BUS_DEVICE(dev); 998 sysbus_realize_and_unref(s, &error_fatal); 999 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 1000 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 1001 sysbus_mmio_get_region(s, 0)); 1002 1003 /* Power Off GPIO at Pin 0 */ 1004 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1005 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1006 } 1007 1008 /* Platform Bus Device */ 1009 if (pmc->has_platform_bus) { 1010 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1011 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1012 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1013 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1014 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1015 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1016 1017 s = SYS_BUS_DEVICE(pms->pbus_dev); 1018 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1019 int irqn = pmc->platform_bus_first_irq + i; 1020 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1021 } 1022 1023 memory_region_add_subregion(address_space_mem, 1024 pmc->platform_bus_base, 1025 sysbus_mmio_get_region(s, 0)); 1026 } 1027 1028 /* 1029 * Smart firmware defaults ahead! 1030 * 1031 * We follow the following table to select which payload we execute. 1032 * 1033 * -kernel | -bios | payload 1034 * ---------+-------+--------- 1035 * N | Y | u-boot 1036 * N | N | u-boot 1037 * Y | Y | u-boot 1038 * Y | N | kernel 1039 * 1040 * This ensures backwards compatibility with how we used to expose 1041 * -kernel to users but allows them to run through u-boot as well. 1042 */ 1043 kernel_as_payload = false; 1044 if (machine->firmware == NULL) { 1045 if (machine->kernel_filename) { 1046 payload_name = machine->kernel_filename; 1047 kernel_as_payload = true; 1048 } else { 1049 payload_name = "u-boot.e500"; 1050 } 1051 } else { 1052 payload_name = machine->firmware; 1053 } 1054 1055 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1056 if (!filename) { 1057 error_report("could not find firmware/kernel file '%s'", payload_name); 1058 exit(1); 1059 } 1060 1061 payload_size = load_elf(filename, NULL, NULL, NULL, 1062 &bios_entry, &loadaddr, NULL, NULL, 1063 1, PPC_ELF_MACHINE, 0, 0); 1064 if (payload_size < 0) { 1065 /* 1066 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1067 * ePAPR compliant kernel 1068 */ 1069 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1070 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1071 NULL, NULL); 1072 if (payload_size < 0) { 1073 error_report("could not load firmware '%s'", filename); 1074 exit(1); 1075 } 1076 } 1077 1078 g_free(filename); 1079 1080 if (kernel_as_payload) { 1081 kernel_base = loadaddr; 1082 kernel_size = payload_size; 1083 } 1084 1085 cur_base = loadaddr + payload_size; 1086 if (cur_base < 32 * MiB) { 1087 /* u-boot occupies memory up to 32MB, so load blobs above */ 1088 cur_base = 32 * MiB; 1089 } 1090 1091 /* Load bare kernel only if no bios/u-boot has been provided */ 1092 if (machine->kernel_filename && !kernel_as_payload) { 1093 kernel_base = cur_base; 1094 kernel_size = load_image_targphys(machine->kernel_filename, 1095 cur_base, 1096 machine->ram_size - cur_base); 1097 if (kernel_size < 0) { 1098 error_report("could not load kernel '%s'", 1099 machine->kernel_filename); 1100 exit(1); 1101 } 1102 1103 cur_base += kernel_size; 1104 } 1105 1106 /* Load initrd. */ 1107 if (machine->initrd_filename) { 1108 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1109 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1110 machine->ram_size - initrd_base); 1111 1112 if (initrd_size < 0) { 1113 error_report("could not load initial ram disk '%s'", 1114 machine->initrd_filename); 1115 exit(1); 1116 } 1117 1118 cur_base = initrd_base + initrd_size; 1119 } 1120 1121 /* 1122 * Reserve space for dtb behind the kernel image because Linux has a bug 1123 * where it can only handle the dtb if it's within the first 64MB of where 1124 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1125 * ensures enough space between kernel and initrd. 1126 */ 1127 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1128 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1129 error_report("not enough memory for device tree"); 1130 exit(1); 1131 } 1132 1133 dt_size = ppce500_prep_device_tree(pms, dt_base, 1134 initrd_base, initrd_size, 1135 kernel_base, kernel_size); 1136 if (dt_size < 0) { 1137 error_report("couldn't load device tree"); 1138 exit(1); 1139 } 1140 assert(dt_size < DTB_MAX_SIZE); 1141 1142 boot_info = env->load_info; 1143 boot_info->entry = bios_entry; 1144 boot_info->dt_base = dt_base; 1145 boot_info->dt_size = dt_size; 1146 } 1147 1148 static void e500_ccsr_initfn(Object *obj) 1149 { 1150 PPCE500CCSRState *ccsr = CCSR(obj); 1151 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1152 MPC8544_CCSRBAR_SIZE); 1153 } 1154 1155 static const TypeInfo e500_ccsr_info = { 1156 .name = TYPE_CCSR, 1157 .parent = TYPE_SYS_BUS_DEVICE, 1158 .instance_size = sizeof(PPCE500CCSRState), 1159 .instance_init = e500_ccsr_initfn, 1160 }; 1161 1162 static const TypeInfo ppce500_info = { 1163 .name = TYPE_PPCE500_MACHINE, 1164 .parent = TYPE_MACHINE, 1165 .abstract = true, 1166 .instance_size = sizeof(PPCE500MachineState), 1167 .class_size = sizeof(PPCE500MachineClass), 1168 }; 1169 1170 static void e500_register_types(void) 1171 { 1172 type_register_static(&e500_ccsr_info); 1173 type_register_static(&ppce500_info); 1174 } 1175 1176 type_init(e500_register_types) 1177