1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "e500.h" 22 #include "e500-ccsr.h" 23 #include "net/net.h" 24 #include "qemu/config-file.h" 25 #include "hw/char/serial.h" 26 #include "hw/pci/pci.h" 27 #include "hw/boards.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/reset.h" 31 #include "kvm_ppc.h" 32 #include "sysemu/device_tree.h" 33 #include "hw/ppc/openpic.h" 34 #include "hw/ppc/openpic_kvm.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/loader.h" 38 #include "elf.h" 39 #include "hw/sysbus.h" 40 #include "exec/address-spaces.h" 41 #include "qemu/host-utils.h" 42 #include "qemu/option.h" 43 #include "hw/pci-host/ppce500.h" 44 #include "qemu/error-report.h" 45 #include "hw/platform-bus.h" 46 #include "hw/net/fsl_etsec/etsec.h" 47 #include "hw/i2c/i2c.h" 48 #include "hw/irq.h" 49 50 #define EPAPR_MAGIC (0x45504150) 51 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 52 #define DTC_LOAD_PAD 0x1800000 53 #define DTC_PAD_MASK 0xFFFFF 54 #define DTB_MAX_SIZE (8 * MiB) 55 #define INITRD_LOAD_PAD 0x2000000 56 #define INITRD_PAD_MASK 0xFFFFFF 57 58 #define RAM_SIZES_ALIGN (64 * MiB) 59 60 /* TODO: parameterize */ 61 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 62 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 63 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 64 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 65 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 66 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 67 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 68 #define MPC8544_UTIL_OFFSET 0xe0000ULL 69 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 70 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 71 #define MPC8XXX_GPIO_IRQ 47 72 #define MPC8544_I2C_IRQ 43 73 #define RTC_REGS_OFFSET 0x68 74 75 struct boot_info 76 { 77 uint32_t dt_base; 78 uint32_t dt_size; 79 uint32_t entry; 80 }; 81 82 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 83 int nr_slots, int *len) 84 { 85 int i = 0; 86 int slot; 87 int pci_irq; 88 int host_irq; 89 int last_slot = first_slot + nr_slots; 90 uint32_t *pci_map; 91 92 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 93 pci_map = g_malloc(*len); 94 95 for (slot = first_slot; slot < last_slot; slot++) { 96 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 97 pci_map[i++] = cpu_to_be32(slot << 11); 98 pci_map[i++] = cpu_to_be32(0x0); 99 pci_map[i++] = cpu_to_be32(0x0); 100 pci_map[i++] = cpu_to_be32(pci_irq + 1); 101 pci_map[i++] = cpu_to_be32(mpic); 102 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 103 pci_map[i++] = cpu_to_be32(host_irq + 1); 104 pci_map[i++] = cpu_to_be32(0x1); 105 } 106 } 107 108 assert((i * sizeof(uint32_t)) == *len); 109 110 return pci_map; 111 } 112 113 static void dt_serial_create(void *fdt, unsigned long long offset, 114 const char *soc, const char *mpic, 115 const char *alias, int idx, bool defcon) 116 { 117 char *ser; 118 119 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 120 qemu_fdt_add_subnode(fdt, ser); 121 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 122 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 123 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 124 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 125 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 126 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 127 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 128 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 129 130 if (defcon) { 131 /* 132 * "linux,stdout-path" and "stdout" properties are deprecated by linux 133 * kernel. New platforms should only use the "stdout-path" property. Set 134 * the new property and continue using older property to remain 135 * compatible with the existing firmware. 136 */ 137 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 138 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 139 } 140 g_free(ser); 141 } 142 143 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 144 { 145 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 146 int irq0 = MPC8XXX_GPIO_IRQ; 147 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 148 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 149 int gpio_ph; 150 151 qemu_fdt_add_subnode(fdt, node); 152 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 153 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 154 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 155 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 156 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 157 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 158 gpio_ph = qemu_fdt_alloc_phandle(fdt); 159 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 160 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 161 162 /* Power Off Pin */ 163 qemu_fdt_add_subnode(fdt, poweroff); 164 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 165 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 166 167 g_free(node); 168 g_free(poweroff); 169 } 170 171 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 172 { 173 int offset = RTC_REGS_OFFSET; 174 175 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 176 qemu_fdt_add_subnode(fdt, rtc); 177 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 178 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 179 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 180 181 g_free(rtc); 182 } 183 184 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 185 const char *alias) 186 { 187 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 188 int irq0 = MPC8544_I2C_IRQ; 189 190 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 191 qemu_fdt_add_subnode(fdt, i2c); 192 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 193 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 194 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 195 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 196 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 197 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 198 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 199 200 g_free(i2c); 201 } 202 203 204 typedef struct PlatformDevtreeData { 205 void *fdt; 206 const char *mpic; 207 int irq_start; 208 const char *node; 209 PlatformBusDevice *pbus; 210 } PlatformDevtreeData; 211 212 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 213 { 214 eTSEC *etsec = ETSEC_COMMON(sbdev); 215 PlatformBusDevice *pbus = data->pbus; 216 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 217 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 218 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 219 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 220 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 221 gchar *group = g_strdup_printf("%s/queue-group", node); 222 void *fdt = data->fdt; 223 224 assert((int64_t)mmio0 >= 0); 225 assert(irq0 >= 0); 226 assert(irq1 >= 0); 227 assert(irq2 >= 0); 228 229 qemu_fdt_add_subnode(fdt, node); 230 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 231 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 232 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 233 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 234 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 235 236 qemu_fdt_add_subnode(fdt, group); 237 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 238 qemu_fdt_setprop_cells(fdt, group, "interrupts", 239 data->irq_start + irq0, 0x2, 240 data->irq_start + irq1, 0x2, 241 data->irq_start + irq2, 0x2); 242 243 g_free(node); 244 g_free(group); 245 246 return 0; 247 } 248 249 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 250 { 251 PlatformDevtreeData *data = opaque; 252 bool matched = false; 253 254 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 255 create_devtree_etsec(sbdev, data); 256 matched = true; 257 } 258 259 if (!matched) { 260 error_report("Device %s is not supported by this machine yet.", 261 qdev_fw_name(DEVICE(sbdev))); 262 exit(1); 263 } 264 } 265 266 static void platform_bus_create_devtree(PPCE500MachineState *pms, 267 void *fdt, const char *mpic) 268 { 269 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 270 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 271 const char platcomp[] = "qemu,platform\0simple-bus"; 272 uint64_t addr = pmc->platform_bus_base; 273 uint64_t size = pmc->platform_bus_size; 274 int irq_start = pmc->platform_bus_first_irq; 275 276 /* Create a /platform node that we can put all devices into */ 277 278 qemu_fdt_add_subnode(fdt, node); 279 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 280 281 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 282 address and size */ 283 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 284 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 285 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 286 287 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 288 289 /* Create dt nodes for dynamic devices */ 290 PlatformDevtreeData data = { 291 .fdt = fdt, 292 .mpic = mpic, 293 .irq_start = irq_start, 294 .node = node, 295 .pbus = pms->pbus_dev, 296 }; 297 298 /* Loop through all dynamic sysbus devices and create nodes for them */ 299 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 300 301 g_free(node); 302 } 303 304 static int ppce500_load_device_tree(PPCE500MachineState *pms, 305 hwaddr addr, 306 hwaddr initrd_base, 307 hwaddr initrd_size, 308 hwaddr kernel_base, 309 hwaddr kernel_size, 310 bool dry_run) 311 { 312 MachineState *machine = MACHINE(pms); 313 unsigned int smp_cpus = machine->smp.cpus; 314 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 315 CPUPPCState *env = first_cpu->env_ptr; 316 int ret = -1; 317 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 318 int fdt_size; 319 void *fdt; 320 uint8_t hypercall[16]; 321 uint32_t clock_freq = 400000000; 322 uint32_t tb_freq = 400000000; 323 int i; 324 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 325 char *soc; 326 char *mpic; 327 uint32_t mpic_ph; 328 uint32_t msi_ph; 329 char *gutil; 330 char *pci; 331 char *msi; 332 uint32_t *pci_map = NULL; 333 int len; 334 uint32_t pci_ranges[14] = 335 { 336 0x2000000, 0x0, pmc->pci_mmio_bus_base, 337 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 338 0x0, 0x20000000, 339 340 0x1000000, 0x0, 0x0, 341 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 342 0x0, 0x10000, 343 }; 344 QemuOpts *machine_opts = qemu_get_machine_opts(); 345 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 346 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 347 348 if (dtb_file) { 349 char *filename; 350 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 351 if (!filename) { 352 goto out; 353 } 354 355 fdt = load_device_tree(filename, &fdt_size); 356 g_free(filename); 357 if (!fdt) { 358 goto out; 359 } 360 goto done; 361 } 362 363 fdt = create_device_tree(&fdt_size); 364 if (fdt == NULL) { 365 goto out; 366 } 367 368 /* Manipulate device tree in memory. */ 369 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 370 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 371 372 qemu_fdt_add_subnode(fdt, "/memory"); 373 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 374 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 375 sizeof(mem_reg_property)); 376 377 qemu_fdt_add_subnode(fdt, "/chosen"); 378 if (initrd_size) { 379 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 380 initrd_base); 381 if (ret < 0) { 382 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 383 } 384 385 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 386 (initrd_base + initrd_size)); 387 if (ret < 0) { 388 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 389 } 390 391 } 392 393 if (kernel_base != -1ULL) { 394 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 395 kernel_base >> 32, kernel_base, 396 kernel_size >> 32, kernel_size); 397 } 398 399 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 400 machine->kernel_cmdline); 401 if (ret < 0) 402 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 403 404 if (kvm_enabled()) { 405 /* Read out host's frequencies */ 406 clock_freq = kvmppc_get_clockfreq(); 407 tb_freq = kvmppc_get_tbfreq(); 408 409 /* indicate KVM hypercall interface */ 410 qemu_fdt_add_subnode(fdt, "/hypervisor"); 411 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 412 "linux,kvm"); 413 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 414 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 415 hypercall, sizeof(hypercall)); 416 /* if KVM supports the idle hcall, set property indicating this */ 417 if (kvmppc_get_hasidle(env)) { 418 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 419 } 420 } 421 422 /* Create CPU nodes */ 423 qemu_fdt_add_subnode(fdt, "/cpus"); 424 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 425 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 426 427 /* We need to generate the cpu nodes in reverse order, so Linux can pick 428 the first node as boot node and be happy */ 429 for (i = smp_cpus - 1; i >= 0; i--) { 430 CPUState *cpu; 431 char *cpu_name; 432 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 433 434 cpu = qemu_get_cpu(i); 435 if (cpu == NULL) { 436 continue; 437 } 438 env = cpu->env_ptr; 439 440 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 441 qemu_fdt_add_subnode(fdt, cpu_name); 442 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 443 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 444 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 445 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 447 env->dcache_line_size); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 449 env->icache_line_size); 450 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 451 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 452 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 453 if (cpu->cpu_index) { 454 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 455 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 456 "spin-table"); 457 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 458 cpu_release_addr); 459 } else { 460 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 461 } 462 g_free(cpu_name); 463 } 464 465 qemu_fdt_add_subnode(fdt, "/aliases"); 466 /* XXX These should go into their respective devices' code */ 467 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 468 qemu_fdt_add_subnode(fdt, soc); 469 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 470 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 471 sizeof(compatible_sb)); 472 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 473 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 474 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 475 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 476 MPC8544_CCSRBAR_SIZE); 477 /* XXX should contain a reasonable value */ 478 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 479 480 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 481 qemu_fdt_add_subnode(fdt, mpic); 482 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 483 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 484 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 485 0x40000); 486 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 487 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 488 mpic_ph = qemu_fdt_alloc_phandle(fdt); 489 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 490 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 491 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 492 493 /* 494 * We have to generate ser1 first, because Linux takes the first 495 * device it finds in the dt as serial output device. And we generate 496 * devices in reverse order to the dt. 497 */ 498 if (serial_hd(1)) { 499 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 500 soc, mpic, "serial1", 1, false); 501 } 502 503 if (serial_hd(0)) { 504 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 505 soc, mpic, "serial0", 0, true); 506 } 507 508 /* i2c */ 509 dt_i2c_create(fdt, soc, mpic, "i2c"); 510 511 dt_rtc_create(fdt, "i2c", "rtc"); 512 513 514 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 515 MPC8544_UTIL_OFFSET); 516 qemu_fdt_add_subnode(fdt, gutil); 517 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 518 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 519 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 520 g_free(gutil); 521 522 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 523 qemu_fdt_add_subnode(fdt, msi); 524 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 525 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 526 msi_ph = qemu_fdt_alloc_phandle(fdt); 527 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 528 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 529 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 530 0xe0, 0x0, 531 0xe1, 0x0, 532 0xe2, 0x0, 533 0xe3, 0x0, 534 0xe4, 0x0, 535 0xe5, 0x0, 536 0xe6, 0x0, 537 0xe7, 0x0); 538 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 539 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 540 g_free(msi); 541 542 pci = g_strdup_printf("/pci@%llx", 543 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 544 qemu_fdt_add_subnode(fdt, pci); 545 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 546 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 547 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 548 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 549 0x0, 0x7); 550 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 551 pmc->pci_first_slot, pmc->pci_nr_slots, 552 &len); 553 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 554 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 555 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 556 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 557 for (i = 0; i < 14; i++) { 558 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 559 } 560 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 561 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 562 qemu_fdt_setprop_cells(fdt, pci, "reg", 563 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 564 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 565 0, 0x1000); 566 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 567 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 568 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 569 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 570 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 571 g_free(pci); 572 573 if (pmc->has_mpc8xxx_gpio) { 574 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 575 } 576 g_free(soc); 577 578 if (pms->pbus_dev) { 579 platform_bus_create_devtree(pms, fdt, mpic); 580 } 581 g_free(mpic); 582 583 pmc->fixup_devtree(fdt); 584 585 if (toplevel_compat) { 586 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 587 strlen(toplevel_compat) + 1); 588 } 589 590 done: 591 if (!dry_run) { 592 qemu_fdt_dumpdtb(fdt, fdt_size); 593 cpu_physical_memory_write(addr, fdt, fdt_size); 594 } 595 ret = fdt_size; 596 597 out: 598 g_free(pci_map); 599 600 return ret; 601 } 602 603 typedef struct DeviceTreeParams { 604 PPCE500MachineState *machine; 605 hwaddr addr; 606 hwaddr initrd_base; 607 hwaddr initrd_size; 608 hwaddr kernel_base; 609 hwaddr kernel_size; 610 Notifier notifier; 611 } DeviceTreeParams; 612 613 static void ppce500_reset_device_tree(void *opaque) 614 { 615 DeviceTreeParams *p = opaque; 616 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 617 p->initrd_size, p->kernel_base, p->kernel_size, 618 false); 619 } 620 621 static void ppce500_init_notify(Notifier *notifier, void *data) 622 { 623 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 624 ppce500_reset_device_tree(p); 625 } 626 627 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 628 hwaddr addr, 629 hwaddr initrd_base, 630 hwaddr initrd_size, 631 hwaddr kernel_base, 632 hwaddr kernel_size) 633 { 634 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 635 p->machine = machine; 636 p->addr = addr; 637 p->initrd_base = initrd_base; 638 p->initrd_size = initrd_size; 639 p->kernel_base = kernel_base; 640 p->kernel_size = kernel_size; 641 642 qemu_register_reset(ppce500_reset_device_tree, p); 643 p->notifier.notify = ppce500_init_notify; 644 qemu_add_machine_init_done_notifier(&p->notifier); 645 646 /* Issue the device tree loader once, so that we get the size of the blob */ 647 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 648 kernel_base, kernel_size, true); 649 } 650 651 /* Create -kernel TLB entries for BookE. */ 652 hwaddr booke206_page_size_to_tlb(uint64_t size) 653 { 654 return 63 - clz64(size / KiB); 655 } 656 657 static int booke206_initial_map_tsize(CPUPPCState *env) 658 { 659 struct boot_info *bi = env->load_info; 660 hwaddr dt_end; 661 int ps; 662 663 /* Our initial TLB entry needs to cover everything from 0 to 664 the device tree top */ 665 dt_end = bi->dt_base + bi->dt_size; 666 ps = booke206_page_size_to_tlb(dt_end) + 1; 667 if (ps & 1) { 668 /* e500v2 can only do even TLB size bits */ 669 ps++; 670 } 671 return ps; 672 } 673 674 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 675 { 676 int tsize; 677 678 tsize = booke206_initial_map_tsize(env); 679 return (1ULL << 10 << tsize); 680 } 681 682 static void mmubooke_create_initial_mapping(CPUPPCState *env) 683 { 684 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 685 hwaddr size; 686 int ps; 687 688 ps = booke206_initial_map_tsize(env); 689 size = (ps << MAS1_TSIZE_SHIFT); 690 tlb->mas1 = MAS1_VALID | size; 691 tlb->mas2 = 0; 692 tlb->mas7_3 = 0; 693 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 694 695 env->tlb_dirty = true; 696 } 697 698 static void ppce500_cpu_reset_sec(void *opaque) 699 { 700 PowerPCCPU *cpu = opaque; 701 CPUState *cs = CPU(cpu); 702 703 cpu_reset(cs); 704 705 /* Secondary CPU starts in halted state for now. Needs to change when 706 implementing non-kernel boot. */ 707 cs->halted = 1; 708 cs->exception_index = EXCP_HLT; 709 } 710 711 static void ppce500_cpu_reset(void *opaque) 712 { 713 PowerPCCPU *cpu = opaque; 714 CPUState *cs = CPU(cpu); 715 CPUPPCState *env = &cpu->env; 716 struct boot_info *bi = env->load_info; 717 718 cpu_reset(cs); 719 720 /* Set initial guest state. */ 721 cs->halted = 0; 722 env->gpr[1] = (16 * MiB) - 8; 723 env->gpr[3] = bi->dt_base; 724 env->gpr[4] = 0; 725 env->gpr[5] = 0; 726 env->gpr[6] = EPAPR_MAGIC; 727 env->gpr[7] = mmubooke_initial_mapsize(env); 728 env->gpr[8] = 0; 729 env->gpr[9] = 0; 730 env->nip = bi->entry; 731 mmubooke_create_initial_mapping(env); 732 } 733 734 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 735 IrqLines *irqs) 736 { 737 DeviceState *dev; 738 SysBusDevice *s; 739 int i, j, k; 740 MachineState *machine = MACHINE(pms); 741 unsigned int smp_cpus = machine->smp.cpus; 742 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 743 744 dev = qdev_create(NULL, TYPE_OPENPIC); 745 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 746 &error_fatal); 747 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 748 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 749 750 qdev_init_nofail(dev); 751 s = SYS_BUS_DEVICE(dev); 752 753 k = 0; 754 for (i = 0; i < smp_cpus; i++) { 755 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 756 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 757 } 758 } 759 760 return dev; 761 } 762 763 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 764 IrqLines *irqs, Error **errp) 765 { 766 Error *err = NULL; 767 DeviceState *dev; 768 CPUState *cs; 769 770 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 771 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 772 773 object_property_set_bool(OBJECT(dev), true, "realized", &err); 774 if (err) { 775 error_propagate(errp, err); 776 object_unparent(OBJECT(dev)); 777 return NULL; 778 } 779 780 CPU_FOREACH(cs) { 781 if (kvm_openpic_connect_vcpu(dev, cs)) { 782 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 783 __func__); 784 abort(); 785 } 786 } 787 788 return dev; 789 } 790 791 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 792 MemoryRegion *ccsr, 793 IrqLines *irqs) 794 { 795 MachineState *machine = MACHINE(pms); 796 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 797 DeviceState *dev = NULL; 798 SysBusDevice *s; 799 800 if (kvm_enabled()) { 801 Error *err = NULL; 802 803 if (machine_kernel_irqchip_allowed(machine)) { 804 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 805 } 806 if (machine_kernel_irqchip_required(machine) && !dev) { 807 error_reportf_err(err, 808 "kernel_irqchip requested but unavailable: "); 809 exit(1); 810 } 811 } 812 813 if (!dev) { 814 dev = ppce500_init_mpic_qemu(pms, irqs); 815 } 816 817 s = SYS_BUS_DEVICE(dev); 818 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 819 s->mmio[0].memory); 820 821 return dev; 822 } 823 824 static void ppce500_power_off(void *opaque, int line, int on) 825 { 826 if (on) { 827 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 828 } 829 } 830 831 void ppce500_init(MachineState *machine) 832 { 833 MemoryRegion *address_space_mem = get_system_memory(); 834 MemoryRegion *ram = g_new(MemoryRegion, 1); 835 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 836 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 837 PCIBus *pci_bus; 838 CPUPPCState *env = NULL; 839 uint64_t loadaddr; 840 hwaddr kernel_base = -1LL; 841 int kernel_size = 0; 842 hwaddr dt_base = 0; 843 hwaddr initrd_base = 0; 844 int initrd_size = 0; 845 hwaddr cur_base = 0; 846 char *filename; 847 const char *payload_name; 848 bool kernel_as_payload; 849 hwaddr bios_entry = 0; 850 target_long payload_size; 851 struct boot_info *boot_info; 852 int dt_size; 853 int i; 854 unsigned int smp_cpus = machine->smp.cpus; 855 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 856 * 4 respectively */ 857 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 858 IrqLines *irqs; 859 DeviceState *dev, *mpicdev; 860 CPUPPCState *firstenv = NULL; 861 MemoryRegion *ccsr_addr_space; 862 SysBusDevice *s; 863 PPCE500CCSRState *ccsr; 864 I2CBus *i2c; 865 866 irqs = g_new0(IrqLines, smp_cpus); 867 for (i = 0; i < smp_cpus; i++) { 868 PowerPCCPU *cpu; 869 CPUState *cs; 870 qemu_irq *input; 871 872 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 873 env = &cpu->env; 874 cs = CPU(cpu); 875 876 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 877 error_report("MMU model %i not supported by this machine", 878 env->mmu_model); 879 exit(1); 880 } 881 882 if (!firstenv) { 883 firstenv = env; 884 } 885 886 input = (qemu_irq *)env->irq_inputs; 887 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 888 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 889 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 890 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 891 892 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 893 894 /* Register reset handler */ 895 if (!i) { 896 /* Primary CPU */ 897 struct boot_info *boot_info; 898 boot_info = g_malloc0(sizeof(struct boot_info)); 899 qemu_register_reset(ppce500_cpu_reset, cpu); 900 env->load_info = boot_info; 901 } else { 902 /* Secondary CPUs */ 903 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 904 } 905 } 906 907 env = firstenv; 908 909 /* Fixup Memory size on a alignment boundary */ 910 ram_size &= ~(RAM_SIZES_ALIGN - 1); 911 machine->ram_size = ram_size; 912 913 /* Register Memory */ 914 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 915 memory_region_add_subregion(address_space_mem, 0, ram); 916 917 dev = qdev_create(NULL, "e500-ccsr"); 918 object_property_add_child(qdev_get_machine(), "e500-ccsr", 919 OBJECT(dev), NULL); 920 qdev_init_nofail(dev); 921 ccsr = CCSR(dev); 922 ccsr_addr_space = &ccsr->ccsr_space; 923 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 924 ccsr_addr_space); 925 926 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 927 928 /* Serial */ 929 if (serial_hd(0)) { 930 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 931 0, qdev_get_gpio_in(mpicdev, 42), 399193, 932 serial_hd(0), DEVICE_BIG_ENDIAN); 933 } 934 935 if (serial_hd(1)) { 936 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 937 0, qdev_get_gpio_in(mpicdev, 42), 399193, 938 serial_hd(1), DEVICE_BIG_ENDIAN); 939 } 940 /* I2C */ 941 dev = qdev_create(NULL, "mpc-i2c"); 942 s = SYS_BUS_DEVICE(dev); 943 qdev_init_nofail(dev); 944 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 945 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 946 sysbus_mmio_get_region(s, 0)); 947 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 948 i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET); 949 950 951 /* General Utility device */ 952 dev = qdev_create(NULL, "mpc8544-guts"); 953 qdev_init_nofail(dev); 954 s = SYS_BUS_DEVICE(dev); 955 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 956 sysbus_mmio_get_region(s, 0)); 957 958 /* PCI */ 959 dev = qdev_create(NULL, "e500-pcihost"); 960 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 961 &error_abort); 962 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 963 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 964 qdev_init_nofail(dev); 965 s = SYS_BUS_DEVICE(dev); 966 for (i = 0; i < PCI_NUM_PINS; i++) { 967 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 968 } 969 970 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 971 sysbus_mmio_get_region(s, 0)); 972 973 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 974 if (!pci_bus) 975 printf("couldn't create PCI controller!\n"); 976 977 if (pci_bus) { 978 /* Register network interfaces. */ 979 for (i = 0; i < nb_nics; i++) { 980 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 981 } 982 } 983 984 /* Register spinning region */ 985 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 986 987 if (pmc->has_mpc8xxx_gpio) { 988 qemu_irq poweroff_irq; 989 990 dev = qdev_create(NULL, "mpc8xxx_gpio"); 991 s = SYS_BUS_DEVICE(dev); 992 qdev_init_nofail(dev); 993 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 994 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 995 sysbus_mmio_get_region(s, 0)); 996 997 /* Power Off GPIO at Pin 0 */ 998 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 999 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1000 } 1001 1002 /* Platform Bus Device */ 1003 if (pmc->has_platform_bus) { 1004 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1005 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1006 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1007 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1008 qdev_init_nofail(dev); 1009 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1010 1011 s = SYS_BUS_DEVICE(pms->pbus_dev); 1012 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1013 int irqn = pmc->platform_bus_first_irq + i; 1014 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1015 } 1016 1017 memory_region_add_subregion(address_space_mem, 1018 pmc->platform_bus_base, 1019 sysbus_mmio_get_region(s, 0)); 1020 } 1021 1022 /* 1023 * Smart firmware defaults ahead! 1024 * 1025 * We follow the following table to select which payload we execute. 1026 * 1027 * -kernel | -bios | payload 1028 * ---------+-------+--------- 1029 * N | Y | u-boot 1030 * N | N | u-boot 1031 * Y | Y | u-boot 1032 * Y | N | kernel 1033 * 1034 * This ensures backwards compatibility with how we used to expose 1035 * -kernel to users but allows them to run through u-boot as well. 1036 */ 1037 kernel_as_payload = false; 1038 if (bios_name == NULL) { 1039 if (machine->kernel_filename) { 1040 payload_name = machine->kernel_filename; 1041 kernel_as_payload = true; 1042 } else { 1043 payload_name = "u-boot.e500"; 1044 } 1045 } else { 1046 payload_name = bios_name; 1047 } 1048 1049 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1050 1051 payload_size = load_elf(filename, NULL, NULL, NULL, 1052 &bios_entry, &loadaddr, NULL, 1053 1, PPC_ELF_MACHINE, 0, 0); 1054 if (payload_size < 0) { 1055 /* 1056 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1057 * ePAPR compliant kernel 1058 */ 1059 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1060 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1061 NULL, NULL); 1062 if (payload_size < 0) { 1063 error_report("could not load firmware '%s'", filename); 1064 exit(1); 1065 } 1066 } 1067 1068 g_free(filename); 1069 1070 if (kernel_as_payload) { 1071 kernel_base = loadaddr; 1072 kernel_size = payload_size; 1073 } 1074 1075 cur_base = loadaddr + payload_size; 1076 if (cur_base < 32 * MiB) { 1077 /* u-boot occupies memory up to 32MB, so load blobs above */ 1078 cur_base = 32 * MiB; 1079 } 1080 1081 /* Load bare kernel only if no bios/u-boot has been provided */ 1082 if (machine->kernel_filename && !kernel_as_payload) { 1083 kernel_base = cur_base; 1084 kernel_size = load_image_targphys(machine->kernel_filename, 1085 cur_base, 1086 ram_size - cur_base); 1087 if (kernel_size < 0) { 1088 error_report("could not load kernel '%s'", 1089 machine->kernel_filename); 1090 exit(1); 1091 } 1092 1093 cur_base += kernel_size; 1094 } 1095 1096 /* Load initrd. */ 1097 if (machine->initrd_filename) { 1098 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1099 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1100 ram_size - initrd_base); 1101 1102 if (initrd_size < 0) { 1103 error_report("could not load initial ram disk '%s'", 1104 machine->initrd_filename); 1105 exit(1); 1106 } 1107 1108 cur_base = initrd_base + initrd_size; 1109 } 1110 1111 /* 1112 * Reserve space for dtb behind the kernel image because Linux has a bug 1113 * where it can only handle the dtb if it's within the first 64MB of where 1114 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1115 * ensures enough space between kernel and initrd. 1116 */ 1117 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1118 if (dt_base + DTB_MAX_SIZE > ram_size) { 1119 error_report("not enough memory for device tree"); 1120 exit(1); 1121 } 1122 1123 dt_size = ppce500_prep_device_tree(pms, dt_base, 1124 initrd_base, initrd_size, 1125 kernel_base, kernel_size); 1126 if (dt_size < 0) { 1127 error_report("couldn't load device tree"); 1128 exit(1); 1129 } 1130 assert(dt_size < DTB_MAX_SIZE); 1131 1132 boot_info = env->load_info; 1133 boot_info->entry = bios_entry; 1134 boot_info->dt_base = dt_base; 1135 boot_info->dt_size = dt_size; 1136 } 1137 1138 static void e500_ccsr_initfn(Object *obj) 1139 { 1140 PPCE500CCSRState *ccsr = CCSR(obj); 1141 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1142 MPC8544_CCSRBAR_SIZE); 1143 } 1144 1145 static const TypeInfo e500_ccsr_info = { 1146 .name = TYPE_CCSR, 1147 .parent = TYPE_SYS_BUS_DEVICE, 1148 .instance_size = sizeof(PPCE500CCSRState), 1149 .instance_init = e500_ccsr_initfn, 1150 }; 1151 1152 static const TypeInfo ppce500_info = { 1153 .name = TYPE_PPCE500_MACHINE, 1154 .parent = TYPE_MACHINE, 1155 .abstract = true, 1156 .instance_size = sizeof(PPCE500MachineState), 1157 .class_size = sizeof(PPCE500MachineClass), 1158 }; 1159 1160 static void e500_register_types(void) 1161 { 1162 type_register_static(&e500_ccsr_info); 1163 type_register_static(&ppce500_info); 1164 } 1165 1166 type_init(e500_register_types) 1167