1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu/datadir.h" 19 #include "qemu/units.h" 20 #include "qemu/guest-random.h" 21 #include "qapi/error.h" 22 #include "e500.h" 23 #include "e500-ccsr.h" 24 #include "net/net.h" 25 #include "qemu/config-file.h" 26 #include "hw/char/serial.h" 27 #include "hw/pci/pci.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/reset.h" 31 #include "sysemu/runstate.h" 32 #include "kvm_ppc.h" 33 #include "sysemu/device_tree.h" 34 #include "hw/ppc/openpic.h" 35 #include "hw/ppc/openpic_kvm.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "hw/sysbus.h" 41 #include "qemu/host-utils.h" 42 #include "qemu/option.h" 43 #include "hw/pci-host/ppce500.h" 44 #include "qemu/error-report.h" 45 #include "hw/platform-bus.h" 46 #include "hw/net/fsl_etsec/etsec.h" 47 #include "hw/i2c/i2c.h" 48 #include "hw/irq.h" 49 50 #define EPAPR_MAGIC (0x45504150) 51 #define DTC_LOAD_PAD 0x1800000 52 #define DTC_PAD_MASK 0xFFFFF 53 #define DTB_MAX_SIZE (8 * MiB) 54 #define INITRD_LOAD_PAD 0x2000000 55 #define INITRD_PAD_MASK 0xFFFFFF 56 57 #define RAM_SIZES_ALIGN (64 * MiB) 58 59 /* TODO: parameterize */ 60 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 61 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 62 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 63 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 64 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 65 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 66 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 67 #define MPC8544_UTIL_OFFSET 0xe0000ULL 68 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 69 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 70 #define MPC8XXX_GPIO_IRQ 47 71 #define MPC8544_I2C_IRQ 43 72 #define RTC_REGS_OFFSET 0x68 73 74 #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) 75 76 struct boot_info 77 { 78 uint32_t dt_base; 79 uint32_t dt_size; 80 uint32_t entry; 81 }; 82 83 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 84 int nr_slots, int *len) 85 { 86 int i = 0; 87 int slot; 88 int pci_irq; 89 int host_irq; 90 int last_slot = first_slot + nr_slots; 91 uint32_t *pci_map; 92 93 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 94 pci_map = g_malloc(*len); 95 96 for (slot = first_slot; slot < last_slot; slot++) { 97 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 98 pci_map[i++] = cpu_to_be32(slot << 11); 99 pci_map[i++] = cpu_to_be32(0x0); 100 pci_map[i++] = cpu_to_be32(0x0); 101 pci_map[i++] = cpu_to_be32(pci_irq + 1); 102 pci_map[i++] = cpu_to_be32(mpic); 103 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 104 pci_map[i++] = cpu_to_be32(host_irq + 1); 105 pci_map[i++] = cpu_to_be32(0x1); 106 } 107 } 108 109 assert((i * sizeof(uint32_t)) == *len); 110 111 return pci_map; 112 } 113 114 static void dt_serial_create(void *fdt, unsigned long long offset, 115 const char *soc, const char *mpic, 116 const char *alias, int idx, bool defcon) 117 { 118 char *ser; 119 120 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 121 qemu_fdt_add_subnode(fdt, ser); 122 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 123 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 124 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 125 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 126 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ); 127 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 128 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 129 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 130 131 if (defcon) { 132 /* 133 * "linux,stdout-path" and "stdout" properties are deprecated by linux 134 * kernel. New platforms should only use the "stdout-path" property. Set 135 * the new property and continue using older property to remain 136 * compatible with the existing firmware. 137 */ 138 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 139 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 140 } 141 g_free(ser); 142 } 143 144 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 145 { 146 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 147 int irq0 = MPC8XXX_GPIO_IRQ; 148 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 149 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 150 int gpio_ph; 151 152 qemu_fdt_add_subnode(fdt, node); 153 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 154 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 155 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 156 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 157 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 158 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 159 gpio_ph = qemu_fdt_alloc_phandle(fdt); 160 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 161 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 162 163 /* Power Off Pin */ 164 qemu_fdt_add_subnode(fdt, poweroff); 165 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 166 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 167 168 g_free(node); 169 g_free(poweroff); 170 } 171 172 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 173 { 174 int offset = RTC_REGS_OFFSET; 175 176 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 177 qemu_fdt_add_subnode(fdt, rtc); 178 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 179 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 180 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 181 182 g_free(rtc); 183 } 184 185 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 186 const char *alias) 187 { 188 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 189 int irq0 = MPC8544_I2C_IRQ; 190 191 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 192 qemu_fdt_add_subnode(fdt, i2c); 193 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 194 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 195 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 196 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 197 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 198 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 199 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 200 201 g_free(i2c); 202 } 203 204 205 typedef struct PlatformDevtreeData { 206 void *fdt; 207 const char *mpic; 208 int irq_start; 209 const char *node; 210 PlatformBusDevice *pbus; 211 } PlatformDevtreeData; 212 213 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 214 { 215 eTSEC *etsec = ETSEC_COMMON(sbdev); 216 PlatformBusDevice *pbus = data->pbus; 217 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 218 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 219 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 220 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 221 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 222 gchar *group = g_strdup_printf("%s/queue-group", node); 223 void *fdt = data->fdt; 224 225 assert((int64_t)mmio0 >= 0); 226 assert(irq0 >= 0); 227 assert(irq1 >= 0); 228 assert(irq2 >= 0); 229 230 qemu_fdt_add_subnode(fdt, node); 231 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0); 232 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 233 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 234 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 235 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 236 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 237 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 238 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 239 240 qemu_fdt_add_subnode(fdt, group); 241 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 242 qemu_fdt_setprop_cells(fdt, group, "interrupts", 243 data->irq_start + irq0, 0x2, 244 data->irq_start + irq1, 0x2, 245 data->irq_start + irq2, 0x2); 246 247 g_free(node); 248 g_free(group); 249 250 return 0; 251 } 252 253 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 254 { 255 PlatformDevtreeData *data = opaque; 256 bool matched = false; 257 258 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 259 create_devtree_etsec(sbdev, data); 260 matched = true; 261 } 262 263 if (!matched) { 264 error_report("Device %s is not supported by this machine yet.", 265 qdev_fw_name(DEVICE(sbdev))); 266 exit(1); 267 } 268 } 269 270 static void platform_bus_create_devtree(PPCE500MachineState *pms, 271 void *fdt, const char *mpic) 272 { 273 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 274 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 275 const char platcomp[] = "qemu,platform\0simple-bus"; 276 uint64_t addr = pmc->platform_bus_base; 277 uint64_t size = pmc->platform_bus_size; 278 int irq_start = pmc->platform_bus_first_irq; 279 280 /* Create a /platform node that we can put all devices into */ 281 282 qemu_fdt_add_subnode(fdt, node); 283 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 284 285 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 286 address and size */ 287 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 288 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 289 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 290 291 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 292 293 /* Create dt nodes for dynamic devices */ 294 PlatformDevtreeData data = { 295 .fdt = fdt, 296 .mpic = mpic, 297 .irq_start = irq_start, 298 .node = node, 299 .pbus = pms->pbus_dev, 300 }; 301 302 /* Loop through all dynamic sysbus devices and create nodes for them */ 303 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 304 305 g_free(node); 306 } 307 308 static int ppce500_load_device_tree(PPCE500MachineState *pms, 309 hwaddr addr, 310 hwaddr initrd_base, 311 hwaddr initrd_size, 312 hwaddr kernel_base, 313 hwaddr kernel_size, 314 bool dry_run) 315 { 316 MachineState *machine = MACHINE(pms); 317 unsigned int smp_cpus = machine->smp.cpus; 318 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 319 CPUPPCState *env = first_cpu->env_ptr; 320 int ret = -1; 321 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 322 int fdt_size; 323 void *fdt; 324 uint8_t hypercall[16]; 325 uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ; 326 uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ; 327 int i; 328 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 329 char *soc; 330 char *mpic; 331 uint32_t mpic_ph; 332 uint32_t msi_ph; 333 char *gutil; 334 char *pci; 335 char *msi; 336 uint32_t *pci_map = NULL; 337 int len; 338 uint32_t pci_ranges[14] = 339 { 340 0x2000000, 0x0, pmc->pci_mmio_bus_base, 341 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 342 0x0, 0x20000000, 343 344 0x1000000, 0x0, 0x0, 345 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 346 0x0, 0x10000, 347 }; 348 const char *dtb_file = machine->dtb; 349 const char *toplevel_compat = machine->dt_compatible; 350 uint8_t rng_seed[32]; 351 352 if (dtb_file) { 353 char *filename; 354 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 355 if (!filename) { 356 goto out; 357 } 358 359 fdt = load_device_tree(filename, &fdt_size); 360 g_free(filename); 361 if (!fdt) { 362 goto out; 363 } 364 goto done; 365 } 366 367 fdt = create_device_tree(&fdt_size); 368 if (fdt == NULL) { 369 goto out; 370 } 371 372 /* Manipulate device tree in memory. */ 373 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 374 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 375 376 qemu_fdt_add_subnode(fdt, "/memory"); 377 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 378 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 379 sizeof(mem_reg_property)); 380 381 qemu_fdt_add_subnode(fdt, "/chosen"); 382 if (initrd_size) { 383 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 384 initrd_base); 385 if (ret < 0) { 386 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 387 } 388 389 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 390 (initrd_base + initrd_size)); 391 if (ret < 0) { 392 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 393 } 394 395 } 396 397 if (kernel_base != -1ULL) { 398 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 399 kernel_base >> 32, kernel_base, 400 kernel_size >> 32, kernel_size); 401 } 402 403 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 404 machine->kernel_cmdline); 405 if (ret < 0) 406 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 407 408 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 409 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 410 411 if (kvm_enabled()) { 412 /* Read out host's frequencies */ 413 clock_freq = kvmppc_get_clockfreq(); 414 tb_freq = kvmppc_get_tbfreq(); 415 416 /* indicate KVM hypercall interface */ 417 qemu_fdt_add_subnode(fdt, "/hypervisor"); 418 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 419 "linux,kvm"); 420 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 421 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 422 hypercall, sizeof(hypercall)); 423 /* if KVM supports the idle hcall, set property indicating this */ 424 if (kvmppc_get_hasidle(env)) { 425 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 426 } 427 } 428 429 /* Create CPU nodes */ 430 qemu_fdt_add_subnode(fdt, "/cpus"); 431 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 432 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 433 434 /* We need to generate the cpu nodes in reverse order, so Linux can pick 435 the first node as boot node and be happy */ 436 for (i = smp_cpus - 1; i >= 0; i--) { 437 CPUState *cpu; 438 char *cpu_name; 439 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 440 441 cpu = qemu_get_cpu(i); 442 if (cpu == NULL) { 443 continue; 444 } 445 env = cpu->env_ptr; 446 447 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 448 qemu_fdt_add_subnode(fdt, cpu_name); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 450 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 451 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 452 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 453 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 454 env->dcache_line_size); 455 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 456 env->icache_line_size); 457 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 458 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 459 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 460 if (cpu->cpu_index) { 461 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 462 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 463 "spin-table"); 464 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 465 cpu_release_addr); 466 } else { 467 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 468 } 469 g_free(cpu_name); 470 } 471 472 qemu_fdt_add_subnode(fdt, "/aliases"); 473 /* XXX These should go into their respective devices' code */ 474 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 475 qemu_fdt_add_subnode(fdt, soc); 476 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 477 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 478 sizeof(compatible_sb)); 479 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 480 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 481 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 482 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 483 MPC8544_CCSRBAR_SIZE); 484 /* XXX should contain a reasonable value */ 485 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 486 487 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 488 qemu_fdt_add_subnode(fdt, mpic); 489 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 490 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 491 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 492 0x40000); 493 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 494 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 495 mpic_ph = qemu_fdt_alloc_phandle(fdt); 496 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 497 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 498 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 499 500 /* 501 * We have to generate ser1 first, because Linux takes the first 502 * device it finds in the dt as serial output device. And we generate 503 * devices in reverse order to the dt. 504 */ 505 if (serial_hd(1)) { 506 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 507 soc, mpic, "serial1", 1, false); 508 } 509 510 if (serial_hd(0)) { 511 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 512 soc, mpic, "serial0", 0, true); 513 } 514 515 /* i2c */ 516 dt_i2c_create(fdt, soc, mpic, "i2c"); 517 518 dt_rtc_create(fdt, "i2c", "rtc"); 519 520 521 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 522 MPC8544_UTIL_OFFSET); 523 qemu_fdt_add_subnode(fdt, gutil); 524 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 525 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 526 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 527 g_free(gutil); 528 529 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 530 qemu_fdt_add_subnode(fdt, msi); 531 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 532 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 533 msi_ph = qemu_fdt_alloc_phandle(fdt); 534 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 535 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 536 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 537 0xe0, 0x0, 538 0xe1, 0x0, 539 0xe2, 0x0, 540 0xe3, 0x0, 541 0xe4, 0x0, 542 0xe5, 0x0, 543 0xe6, 0x0, 544 0xe7, 0x0); 545 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 546 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 547 g_free(msi); 548 549 pci = g_strdup_printf("/pci@%llx", 550 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 551 qemu_fdt_add_subnode(fdt, pci); 552 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 553 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 554 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 555 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 556 0x0, 0x7); 557 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 558 pmc->pci_first_slot, pmc->pci_nr_slots, 559 &len); 560 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 561 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 562 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 563 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 564 for (i = 0; i < 14; i++) { 565 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 566 } 567 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 568 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 569 qemu_fdt_setprop_cells(fdt, pci, "reg", 570 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 571 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 572 0, 0x1000); 573 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 574 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 575 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 576 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 577 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 578 g_free(pci); 579 580 if (pmc->has_mpc8xxx_gpio) { 581 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 582 } 583 g_free(soc); 584 585 if (pms->pbus_dev) { 586 platform_bus_create_devtree(pms, fdt, mpic); 587 } 588 g_free(mpic); 589 590 pmc->fixup_devtree(fdt); 591 592 if (toplevel_compat) { 593 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 594 strlen(toplevel_compat) + 1); 595 } 596 597 done: 598 if (!dry_run) { 599 qemu_fdt_dumpdtb(fdt, fdt_size); 600 cpu_physical_memory_write(addr, fdt, fdt_size); 601 } 602 ret = fdt_size; 603 g_free(fdt); 604 605 out: 606 g_free(pci_map); 607 608 return ret; 609 } 610 611 typedef struct DeviceTreeParams { 612 PPCE500MachineState *machine; 613 hwaddr addr; 614 hwaddr initrd_base; 615 hwaddr initrd_size; 616 hwaddr kernel_base; 617 hwaddr kernel_size; 618 Notifier notifier; 619 } DeviceTreeParams; 620 621 static void ppce500_reset_device_tree(void *opaque) 622 { 623 DeviceTreeParams *p = opaque; 624 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 625 p->initrd_size, p->kernel_base, p->kernel_size, 626 false); 627 } 628 629 static void ppce500_init_notify(Notifier *notifier, void *data) 630 { 631 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 632 ppce500_reset_device_tree(p); 633 } 634 635 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 636 hwaddr addr, 637 hwaddr initrd_base, 638 hwaddr initrd_size, 639 hwaddr kernel_base, 640 hwaddr kernel_size) 641 { 642 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 643 p->machine = machine; 644 p->addr = addr; 645 p->initrd_base = initrd_base; 646 p->initrd_size = initrd_size; 647 p->kernel_base = kernel_base; 648 p->kernel_size = kernel_size; 649 650 qemu_register_reset(ppce500_reset_device_tree, p); 651 p->notifier.notify = ppce500_init_notify; 652 qemu_add_machine_init_done_notifier(&p->notifier); 653 654 /* Issue the device tree loader once, so that we get the size of the blob */ 655 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 656 kernel_base, kernel_size, true); 657 } 658 659 /* Create -kernel TLB entries for BookE. */ 660 hwaddr booke206_page_size_to_tlb(uint64_t size) 661 { 662 return 63 - clz64(size / KiB); 663 } 664 665 static int booke206_initial_map_tsize(CPUPPCState *env) 666 { 667 struct boot_info *bi = env->load_info; 668 hwaddr dt_end; 669 int ps; 670 671 /* Our initial TLB entry needs to cover everything from 0 to 672 the device tree top */ 673 dt_end = bi->dt_base + bi->dt_size; 674 ps = booke206_page_size_to_tlb(dt_end) + 1; 675 if (ps & 1) { 676 /* e500v2 can only do even TLB size bits */ 677 ps++; 678 } 679 return ps; 680 } 681 682 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 683 { 684 int tsize; 685 686 tsize = booke206_initial_map_tsize(env); 687 return (1ULL << 10 << tsize); 688 } 689 690 static void mmubooke_create_initial_mapping(CPUPPCState *env) 691 { 692 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 693 hwaddr size; 694 int ps; 695 696 ps = booke206_initial_map_tsize(env); 697 size = (ps << MAS1_TSIZE_SHIFT); 698 tlb->mas1 = MAS1_VALID | size; 699 tlb->mas2 = 0; 700 tlb->mas7_3 = 0; 701 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 702 703 env->tlb_dirty = true; 704 } 705 706 static void ppce500_cpu_reset_sec(void *opaque) 707 { 708 PowerPCCPU *cpu = opaque; 709 CPUState *cs = CPU(cpu); 710 711 cpu_reset(cs); 712 713 cs->exception_index = EXCP_HLT; 714 } 715 716 static void ppce500_cpu_reset(void *opaque) 717 { 718 PowerPCCPU *cpu = opaque; 719 CPUState *cs = CPU(cpu); 720 CPUPPCState *env = &cpu->env; 721 struct boot_info *bi = env->load_info; 722 723 cpu_reset(cs); 724 725 /* Set initial guest state. */ 726 cs->halted = 0; 727 env->gpr[1] = (16 * MiB) - 8; 728 env->gpr[3] = bi->dt_base; 729 env->gpr[4] = 0; 730 env->gpr[5] = 0; 731 env->gpr[6] = EPAPR_MAGIC; 732 env->gpr[7] = mmubooke_initial_mapsize(env); 733 env->gpr[8] = 0; 734 env->gpr[9] = 0; 735 env->nip = bi->entry; 736 mmubooke_create_initial_mapping(env); 737 } 738 739 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 740 IrqLines *irqs) 741 { 742 DeviceState *dev; 743 SysBusDevice *s; 744 int i, j, k; 745 MachineState *machine = MACHINE(pms); 746 unsigned int smp_cpus = machine->smp.cpus; 747 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 748 749 dev = qdev_new(TYPE_OPENPIC); 750 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev)); 751 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 752 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 753 754 s = SYS_BUS_DEVICE(dev); 755 sysbus_realize_and_unref(s, &error_fatal); 756 757 k = 0; 758 for (i = 0; i < smp_cpus; i++) { 759 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 760 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 761 } 762 } 763 764 return dev; 765 } 766 767 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 768 IrqLines *irqs, Error **errp) 769 { 770 DeviceState *dev; 771 CPUState *cs; 772 773 dev = qdev_new(TYPE_KVM_OPENPIC); 774 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 775 776 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) { 777 object_unparent(OBJECT(dev)); 778 return NULL; 779 } 780 781 CPU_FOREACH(cs) { 782 if (kvm_openpic_connect_vcpu(dev, cs)) { 783 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 784 __func__); 785 abort(); 786 } 787 } 788 789 return dev; 790 } 791 792 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 793 MemoryRegion *ccsr, 794 IrqLines *irqs) 795 { 796 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 797 DeviceState *dev = NULL; 798 SysBusDevice *s; 799 800 if (kvm_enabled()) { 801 Error *err = NULL; 802 803 if (kvm_kernel_irqchip_allowed()) { 804 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 805 } 806 if (kvm_kernel_irqchip_required() && !dev) { 807 error_reportf_err(err, 808 "kernel_irqchip requested but unavailable: "); 809 exit(1); 810 } 811 } 812 813 if (!dev) { 814 dev = ppce500_init_mpic_qemu(pms, irqs); 815 } 816 817 s = SYS_BUS_DEVICE(dev); 818 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 819 s->mmio[0].memory); 820 821 return dev; 822 } 823 824 static void ppce500_power_off(void *opaque, int line, int on) 825 { 826 if (on) { 827 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 828 } 829 } 830 831 void ppce500_init(MachineState *machine) 832 { 833 MemoryRegion *address_space_mem = get_system_memory(); 834 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 835 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 836 PCIBus *pci_bus; 837 CPUPPCState *env = NULL; 838 uint64_t loadaddr; 839 hwaddr kernel_base = -1LL; 840 int kernel_size = 0; 841 hwaddr dt_base = 0; 842 hwaddr initrd_base = 0; 843 int initrd_size = 0; 844 hwaddr cur_base = 0; 845 char *filename; 846 const char *payload_name; 847 bool kernel_as_payload; 848 hwaddr bios_entry = 0; 849 target_long payload_size; 850 struct boot_info *boot_info; 851 int dt_size; 852 int i; 853 unsigned int smp_cpus = machine->smp.cpus; 854 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 855 * 4 respectively */ 856 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 857 IrqLines *irqs; 858 DeviceState *dev, *mpicdev; 859 CPUPPCState *firstenv = NULL; 860 MemoryRegion *ccsr_addr_space; 861 SysBusDevice *s; 862 PPCE500CCSRState *ccsr; 863 I2CBus *i2c; 864 865 irqs = g_new0(IrqLines, smp_cpus); 866 for (i = 0; i < smp_cpus; i++) { 867 PowerPCCPU *cpu; 868 CPUState *cs; 869 870 cpu = POWERPC_CPU(object_new(machine->cpu_type)); 871 env = &cpu->env; 872 cs = CPU(cpu); 873 874 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 875 error_report("MMU model %i not supported by this machine", 876 env->mmu_model); 877 exit(1); 878 } 879 880 /* 881 * Secondary CPU starts in halted state for now. Needs to change 882 * when implementing non-kernel boot. 883 */ 884 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0, 885 &error_fatal); 886 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal); 887 888 if (!firstenv) { 889 firstenv = env; 890 } 891 892 irqs[i].irq[OPENPIC_OUTPUT_INT] = 893 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT); 894 irqs[i].irq[OPENPIC_OUTPUT_CINT] = 895 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT); 896 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 897 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 898 899 ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500); 900 901 /* Register reset handler */ 902 if (!i) { 903 /* Primary CPU */ 904 struct boot_info *boot_info; 905 boot_info = g_new0(struct boot_info, 1); 906 qemu_register_reset(ppce500_cpu_reset, cpu); 907 env->load_info = boot_info; 908 } else { 909 /* Secondary CPUs */ 910 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 911 } 912 } 913 914 env = firstenv; 915 916 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 917 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 918 exit(EXIT_FAILURE); 919 } 920 921 /* Register Memory */ 922 memory_region_add_subregion(address_space_mem, 0, machine->ram); 923 924 dev = qdev_new("e500-ccsr"); 925 object_property_add_child(qdev_get_machine(), "e500-ccsr", 926 OBJECT(dev)); 927 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 928 ccsr = CCSR(dev); 929 ccsr_addr_space = &ccsr->ccsr_space; 930 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 931 ccsr_addr_space); 932 933 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 934 g_free(irqs); 935 936 /* Serial */ 937 if (serial_hd(0)) { 938 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 939 0, qdev_get_gpio_in(mpicdev, 42), 399193, 940 serial_hd(0), DEVICE_BIG_ENDIAN); 941 } 942 943 if (serial_hd(1)) { 944 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 945 0, qdev_get_gpio_in(mpicdev, 42), 399193, 946 serial_hd(1), DEVICE_BIG_ENDIAN); 947 } 948 /* I2C */ 949 dev = qdev_new("mpc-i2c"); 950 s = SYS_BUS_DEVICE(dev); 951 sysbus_realize_and_unref(s, &error_fatal); 952 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 953 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 954 sysbus_mmio_get_region(s, 0)); 955 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 956 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET); 957 958 959 /* General Utility device */ 960 dev = qdev_new("mpc8544-guts"); 961 s = SYS_BUS_DEVICE(dev); 962 sysbus_realize_and_unref(s, &error_fatal); 963 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 964 sysbus_mmio_get_region(s, 0)); 965 966 /* PCI */ 967 dev = qdev_new("e500-pcihost"); 968 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev)); 969 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 970 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 971 s = SYS_BUS_DEVICE(dev); 972 sysbus_realize_and_unref(s, &error_fatal); 973 for (i = 0; i < PCI_NUM_PINS; i++) { 974 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 975 } 976 977 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 978 sysbus_mmio_get_region(s, 0)); 979 980 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 981 if (!pci_bus) 982 printf("couldn't create PCI controller!\n"); 983 984 if (pci_bus) { 985 /* Register network interfaces. */ 986 for (i = 0; i < nb_nics; i++) { 987 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 988 } 989 } 990 991 /* Register spinning region */ 992 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 993 994 if (pmc->has_mpc8xxx_gpio) { 995 qemu_irq poweroff_irq; 996 997 dev = qdev_new("mpc8xxx_gpio"); 998 s = SYS_BUS_DEVICE(dev); 999 sysbus_realize_and_unref(s, &error_fatal); 1000 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 1001 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 1002 sysbus_mmio_get_region(s, 0)); 1003 1004 /* Power Off GPIO at Pin 0 */ 1005 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 1006 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1007 } 1008 1009 /* Platform Bus Device */ 1010 if (pmc->has_platform_bus) { 1011 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1012 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1013 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1014 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1015 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1016 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1017 1018 s = SYS_BUS_DEVICE(pms->pbus_dev); 1019 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1020 int irqn = pmc->platform_bus_first_irq + i; 1021 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1022 } 1023 1024 memory_region_add_subregion(address_space_mem, 1025 pmc->platform_bus_base, 1026 sysbus_mmio_get_region(s, 0)); 1027 } 1028 1029 /* 1030 * Smart firmware defaults ahead! 1031 * 1032 * We follow the following table to select which payload we execute. 1033 * 1034 * -kernel | -bios | payload 1035 * ---------+-------+--------- 1036 * N | Y | u-boot 1037 * N | N | u-boot 1038 * Y | Y | u-boot 1039 * Y | N | kernel 1040 * 1041 * This ensures backwards compatibility with how we used to expose 1042 * -kernel to users but allows them to run through u-boot as well. 1043 */ 1044 kernel_as_payload = false; 1045 if (machine->firmware == NULL) { 1046 if (machine->kernel_filename) { 1047 payload_name = machine->kernel_filename; 1048 kernel_as_payload = true; 1049 } else { 1050 payload_name = "u-boot.e500"; 1051 } 1052 } else { 1053 payload_name = machine->firmware; 1054 } 1055 1056 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1057 if (!filename) { 1058 error_report("could not find firmware/kernel file '%s'", payload_name); 1059 exit(1); 1060 } 1061 1062 payload_size = load_elf(filename, NULL, NULL, NULL, 1063 &bios_entry, &loadaddr, NULL, NULL, 1064 1, PPC_ELF_MACHINE, 0, 0); 1065 if (payload_size < 0) { 1066 /* 1067 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1068 * ePAPR compliant kernel 1069 */ 1070 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1071 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1072 NULL, NULL); 1073 if (payload_size < 0) { 1074 error_report("could not load firmware '%s'", filename); 1075 exit(1); 1076 } 1077 } 1078 1079 g_free(filename); 1080 1081 if (kernel_as_payload) { 1082 kernel_base = loadaddr; 1083 kernel_size = payload_size; 1084 } 1085 1086 cur_base = loadaddr + payload_size; 1087 if (cur_base < 32 * MiB) { 1088 /* u-boot occupies memory up to 32MB, so load blobs above */ 1089 cur_base = 32 * MiB; 1090 } 1091 1092 /* Load bare kernel only if no bios/u-boot has been provided */ 1093 if (machine->kernel_filename && !kernel_as_payload) { 1094 kernel_base = cur_base; 1095 kernel_size = load_image_targphys(machine->kernel_filename, 1096 cur_base, 1097 machine->ram_size - cur_base); 1098 if (kernel_size < 0) { 1099 error_report("could not load kernel '%s'", 1100 machine->kernel_filename); 1101 exit(1); 1102 } 1103 1104 cur_base += kernel_size; 1105 } 1106 1107 /* Load initrd. */ 1108 if (machine->initrd_filename) { 1109 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1110 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1111 machine->ram_size - initrd_base); 1112 1113 if (initrd_size < 0) { 1114 error_report("could not load initial ram disk '%s'", 1115 machine->initrd_filename); 1116 exit(1); 1117 } 1118 1119 cur_base = initrd_base + initrd_size; 1120 } 1121 1122 /* 1123 * Reserve space for dtb behind the kernel image because Linux has a bug 1124 * where it can only handle the dtb if it's within the first 64MB of where 1125 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1126 * ensures enough space between kernel and initrd. 1127 */ 1128 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1129 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1130 error_report("not enough memory for device tree"); 1131 exit(1); 1132 } 1133 1134 dt_size = ppce500_prep_device_tree(pms, dt_base, 1135 initrd_base, initrd_size, 1136 kernel_base, kernel_size); 1137 if (dt_size < 0) { 1138 error_report("couldn't load device tree"); 1139 exit(1); 1140 } 1141 assert(dt_size < DTB_MAX_SIZE); 1142 1143 boot_info = env->load_info; 1144 boot_info->entry = bios_entry; 1145 boot_info->dt_base = dt_base; 1146 boot_info->dt_size = dt_size; 1147 } 1148 1149 static void e500_ccsr_initfn(Object *obj) 1150 { 1151 PPCE500CCSRState *ccsr = CCSR(obj); 1152 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1153 MPC8544_CCSRBAR_SIZE); 1154 } 1155 1156 static const TypeInfo e500_ccsr_info = { 1157 .name = TYPE_CCSR, 1158 .parent = TYPE_SYS_BUS_DEVICE, 1159 .instance_size = sizeof(PPCE500CCSRState), 1160 .instance_init = e500_ccsr_initfn, 1161 }; 1162 1163 static const TypeInfo ppce500_info = { 1164 .name = TYPE_PPCE500_MACHINE, 1165 .parent = TYPE_MACHINE, 1166 .abstract = true, 1167 .instance_size = sizeof(PPCE500MachineState), 1168 .class_size = sizeof(PPCE500MachineClass), 1169 }; 1170 1171 static void e500_register_types(void) 1172 { 1173 type_register_static(&e500_ccsr_info); 1174 type_register_static(&ppce500_info); 1175 } 1176 1177 type_init(e500_register_types) 1178