1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qapi/error.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/openpic_kvm.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/loader.h" 35 #include "elf.h" 36 #include "hw/sysbus.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/host-utils.h" 39 #include "qemu/option.h" 40 #include "hw/pci-host/ppce500.h" 41 #include "qemu/error-report.h" 42 #include "hw/platform-bus.h" 43 #include "hw/net/fsl_etsec/etsec.h" 44 45 #define EPAPR_MAGIC (0x45504150) 46 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 47 #define DTC_LOAD_PAD 0x1800000 48 #define DTC_PAD_MASK 0xFFFFF 49 #define DTB_MAX_SIZE (8 * 1024 * 1024) 50 #define INITRD_LOAD_PAD 0x2000000 51 #define INITRD_PAD_MASK 0xFFFFFF 52 53 #define RAM_SIZES_ALIGN (64UL << 20) 54 55 /* TODO: parameterize */ 56 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 57 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 58 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 59 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 60 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 61 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 62 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 65 #define MPC8XXX_GPIO_IRQ 47 66 67 struct boot_info 68 { 69 uint32_t dt_base; 70 uint32_t dt_size; 71 uint32_t entry; 72 }; 73 74 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 75 int nr_slots, int *len) 76 { 77 int i = 0; 78 int slot; 79 int pci_irq; 80 int host_irq; 81 int last_slot = first_slot + nr_slots; 82 uint32_t *pci_map; 83 84 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 85 pci_map = g_malloc(*len); 86 87 for (slot = first_slot; slot < last_slot; slot++) { 88 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 89 pci_map[i++] = cpu_to_be32(slot << 11); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(0x0); 92 pci_map[i++] = cpu_to_be32(pci_irq + 1); 93 pci_map[i++] = cpu_to_be32(mpic); 94 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 95 pci_map[i++] = cpu_to_be32(host_irq + 1); 96 pci_map[i++] = cpu_to_be32(0x1); 97 } 98 } 99 100 assert((i * sizeof(uint32_t)) == *len); 101 102 return pci_map; 103 } 104 105 static void dt_serial_create(void *fdt, unsigned long long offset, 106 const char *soc, const char *mpic, 107 const char *alias, int idx, bool defcon) 108 { 109 char *ser; 110 111 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 112 qemu_fdt_add_subnode(fdt, ser); 113 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 114 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 115 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 116 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 117 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 118 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 119 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 120 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 121 122 if (defcon) { 123 /* 124 * "linux,stdout-path" and "stdout" properties are deprecated by linux 125 * kernel. New platforms should only use the "stdout-path" property. Set 126 * the new property and continue using older property to remain 127 * compatible with the existing firmware. 128 */ 129 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 130 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 131 } 132 g_free(ser); 133 } 134 135 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 136 { 137 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 138 int irq0 = MPC8XXX_GPIO_IRQ; 139 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 140 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 141 int gpio_ph; 142 143 qemu_fdt_add_subnode(fdt, node); 144 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 145 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 146 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 147 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 148 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 149 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 150 gpio_ph = qemu_fdt_alloc_phandle(fdt); 151 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 152 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 153 154 /* Power Off Pin */ 155 qemu_fdt_add_subnode(fdt, poweroff); 156 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 157 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 158 159 g_free(node); 160 g_free(poweroff); 161 } 162 163 typedef struct PlatformDevtreeData { 164 void *fdt; 165 const char *mpic; 166 int irq_start; 167 const char *node; 168 PlatformBusDevice *pbus; 169 } PlatformDevtreeData; 170 171 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 172 { 173 eTSEC *etsec = ETSEC_COMMON(sbdev); 174 PlatformBusDevice *pbus = data->pbus; 175 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 176 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 177 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 178 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 179 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 180 gchar *group = g_strdup_printf("%s/queue-group", node); 181 void *fdt = data->fdt; 182 183 assert((int64_t)mmio0 >= 0); 184 assert(irq0 >= 0); 185 assert(irq1 >= 0); 186 assert(irq2 >= 0); 187 188 qemu_fdt_add_subnode(fdt, node); 189 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 190 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 191 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 192 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 193 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 194 195 qemu_fdt_add_subnode(fdt, group); 196 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 197 qemu_fdt_setprop_cells(fdt, group, "interrupts", 198 data->irq_start + irq0, 0x2, 199 data->irq_start + irq1, 0x2, 200 data->irq_start + irq2, 0x2); 201 202 g_free(node); 203 g_free(group); 204 205 return 0; 206 } 207 208 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 209 { 210 PlatformDevtreeData *data = opaque; 211 bool matched = false; 212 213 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 214 create_devtree_etsec(sbdev, data); 215 matched = true; 216 } 217 218 if (!matched) { 219 error_report("Device %s is not supported by this machine yet.", 220 qdev_fw_name(DEVICE(sbdev))); 221 exit(1); 222 } 223 } 224 225 static void platform_bus_create_devtree(PPCE500MachineState *pms, 226 void *fdt, const char *mpic) 227 { 228 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 229 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 230 const char platcomp[] = "qemu,platform\0simple-bus"; 231 uint64_t addr = pmc->platform_bus_base; 232 uint64_t size = pmc->platform_bus_size; 233 int irq_start = pmc->platform_bus_first_irq; 234 235 /* Create a /platform node that we can put all devices into */ 236 237 qemu_fdt_add_subnode(fdt, node); 238 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 239 240 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 241 address and size */ 242 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 243 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 244 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 245 246 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 247 248 /* Create dt nodes for dynamic devices */ 249 PlatformDevtreeData data = { 250 .fdt = fdt, 251 .mpic = mpic, 252 .irq_start = irq_start, 253 .node = node, 254 .pbus = pms->pbus_dev, 255 }; 256 257 /* Loop through all dynamic sysbus devices and create nodes for them */ 258 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 259 260 g_free(node); 261 } 262 263 static int ppce500_load_device_tree(PPCE500MachineState *pms, 264 hwaddr addr, 265 hwaddr initrd_base, 266 hwaddr initrd_size, 267 hwaddr kernel_base, 268 hwaddr kernel_size, 269 bool dry_run) 270 { 271 MachineState *machine = MACHINE(pms); 272 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 273 CPUPPCState *env = first_cpu->env_ptr; 274 int ret = -1; 275 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 276 int fdt_size; 277 void *fdt; 278 uint8_t hypercall[16]; 279 uint32_t clock_freq = 400000000; 280 uint32_t tb_freq = 400000000; 281 int i; 282 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 283 char *soc; 284 char *mpic; 285 uint32_t mpic_ph; 286 uint32_t msi_ph; 287 char *gutil; 288 char *pci; 289 char *msi; 290 uint32_t *pci_map = NULL; 291 int len; 292 uint32_t pci_ranges[14] = 293 { 294 0x2000000, 0x0, pmc->pci_mmio_bus_base, 295 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 296 0x0, 0x20000000, 297 298 0x1000000, 0x0, 0x0, 299 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 300 0x0, 0x10000, 301 }; 302 QemuOpts *machine_opts = qemu_get_machine_opts(); 303 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 304 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 305 306 if (dtb_file) { 307 char *filename; 308 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 309 if (!filename) { 310 goto out; 311 } 312 313 fdt = load_device_tree(filename, &fdt_size); 314 g_free(filename); 315 if (!fdt) { 316 goto out; 317 } 318 goto done; 319 } 320 321 fdt = create_device_tree(&fdt_size); 322 if (fdt == NULL) { 323 goto out; 324 } 325 326 /* Manipulate device tree in memory. */ 327 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 328 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 329 330 qemu_fdt_add_subnode(fdt, "/memory"); 331 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 332 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 333 sizeof(mem_reg_property)); 334 335 qemu_fdt_add_subnode(fdt, "/chosen"); 336 if (initrd_size) { 337 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 338 initrd_base); 339 if (ret < 0) { 340 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 341 } 342 343 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 344 (initrd_base + initrd_size)); 345 if (ret < 0) { 346 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 347 } 348 349 } 350 351 if (kernel_base != -1ULL) { 352 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 353 kernel_base >> 32, kernel_base, 354 kernel_size >> 32, kernel_size); 355 } 356 357 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 358 machine->kernel_cmdline); 359 if (ret < 0) 360 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 361 362 if (kvm_enabled()) { 363 /* Read out host's frequencies */ 364 clock_freq = kvmppc_get_clockfreq(); 365 tb_freq = kvmppc_get_tbfreq(); 366 367 /* indicate KVM hypercall interface */ 368 qemu_fdt_add_subnode(fdt, "/hypervisor"); 369 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 370 "linux,kvm"); 371 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 372 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 373 hypercall, sizeof(hypercall)); 374 /* if KVM supports the idle hcall, set property indicating this */ 375 if (kvmppc_get_hasidle(env)) { 376 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 377 } 378 } 379 380 /* Create CPU nodes */ 381 qemu_fdt_add_subnode(fdt, "/cpus"); 382 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 383 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 384 385 /* We need to generate the cpu nodes in reverse order, so Linux can pick 386 the first node as boot node and be happy */ 387 for (i = smp_cpus - 1; i >= 0; i--) { 388 CPUState *cpu; 389 char *cpu_name; 390 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 391 392 cpu = qemu_get_cpu(i); 393 if (cpu == NULL) { 394 continue; 395 } 396 env = cpu->env_ptr; 397 398 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 399 qemu_fdt_add_subnode(fdt, cpu_name); 400 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 401 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 402 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 403 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 404 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 405 env->dcache_line_size); 406 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 407 env->icache_line_size); 408 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 409 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 410 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 411 if (cpu->cpu_index) { 412 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 413 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 414 "spin-table"); 415 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 416 cpu_release_addr); 417 } else { 418 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 419 } 420 g_free(cpu_name); 421 } 422 423 qemu_fdt_add_subnode(fdt, "/aliases"); 424 /* XXX These should go into their respective devices' code */ 425 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 426 qemu_fdt_add_subnode(fdt, soc); 427 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 428 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 429 sizeof(compatible_sb)); 430 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 431 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 432 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 433 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 434 MPC8544_CCSRBAR_SIZE); 435 /* XXX should contain a reasonable value */ 436 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 437 438 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 439 qemu_fdt_add_subnode(fdt, mpic); 440 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 441 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 442 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 443 0x40000); 444 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 445 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 446 mpic_ph = qemu_fdt_alloc_phandle(fdt); 447 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 448 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 449 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 450 451 /* 452 * We have to generate ser1 first, because Linux takes the first 453 * device it finds in the dt as serial output device. And we generate 454 * devices in reverse order to the dt. 455 */ 456 if (serial_hd(1)) { 457 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 458 soc, mpic, "serial1", 1, false); 459 } 460 461 if (serial_hd(0)) { 462 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 463 soc, mpic, "serial0", 0, true); 464 } 465 466 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 467 MPC8544_UTIL_OFFSET); 468 qemu_fdt_add_subnode(fdt, gutil); 469 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 470 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 471 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 472 g_free(gutil); 473 474 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 475 qemu_fdt_add_subnode(fdt, msi); 476 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 477 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 478 msi_ph = qemu_fdt_alloc_phandle(fdt); 479 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 480 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 481 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 482 0xe0, 0x0, 483 0xe1, 0x0, 484 0xe2, 0x0, 485 0xe3, 0x0, 486 0xe4, 0x0, 487 0xe5, 0x0, 488 0xe6, 0x0, 489 0xe7, 0x0); 490 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 491 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 492 g_free(msi); 493 494 pci = g_strdup_printf("/pci@%llx", 495 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 496 qemu_fdt_add_subnode(fdt, pci); 497 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 498 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 499 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 500 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 501 0x0, 0x7); 502 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 503 pmc->pci_first_slot, pmc->pci_nr_slots, 504 &len); 505 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 506 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 507 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 508 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 509 for (i = 0; i < 14; i++) { 510 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 511 } 512 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 513 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 514 qemu_fdt_setprop_cells(fdt, pci, "reg", 515 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 516 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 517 0, 0x1000); 518 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 519 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 520 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 521 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 522 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 523 g_free(pci); 524 525 if (pmc->has_mpc8xxx_gpio) { 526 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 527 } 528 g_free(soc); 529 530 if (pms->pbus_dev) { 531 platform_bus_create_devtree(pms, fdt, mpic); 532 } 533 g_free(mpic); 534 535 pmc->fixup_devtree(fdt); 536 537 if (toplevel_compat) { 538 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 539 strlen(toplevel_compat) + 1); 540 } 541 542 done: 543 if (!dry_run) { 544 qemu_fdt_dumpdtb(fdt, fdt_size); 545 cpu_physical_memory_write(addr, fdt, fdt_size); 546 } 547 ret = fdt_size; 548 549 out: 550 g_free(pci_map); 551 552 return ret; 553 } 554 555 typedef struct DeviceTreeParams { 556 PPCE500MachineState *machine; 557 hwaddr addr; 558 hwaddr initrd_base; 559 hwaddr initrd_size; 560 hwaddr kernel_base; 561 hwaddr kernel_size; 562 Notifier notifier; 563 } DeviceTreeParams; 564 565 static void ppce500_reset_device_tree(void *opaque) 566 { 567 DeviceTreeParams *p = opaque; 568 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 569 p->initrd_size, p->kernel_base, p->kernel_size, 570 false); 571 } 572 573 static void ppce500_init_notify(Notifier *notifier, void *data) 574 { 575 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 576 ppce500_reset_device_tree(p); 577 } 578 579 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 580 hwaddr addr, 581 hwaddr initrd_base, 582 hwaddr initrd_size, 583 hwaddr kernel_base, 584 hwaddr kernel_size) 585 { 586 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 587 p->machine = machine; 588 p->addr = addr; 589 p->initrd_base = initrd_base; 590 p->initrd_size = initrd_size; 591 p->kernel_base = kernel_base; 592 p->kernel_size = kernel_size; 593 594 qemu_register_reset(ppce500_reset_device_tree, p); 595 p->notifier.notify = ppce500_init_notify; 596 qemu_add_machine_init_done_notifier(&p->notifier); 597 598 /* Issue the device tree loader once, so that we get the size of the blob */ 599 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 600 kernel_base, kernel_size, true); 601 } 602 603 /* Create -kernel TLB entries for BookE. */ 604 hwaddr booke206_page_size_to_tlb(uint64_t size) 605 { 606 return 63 - clz64(size >> 10); 607 } 608 609 static int booke206_initial_map_tsize(CPUPPCState *env) 610 { 611 struct boot_info *bi = env->load_info; 612 hwaddr dt_end; 613 int ps; 614 615 /* Our initial TLB entry needs to cover everything from 0 to 616 the device tree top */ 617 dt_end = bi->dt_base + bi->dt_size; 618 ps = booke206_page_size_to_tlb(dt_end) + 1; 619 if (ps & 1) { 620 /* e500v2 can only do even TLB size bits */ 621 ps++; 622 } 623 return ps; 624 } 625 626 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 627 { 628 int tsize; 629 630 tsize = booke206_initial_map_tsize(env); 631 return (1ULL << 10 << tsize); 632 } 633 634 static void mmubooke_create_initial_mapping(CPUPPCState *env) 635 { 636 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 637 hwaddr size; 638 int ps; 639 640 ps = booke206_initial_map_tsize(env); 641 size = (ps << MAS1_TSIZE_SHIFT); 642 tlb->mas1 = MAS1_VALID | size; 643 tlb->mas2 = 0; 644 tlb->mas7_3 = 0; 645 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 646 647 env->tlb_dirty = true; 648 } 649 650 static void ppce500_cpu_reset_sec(void *opaque) 651 { 652 PowerPCCPU *cpu = opaque; 653 CPUState *cs = CPU(cpu); 654 655 cpu_reset(cs); 656 657 /* Secondary CPU starts in halted state for now. Needs to change when 658 implementing non-kernel boot. */ 659 cs->halted = 1; 660 cs->exception_index = EXCP_HLT; 661 } 662 663 static void ppce500_cpu_reset(void *opaque) 664 { 665 PowerPCCPU *cpu = opaque; 666 CPUState *cs = CPU(cpu); 667 CPUPPCState *env = &cpu->env; 668 struct boot_info *bi = env->load_info; 669 670 cpu_reset(cs); 671 672 /* Set initial guest state. */ 673 cs->halted = 0; 674 env->gpr[1] = (16<<20) - 8; 675 env->gpr[3] = bi->dt_base; 676 env->gpr[4] = 0; 677 env->gpr[5] = 0; 678 env->gpr[6] = EPAPR_MAGIC; 679 env->gpr[7] = mmubooke_initial_mapsize(env); 680 env->gpr[8] = 0; 681 env->gpr[9] = 0; 682 env->nip = bi->entry; 683 mmubooke_create_initial_mapping(env); 684 } 685 686 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 687 qemu_irq **irqs) 688 { 689 DeviceState *dev; 690 SysBusDevice *s; 691 int i, j, k; 692 MachineState *machine = MACHINE(pms); 693 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 694 695 dev = qdev_create(NULL, TYPE_OPENPIC); 696 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 697 &error_fatal); 698 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 699 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 700 701 qdev_init_nofail(dev); 702 s = SYS_BUS_DEVICE(dev); 703 704 k = 0; 705 for (i = 0; i < smp_cpus; i++) { 706 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 707 sysbus_connect_irq(s, k++, irqs[i][j]); 708 } 709 } 710 711 return dev; 712 } 713 714 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 715 qemu_irq **irqs, Error **errp) 716 { 717 Error *err = NULL; 718 DeviceState *dev; 719 CPUState *cs; 720 721 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 722 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 723 724 object_property_set_bool(OBJECT(dev), true, "realized", &err); 725 if (err) { 726 error_propagate(errp, err); 727 object_unparent(OBJECT(dev)); 728 return NULL; 729 } 730 731 CPU_FOREACH(cs) { 732 if (kvm_openpic_connect_vcpu(dev, cs)) { 733 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 734 __func__); 735 abort(); 736 } 737 } 738 739 return dev; 740 } 741 742 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 743 MemoryRegion *ccsr, 744 qemu_irq **irqs) 745 { 746 MachineState *machine = MACHINE(pms); 747 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 748 DeviceState *dev = NULL; 749 SysBusDevice *s; 750 751 if (kvm_enabled()) { 752 Error *err = NULL; 753 754 if (machine_kernel_irqchip_allowed(machine)) { 755 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 756 } 757 if (machine_kernel_irqchip_required(machine) && !dev) { 758 error_reportf_err(err, 759 "kernel_irqchip requested but unavailable: "); 760 exit(1); 761 } 762 } 763 764 if (!dev) { 765 dev = ppce500_init_mpic_qemu(pms, irqs); 766 } 767 768 s = SYS_BUS_DEVICE(dev); 769 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 770 s->mmio[0].memory); 771 772 return dev; 773 } 774 775 static void ppce500_power_off(void *opaque, int line, int on) 776 { 777 if (on) { 778 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 779 } 780 } 781 782 void ppce500_init(MachineState *machine) 783 { 784 MemoryRegion *address_space_mem = get_system_memory(); 785 MemoryRegion *ram = g_new(MemoryRegion, 1); 786 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 787 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 788 PCIBus *pci_bus; 789 CPUPPCState *env = NULL; 790 uint64_t loadaddr; 791 hwaddr kernel_base = -1LL; 792 int kernel_size = 0; 793 hwaddr dt_base = 0; 794 hwaddr initrd_base = 0; 795 int initrd_size = 0; 796 hwaddr cur_base = 0; 797 char *filename; 798 const char *payload_name; 799 bool kernel_as_payload; 800 hwaddr bios_entry = 0; 801 target_long payload_size; 802 struct boot_info *boot_info; 803 int dt_size; 804 int i; 805 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 806 * 4 respectively */ 807 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 808 qemu_irq **irqs; 809 DeviceState *dev, *mpicdev; 810 CPUPPCState *firstenv = NULL; 811 MemoryRegion *ccsr_addr_space; 812 SysBusDevice *s; 813 PPCE500CCSRState *ccsr; 814 815 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 816 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 817 for (i = 0; i < smp_cpus; i++) { 818 PowerPCCPU *cpu; 819 CPUState *cs; 820 qemu_irq *input; 821 822 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 823 env = &cpu->env; 824 cs = CPU(cpu); 825 826 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 827 error_report("MMU model %i not supported by this machine", 828 env->mmu_model); 829 exit(1); 830 } 831 832 if (!firstenv) { 833 firstenv = env; 834 } 835 836 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 837 input = (qemu_irq *)env->irq_inputs; 838 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 839 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 840 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 841 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 842 843 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 844 845 /* Register reset handler */ 846 if (!i) { 847 /* Primary CPU */ 848 struct boot_info *boot_info; 849 boot_info = g_malloc0(sizeof(struct boot_info)); 850 qemu_register_reset(ppce500_cpu_reset, cpu); 851 env->load_info = boot_info; 852 } else { 853 /* Secondary CPUs */ 854 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 855 } 856 } 857 858 env = firstenv; 859 860 /* Fixup Memory size on a alignment boundary */ 861 ram_size &= ~(RAM_SIZES_ALIGN - 1); 862 machine->ram_size = ram_size; 863 864 /* Register Memory */ 865 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 866 memory_region_add_subregion(address_space_mem, 0, ram); 867 868 dev = qdev_create(NULL, "e500-ccsr"); 869 object_property_add_child(qdev_get_machine(), "e500-ccsr", 870 OBJECT(dev), NULL); 871 qdev_init_nofail(dev); 872 ccsr = CCSR(dev); 873 ccsr_addr_space = &ccsr->ccsr_space; 874 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 875 ccsr_addr_space); 876 877 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 878 879 /* Serial */ 880 if (serial_hd(0)) { 881 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 882 0, qdev_get_gpio_in(mpicdev, 42), 399193, 883 serial_hd(0), DEVICE_BIG_ENDIAN); 884 } 885 886 if (serial_hd(1)) { 887 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 888 0, qdev_get_gpio_in(mpicdev, 42), 399193, 889 serial_hd(1), DEVICE_BIG_ENDIAN); 890 } 891 892 /* General Utility device */ 893 dev = qdev_create(NULL, "mpc8544-guts"); 894 qdev_init_nofail(dev); 895 s = SYS_BUS_DEVICE(dev); 896 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 897 sysbus_mmio_get_region(s, 0)); 898 899 /* PCI */ 900 dev = qdev_create(NULL, "e500-pcihost"); 901 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 902 &error_abort); 903 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 904 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 905 qdev_init_nofail(dev); 906 s = SYS_BUS_DEVICE(dev); 907 for (i = 0; i < PCI_NUM_PINS; i++) { 908 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 909 } 910 911 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 912 sysbus_mmio_get_region(s, 0)); 913 914 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 915 if (!pci_bus) 916 printf("couldn't create PCI controller!\n"); 917 918 if (pci_bus) { 919 /* Register network interfaces. */ 920 for (i = 0; i < nb_nics; i++) { 921 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 922 } 923 } 924 925 /* Register spinning region */ 926 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 927 928 if (pmc->has_mpc8xxx_gpio) { 929 qemu_irq poweroff_irq; 930 931 dev = qdev_create(NULL, "mpc8xxx_gpio"); 932 s = SYS_BUS_DEVICE(dev); 933 qdev_init_nofail(dev); 934 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 935 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 936 sysbus_mmio_get_region(s, 0)); 937 938 /* Power Off GPIO at Pin 0 */ 939 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 940 qdev_connect_gpio_out(dev, 0, poweroff_irq); 941 } 942 943 /* Platform Bus Device */ 944 if (pmc->has_platform_bus) { 945 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 946 dev->id = TYPE_PLATFORM_BUS_DEVICE; 947 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 948 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 949 qdev_init_nofail(dev); 950 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 951 952 s = SYS_BUS_DEVICE(pms->pbus_dev); 953 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 954 int irqn = pmc->platform_bus_first_irq + i; 955 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 956 } 957 958 memory_region_add_subregion(address_space_mem, 959 pmc->platform_bus_base, 960 sysbus_mmio_get_region(s, 0)); 961 } 962 963 /* 964 * Smart firmware defaults ahead! 965 * 966 * We follow the following table to select which payload we execute. 967 * 968 * -kernel | -bios | payload 969 * ---------+-------+--------- 970 * N | Y | u-boot 971 * N | N | u-boot 972 * Y | Y | u-boot 973 * Y | N | kernel 974 * 975 * This ensures backwards compatibility with how we used to expose 976 * -kernel to users but allows them to run through u-boot as well. 977 */ 978 kernel_as_payload = false; 979 if (bios_name == NULL) { 980 if (machine->kernel_filename) { 981 payload_name = machine->kernel_filename; 982 kernel_as_payload = true; 983 } else { 984 payload_name = "u-boot.e500"; 985 } 986 } else { 987 payload_name = bios_name; 988 } 989 990 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 991 992 payload_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 993 1, PPC_ELF_MACHINE, 0, 0); 994 if (payload_size < 0) { 995 /* 996 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 997 * ePAPR compliant kernel 998 */ 999 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1000 NULL, NULL); 1001 if (payload_size < 0) { 1002 error_report("qemu: could not load firmware '%s'", filename); 1003 exit(1); 1004 } 1005 } 1006 1007 g_free(filename); 1008 1009 if (kernel_as_payload) { 1010 kernel_base = loadaddr; 1011 kernel_size = payload_size; 1012 } 1013 1014 cur_base = loadaddr + payload_size; 1015 if (cur_base < (32 * 1024 * 1024)) { 1016 /* u-boot occupies memory up to 32MB, so load blobs above */ 1017 cur_base = (32 * 1024 * 1024); 1018 } 1019 1020 /* Load bare kernel only if no bios/u-boot has been provided */ 1021 if (machine->kernel_filename && !kernel_as_payload) { 1022 kernel_base = cur_base; 1023 kernel_size = load_image_targphys(machine->kernel_filename, 1024 cur_base, 1025 ram_size - cur_base); 1026 if (kernel_size < 0) { 1027 error_report("could not load kernel '%s'", 1028 machine->kernel_filename); 1029 exit(1); 1030 } 1031 1032 cur_base += kernel_size; 1033 } 1034 1035 /* Load initrd. */ 1036 if (machine->initrd_filename) { 1037 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1038 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1039 ram_size - initrd_base); 1040 1041 if (initrd_size < 0) { 1042 error_report("could not load initial ram disk '%s'", 1043 machine->initrd_filename); 1044 exit(1); 1045 } 1046 1047 cur_base = initrd_base + initrd_size; 1048 } 1049 1050 /* 1051 * Reserve space for dtb behind the kernel image because Linux has a bug 1052 * where it can only handle the dtb if it's within the first 64MB of where 1053 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1054 * ensures enough space between kernel and initrd. 1055 */ 1056 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1057 if (dt_base + DTB_MAX_SIZE > ram_size) { 1058 error_report("qemu: not enough memory for device tree"); 1059 exit(1); 1060 } 1061 1062 dt_size = ppce500_prep_device_tree(pms, dt_base, 1063 initrd_base, initrd_size, 1064 kernel_base, kernel_size); 1065 if (dt_size < 0) { 1066 error_report("couldn't load device tree"); 1067 exit(1); 1068 } 1069 assert(dt_size < DTB_MAX_SIZE); 1070 1071 boot_info = env->load_info; 1072 boot_info->entry = bios_entry; 1073 boot_info->dt_base = dt_base; 1074 boot_info->dt_size = dt_size; 1075 } 1076 1077 static void e500_ccsr_initfn(Object *obj) 1078 { 1079 PPCE500CCSRState *ccsr = CCSR(obj); 1080 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1081 MPC8544_CCSRBAR_SIZE); 1082 } 1083 1084 static const TypeInfo e500_ccsr_info = { 1085 .name = TYPE_CCSR, 1086 .parent = TYPE_SYS_BUS_DEVICE, 1087 .instance_size = sizeof(PPCE500CCSRState), 1088 .instance_init = e500_ccsr_initfn, 1089 }; 1090 1091 static const TypeInfo ppce500_info = { 1092 .name = TYPE_PPCE500_MACHINE, 1093 .parent = TYPE_MACHINE, 1094 .abstract = true, 1095 .instance_size = sizeof(PPCE500MachineState), 1096 .class_size = sizeof(PPCE500MachineClass), 1097 }; 1098 1099 static void e500_register_types(void) 1100 { 1101 type_register_static(&e500_ccsr_info); 1102 type_register_static(&ppce500_info); 1103 } 1104 1105 type_init(e500_register_types) 1106