1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qapi/error.h" 19 #include "qemu-common.h" 20 #include "e500.h" 21 #include "e500-ccsr.h" 22 #include "net/net.h" 23 #include "qemu/config-file.h" 24 #include "hw/hw.h" 25 #include "hw/char/serial.h" 26 #include "hw/pci/pci.h" 27 #include "hw/boards.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/device_tree.h" 32 #include "hw/ppc/openpic.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/loader.h" 35 #include "elf.h" 36 #include "hw/sysbus.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/host-utils.h" 39 #include "hw/pci-host/ppce500.h" 40 #include "qemu/error-report.h" 41 #include "hw/platform-bus.h" 42 #include "hw/net/fsl_etsec/etsec.h" 43 44 #define EPAPR_MAGIC (0x45504150) 45 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 46 #define DTC_LOAD_PAD 0x1800000 47 #define DTC_PAD_MASK 0xFFFFF 48 #define DTB_MAX_SIZE (8 * 1024 * 1024) 49 #define INITRD_LOAD_PAD 0x2000000 50 #define INITRD_PAD_MASK 0xFFFFFF 51 52 #define RAM_SIZES_ALIGN (64UL << 20) 53 54 /* TODO: parameterize */ 55 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 56 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 57 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 58 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 59 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 60 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 62 #define MPC8544_UTIL_OFFSET 0xe0000ULL 63 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 64 #define MPC8XXX_GPIO_IRQ 47 65 66 struct boot_info 67 { 68 uint32_t dt_base; 69 uint32_t dt_size; 70 uint32_t entry; 71 }; 72 73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 74 int nr_slots, int *len) 75 { 76 int i = 0; 77 int slot; 78 int pci_irq; 79 int host_irq; 80 int last_slot = first_slot + nr_slots; 81 uint32_t *pci_map; 82 83 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 84 pci_map = g_malloc(*len); 85 86 for (slot = first_slot; slot < last_slot; slot++) { 87 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 88 pci_map[i++] = cpu_to_be32(slot << 11); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(pci_irq + 1); 92 pci_map[i++] = cpu_to_be32(mpic); 93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 94 pci_map[i++] = cpu_to_be32(host_irq + 1); 95 pci_map[i++] = cpu_to_be32(0x1); 96 } 97 } 98 99 assert((i * sizeof(uint32_t)) == *len); 100 101 return pci_map; 102 } 103 104 static void dt_serial_create(void *fdt, unsigned long long offset, 105 const char *soc, const char *mpic, 106 const char *alias, int idx, bool defcon) 107 { 108 char ser[128]; 109 110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 111 qemu_fdt_add_subnode(fdt, ser); 112 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 113 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 114 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 115 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 116 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 117 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 118 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 119 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 120 121 if (defcon) { 122 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 123 } 124 } 125 126 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 127 { 128 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 129 int irq0 = MPC8XXX_GPIO_IRQ; 130 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 131 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 132 int gpio_ph; 133 134 qemu_fdt_add_subnode(fdt, node); 135 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 136 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 137 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 138 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 139 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 140 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 141 gpio_ph = qemu_fdt_alloc_phandle(fdt); 142 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 143 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 144 145 /* Power Off Pin */ 146 qemu_fdt_add_subnode(fdt, poweroff); 147 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 148 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 149 150 g_free(node); 151 g_free(poweroff); 152 } 153 154 typedef struct PlatformDevtreeData { 155 void *fdt; 156 const char *mpic; 157 int irq_start; 158 const char *node; 159 PlatformBusDevice *pbus; 160 } PlatformDevtreeData; 161 162 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 163 { 164 eTSEC *etsec = ETSEC_COMMON(sbdev); 165 PlatformBusDevice *pbus = data->pbus; 166 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 167 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 168 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 169 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 170 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 171 gchar *group = g_strdup_printf("%s/queue-group", node); 172 void *fdt = data->fdt; 173 174 assert((int64_t)mmio0 >= 0); 175 assert(irq0 >= 0); 176 assert(irq1 >= 0); 177 assert(irq2 >= 0); 178 179 qemu_fdt_add_subnode(fdt, node); 180 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 181 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 182 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 183 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 184 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 185 186 qemu_fdt_add_subnode(fdt, group); 187 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 188 qemu_fdt_setprop_cells(fdt, group, "interrupts", 189 data->irq_start + irq0, 0x2, 190 data->irq_start + irq1, 0x2, 191 data->irq_start + irq2, 0x2); 192 193 g_free(node); 194 g_free(group); 195 196 return 0; 197 } 198 199 static int sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 200 { 201 PlatformDevtreeData *data = opaque; 202 bool matched = false; 203 204 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 205 create_devtree_etsec(sbdev, data); 206 matched = true; 207 } 208 209 if (!matched) { 210 error_report("Device %s is not supported by this machine yet.", 211 qdev_fw_name(DEVICE(sbdev))); 212 exit(1); 213 } 214 215 return 0; 216 } 217 218 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, 219 const char *mpic) 220 { 221 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); 222 const char platcomp[] = "qemu,platform\0simple-bus"; 223 uint64_t addr = params->platform_bus_base; 224 uint64_t size = params->platform_bus_size; 225 int irq_start = params->platform_bus_first_irq; 226 PlatformBusDevice *pbus; 227 DeviceState *dev; 228 229 /* Create a /platform node that we can put all devices into */ 230 231 qemu_fdt_add_subnode(fdt, node); 232 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 233 234 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 235 address and size */ 236 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 237 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 238 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 239 240 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 241 242 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); 243 pbus = PLATFORM_BUS_DEVICE(dev); 244 245 /* We can only create dt nodes for dynamic devices when they're ready */ 246 if (pbus->done_gathering) { 247 PlatformDevtreeData data = { 248 .fdt = fdt, 249 .mpic = mpic, 250 .irq_start = irq_start, 251 .node = node, 252 .pbus = pbus, 253 }; 254 255 /* Loop through all dynamic sysbus devices and create nodes for them */ 256 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 257 } 258 259 g_free(node); 260 } 261 262 static int ppce500_load_device_tree(MachineState *machine, 263 PPCE500Params *params, 264 hwaddr addr, 265 hwaddr initrd_base, 266 hwaddr initrd_size, 267 hwaddr kernel_base, 268 hwaddr kernel_size, 269 bool dry_run) 270 { 271 CPUPPCState *env = first_cpu->env_ptr; 272 int ret = -1; 273 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 274 int fdt_size; 275 void *fdt; 276 uint8_t hypercall[16]; 277 uint32_t clock_freq = 400000000; 278 uint32_t tb_freq = 400000000; 279 int i; 280 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 281 char soc[128]; 282 char mpic[128]; 283 uint32_t mpic_ph; 284 uint32_t msi_ph; 285 char gutil[128]; 286 char pci[128]; 287 char msi[128]; 288 uint32_t *pci_map = NULL; 289 int len; 290 uint32_t pci_ranges[14] = 291 { 292 0x2000000, 0x0, params->pci_mmio_bus_base, 293 params->pci_mmio_base >> 32, params->pci_mmio_base, 294 0x0, 0x20000000, 295 296 0x1000000, 0x0, 0x0, 297 params->pci_pio_base >> 32, params->pci_pio_base, 298 0x0, 0x10000, 299 }; 300 QemuOpts *machine_opts = qemu_get_machine_opts(); 301 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 302 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 303 304 if (dtb_file) { 305 char *filename; 306 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 307 if (!filename) { 308 goto out; 309 } 310 311 fdt = load_device_tree(filename, &fdt_size); 312 g_free(filename); 313 if (!fdt) { 314 goto out; 315 } 316 goto done; 317 } 318 319 fdt = create_device_tree(&fdt_size); 320 if (fdt == NULL) { 321 goto out; 322 } 323 324 /* Manipulate device tree in memory. */ 325 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 326 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 327 328 qemu_fdt_add_subnode(fdt, "/memory"); 329 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 330 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 331 sizeof(mem_reg_property)); 332 333 qemu_fdt_add_subnode(fdt, "/chosen"); 334 if (initrd_size) { 335 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 336 initrd_base); 337 if (ret < 0) { 338 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 339 } 340 341 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 342 (initrd_base + initrd_size)); 343 if (ret < 0) { 344 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 345 } 346 347 } 348 349 if (kernel_base != -1ULL) { 350 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 351 kernel_base >> 32, kernel_base, 352 kernel_size >> 32, kernel_size); 353 } 354 355 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 356 machine->kernel_cmdline); 357 if (ret < 0) 358 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 359 360 if (kvm_enabled()) { 361 /* Read out host's frequencies */ 362 clock_freq = kvmppc_get_clockfreq(); 363 tb_freq = kvmppc_get_tbfreq(); 364 365 /* indicate KVM hypercall interface */ 366 qemu_fdt_add_subnode(fdt, "/hypervisor"); 367 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 368 "linux,kvm"); 369 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 370 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 371 hypercall, sizeof(hypercall)); 372 /* if KVM supports the idle hcall, set property indicating this */ 373 if (kvmppc_get_hasidle(env)) { 374 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 375 } 376 } 377 378 /* Create CPU nodes */ 379 qemu_fdt_add_subnode(fdt, "/cpus"); 380 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 381 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 382 383 /* We need to generate the cpu nodes in reverse order, so Linux can pick 384 the first node as boot node and be happy */ 385 for (i = smp_cpus - 1; i >= 0; i--) { 386 CPUState *cpu; 387 PowerPCCPU *pcpu; 388 char cpu_name[128]; 389 uint64_t cpu_release_addr = params->spin_base + (i * 0x20); 390 391 cpu = qemu_get_cpu(i); 392 if (cpu == NULL) { 393 continue; 394 } 395 env = cpu->env_ptr; 396 pcpu = POWERPC_CPU(cpu); 397 398 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 399 ppc_get_vcpu_dt_id(pcpu)); 400 qemu_fdt_add_subnode(fdt, cpu_name); 401 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 402 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 403 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 404 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 405 ppc_get_vcpu_dt_id(pcpu)); 406 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 407 env->dcache_line_size); 408 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 409 env->icache_line_size); 410 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 411 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 412 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 413 if (cpu->cpu_index) { 414 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 415 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 416 "spin-table"); 417 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 418 cpu_release_addr); 419 } else { 420 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 421 } 422 } 423 424 qemu_fdt_add_subnode(fdt, "/aliases"); 425 /* XXX These should go into their respective devices' code */ 426 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); 427 qemu_fdt_add_subnode(fdt, soc); 428 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 429 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 430 sizeof(compatible_sb)); 431 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 432 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 433 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 434 params->ccsrbar_base >> 32, params->ccsrbar_base, 435 MPC8544_CCSRBAR_SIZE); 436 /* XXX should contain a reasonable value */ 437 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 438 439 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 440 qemu_fdt_add_subnode(fdt, mpic); 441 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 442 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 443 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 444 0x40000); 445 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 446 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 447 mpic_ph = qemu_fdt_alloc_phandle(fdt); 448 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 449 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 450 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 451 452 /* 453 * We have to generate ser1 first, because Linux takes the first 454 * device it finds in the dt as serial output device. And we generate 455 * devices in reverse order to the dt. 456 */ 457 if (serial_hds[1]) { 458 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 459 soc, mpic, "serial1", 1, false); 460 } 461 462 if (serial_hds[0]) { 463 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 464 soc, mpic, "serial0", 0, true); 465 } 466 467 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 468 MPC8544_UTIL_OFFSET); 469 qemu_fdt_add_subnode(fdt, gutil); 470 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 471 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 472 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 473 474 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 475 qemu_fdt_add_subnode(fdt, msi); 476 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 477 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 478 msi_ph = qemu_fdt_alloc_phandle(fdt); 479 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 480 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 481 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 482 0xe0, 0x0, 483 0xe1, 0x0, 484 0xe2, 0x0, 485 0xe3, 0x0, 486 0xe4, 0x0, 487 0xe5, 0x0, 488 0xe6, 0x0, 489 0xe7, 0x0); 490 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 491 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 492 493 snprintf(pci, sizeof(pci), "/pci@%llx", 494 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 495 qemu_fdt_add_subnode(fdt, pci); 496 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 497 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 498 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 499 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 500 0x0, 0x7); 501 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 502 params->pci_first_slot, params->pci_nr_slots, 503 &len); 504 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 505 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 506 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 507 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 508 for (i = 0; i < 14; i++) { 509 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 510 } 511 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 512 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 513 qemu_fdt_setprop_cells(fdt, pci, "reg", 514 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 515 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 516 0, 0x1000); 517 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 518 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 519 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 520 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 521 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 522 523 if (params->has_mpc8xxx_gpio) { 524 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 525 } 526 527 if (params->has_platform_bus) { 528 platform_bus_create_devtree(params, fdt, mpic); 529 } 530 531 params->fixup_devtree(params, fdt); 532 533 if (toplevel_compat) { 534 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 535 strlen(toplevel_compat) + 1); 536 } 537 538 done: 539 if (!dry_run) { 540 qemu_fdt_dumpdtb(fdt, fdt_size); 541 cpu_physical_memory_write(addr, fdt, fdt_size); 542 } 543 ret = fdt_size; 544 545 out: 546 g_free(pci_map); 547 548 return ret; 549 } 550 551 typedef struct DeviceTreeParams { 552 MachineState *machine; 553 PPCE500Params params; 554 hwaddr addr; 555 hwaddr initrd_base; 556 hwaddr initrd_size; 557 hwaddr kernel_base; 558 hwaddr kernel_size; 559 Notifier notifier; 560 } DeviceTreeParams; 561 562 static void ppce500_reset_device_tree(void *opaque) 563 { 564 DeviceTreeParams *p = opaque; 565 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base, 566 p->initrd_size, p->kernel_base, p->kernel_size, 567 false); 568 } 569 570 static void ppce500_init_notify(Notifier *notifier, void *data) 571 { 572 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 573 ppce500_reset_device_tree(p); 574 } 575 576 static int ppce500_prep_device_tree(MachineState *machine, 577 PPCE500Params *params, 578 hwaddr addr, 579 hwaddr initrd_base, 580 hwaddr initrd_size, 581 hwaddr kernel_base, 582 hwaddr kernel_size) 583 { 584 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 585 p->machine = machine; 586 p->params = *params; 587 p->addr = addr; 588 p->initrd_base = initrd_base; 589 p->initrd_size = initrd_size; 590 p->kernel_base = kernel_base; 591 p->kernel_size = kernel_size; 592 593 qemu_register_reset(ppce500_reset_device_tree, p); 594 p->notifier.notify = ppce500_init_notify; 595 qemu_add_machine_init_done_notifier(&p->notifier); 596 597 /* Issue the device tree loader once, so that we get the size of the blob */ 598 return ppce500_load_device_tree(machine, params, addr, initrd_base, 599 initrd_size, kernel_base, kernel_size, 600 true); 601 } 602 603 /* Create -kernel TLB entries for BookE. */ 604 hwaddr booke206_page_size_to_tlb(uint64_t size) 605 { 606 return 63 - clz64(size >> 10); 607 } 608 609 static int booke206_initial_map_tsize(CPUPPCState *env) 610 { 611 struct boot_info *bi = env->load_info; 612 hwaddr dt_end; 613 int ps; 614 615 /* Our initial TLB entry needs to cover everything from 0 to 616 the device tree top */ 617 dt_end = bi->dt_base + bi->dt_size; 618 ps = booke206_page_size_to_tlb(dt_end) + 1; 619 if (ps & 1) { 620 /* e500v2 can only do even TLB size bits */ 621 ps++; 622 } 623 return ps; 624 } 625 626 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 627 { 628 int tsize; 629 630 tsize = booke206_initial_map_tsize(env); 631 return (1ULL << 10 << tsize); 632 } 633 634 static void mmubooke_create_initial_mapping(CPUPPCState *env) 635 { 636 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 637 hwaddr size; 638 int ps; 639 640 ps = booke206_initial_map_tsize(env); 641 size = (ps << MAS1_TSIZE_SHIFT); 642 tlb->mas1 = MAS1_VALID | size; 643 tlb->mas2 = 0; 644 tlb->mas7_3 = 0; 645 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 646 647 env->tlb_dirty = true; 648 } 649 650 static void ppce500_cpu_reset_sec(void *opaque) 651 { 652 PowerPCCPU *cpu = opaque; 653 CPUState *cs = CPU(cpu); 654 655 cpu_reset(cs); 656 657 /* Secondary CPU starts in halted state for now. Needs to change when 658 implementing non-kernel boot. */ 659 cs->halted = 1; 660 cs->exception_index = EXCP_HLT; 661 } 662 663 static void ppce500_cpu_reset(void *opaque) 664 { 665 PowerPCCPU *cpu = opaque; 666 CPUState *cs = CPU(cpu); 667 CPUPPCState *env = &cpu->env; 668 struct boot_info *bi = env->load_info; 669 670 cpu_reset(cs); 671 672 /* Set initial guest state. */ 673 cs->halted = 0; 674 env->gpr[1] = (16<<20) - 8; 675 env->gpr[3] = bi->dt_base; 676 env->gpr[4] = 0; 677 env->gpr[5] = 0; 678 env->gpr[6] = EPAPR_MAGIC; 679 env->gpr[7] = mmubooke_initial_mapsize(env); 680 env->gpr[8] = 0; 681 env->gpr[9] = 0; 682 env->nip = bi->entry; 683 mmubooke_create_initial_mapping(env); 684 } 685 686 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 687 qemu_irq **irqs) 688 { 689 DeviceState *dev; 690 SysBusDevice *s; 691 int i, j, k; 692 693 dev = qdev_create(NULL, TYPE_OPENPIC); 694 qdev_prop_set_uint32(dev, "model", params->mpic_version); 695 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 696 697 qdev_init_nofail(dev); 698 s = SYS_BUS_DEVICE(dev); 699 700 k = 0; 701 for (i = 0; i < smp_cpus; i++) { 702 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 703 sysbus_connect_irq(s, k++, irqs[i][j]); 704 } 705 } 706 707 return dev; 708 } 709 710 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 711 qemu_irq **irqs, Error **errp) 712 { 713 Error *err = NULL; 714 DeviceState *dev; 715 CPUState *cs; 716 717 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 718 qdev_prop_set_uint32(dev, "model", params->mpic_version); 719 720 object_property_set_bool(OBJECT(dev), true, "realized", &err); 721 if (err) { 722 error_propagate(errp, err); 723 object_unparent(OBJECT(dev)); 724 return NULL; 725 } 726 727 CPU_FOREACH(cs) { 728 if (kvm_openpic_connect_vcpu(dev, cs)) { 729 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 730 __func__); 731 abort(); 732 } 733 } 734 735 return dev; 736 } 737 738 static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params, 739 MemoryRegion *ccsr, qemu_irq **irqs) 740 { 741 qemu_irq *mpic; 742 DeviceState *dev = NULL; 743 SysBusDevice *s; 744 int i; 745 746 mpic = g_new0(qemu_irq, 256); 747 748 if (kvm_enabled()) { 749 Error *err = NULL; 750 751 if (machine_kernel_irqchip_allowed(machine)) { 752 dev = ppce500_init_mpic_kvm(params, irqs, &err); 753 } 754 if (machine_kernel_irqchip_required(machine) && !dev) { 755 error_reportf_err(err, 756 "kernel_irqchip requested but unavailable: "); 757 exit(1); 758 } 759 } 760 761 if (!dev) { 762 dev = ppce500_init_mpic_qemu(params, irqs); 763 } 764 765 for (i = 0; i < 256; i++) { 766 mpic[i] = qdev_get_gpio_in(dev, i); 767 } 768 769 s = SYS_BUS_DEVICE(dev); 770 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 771 s->mmio[0].memory); 772 773 return mpic; 774 } 775 776 static void ppce500_power_off(void *opaque, int line, int on) 777 { 778 if (on) { 779 qemu_system_shutdown_request(); 780 } 781 } 782 783 void ppce500_init(MachineState *machine, PPCE500Params *params) 784 { 785 MemoryRegion *address_space_mem = get_system_memory(); 786 MemoryRegion *ram = g_new(MemoryRegion, 1); 787 PCIBus *pci_bus; 788 CPUPPCState *env = NULL; 789 uint64_t loadaddr; 790 hwaddr kernel_base = -1LL; 791 int kernel_size = 0; 792 hwaddr dt_base = 0; 793 hwaddr initrd_base = 0; 794 int initrd_size = 0; 795 hwaddr cur_base = 0; 796 char *filename; 797 hwaddr bios_entry = 0; 798 target_long bios_size; 799 struct boot_info *boot_info; 800 int dt_size; 801 int i; 802 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 803 * 4 respectively */ 804 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 805 qemu_irq **irqs, *mpic; 806 DeviceState *dev; 807 CPUPPCState *firstenv = NULL; 808 MemoryRegion *ccsr_addr_space; 809 SysBusDevice *s; 810 PPCE500CCSRState *ccsr; 811 812 /* Setup CPUs */ 813 if (machine->cpu_model == NULL) { 814 machine->cpu_model = "e500v2_v30"; 815 } 816 817 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 818 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 819 for (i = 0; i < smp_cpus; i++) { 820 PowerPCCPU *cpu; 821 CPUState *cs; 822 qemu_irq *input; 823 824 cpu = cpu_ppc_init(machine->cpu_model); 825 if (cpu == NULL) { 826 fprintf(stderr, "Unable to initialize CPU!\n"); 827 exit(1); 828 } 829 env = &cpu->env; 830 cs = CPU(cpu); 831 832 if (!firstenv) { 833 firstenv = env; 834 } 835 836 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 837 input = (qemu_irq *)env->irq_inputs; 838 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 839 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 840 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 841 env->mpic_iack = params->ccsrbar_base + 842 MPC8544_MPIC_REGS_OFFSET + 0xa0; 843 844 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 845 846 /* Register reset handler */ 847 if (!i) { 848 /* Primary CPU */ 849 struct boot_info *boot_info; 850 boot_info = g_malloc0(sizeof(struct boot_info)); 851 qemu_register_reset(ppce500_cpu_reset, cpu); 852 env->load_info = boot_info; 853 } else { 854 /* Secondary CPUs */ 855 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 856 } 857 } 858 859 env = firstenv; 860 861 /* Fixup Memory size on a alignment boundary */ 862 ram_size &= ~(RAM_SIZES_ALIGN - 1); 863 machine->ram_size = ram_size; 864 865 /* Register Memory */ 866 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 867 memory_region_add_subregion(address_space_mem, 0, ram); 868 869 dev = qdev_create(NULL, "e500-ccsr"); 870 object_property_add_child(qdev_get_machine(), "e500-ccsr", 871 OBJECT(dev), NULL); 872 qdev_init_nofail(dev); 873 ccsr = CCSR(dev); 874 ccsr_addr_space = &ccsr->ccsr_space; 875 memory_region_add_subregion(address_space_mem, params->ccsrbar_base, 876 ccsr_addr_space); 877 878 mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); 879 880 /* Serial */ 881 if (serial_hds[0]) { 882 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 883 0, mpic[42], 399193, 884 serial_hds[0], DEVICE_BIG_ENDIAN); 885 } 886 887 if (serial_hds[1]) { 888 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 889 0, mpic[42], 399193, 890 serial_hds[1], DEVICE_BIG_ENDIAN); 891 } 892 893 /* General Utility device */ 894 dev = qdev_create(NULL, "mpc8544-guts"); 895 qdev_init_nofail(dev); 896 s = SYS_BUS_DEVICE(dev); 897 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 898 sysbus_mmio_get_region(s, 0)); 899 900 /* PCI */ 901 dev = qdev_create(NULL, "e500-pcihost"); 902 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 903 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 904 qdev_init_nofail(dev); 905 s = SYS_BUS_DEVICE(dev); 906 for (i = 0; i < PCI_NUM_PINS; i++) { 907 sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]); 908 } 909 910 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 911 sysbus_mmio_get_region(s, 0)); 912 913 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 914 if (!pci_bus) 915 printf("couldn't create PCI controller!\n"); 916 917 if (pci_bus) { 918 /* Register network interfaces. */ 919 for (i = 0; i < nb_nics; i++) { 920 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 921 } 922 } 923 924 /* Register spinning region */ 925 sysbus_create_simple("e500-spin", params->spin_base, NULL); 926 927 if (cur_base < (32 * 1024 * 1024)) { 928 /* u-boot occupies memory up to 32MB, so load blobs above */ 929 cur_base = (32 * 1024 * 1024); 930 } 931 932 if (params->has_mpc8xxx_gpio) { 933 qemu_irq poweroff_irq; 934 935 dev = qdev_create(NULL, "mpc8xxx_gpio"); 936 s = SYS_BUS_DEVICE(dev); 937 qdev_init_nofail(dev); 938 sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]); 939 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 940 sysbus_mmio_get_region(s, 0)); 941 942 /* Power Off GPIO at Pin 0 */ 943 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 944 qdev_connect_gpio_out(dev, 0, poweroff_irq); 945 } 946 947 /* Platform Bus Device */ 948 if (params->has_platform_bus) { 949 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 950 dev->id = TYPE_PLATFORM_BUS_DEVICE; 951 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs); 952 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size); 953 qdev_init_nofail(dev); 954 s = SYS_BUS_DEVICE(dev); 955 956 for (i = 0; i < params->platform_bus_num_irqs; i++) { 957 int irqn = params->platform_bus_first_irq + i; 958 sysbus_connect_irq(s, i, mpic[irqn]); 959 } 960 961 memory_region_add_subregion(address_space_mem, 962 params->platform_bus_base, 963 sysbus_mmio_get_region(s, 0)); 964 } 965 966 /* Load kernel. */ 967 if (machine->kernel_filename) { 968 kernel_base = cur_base; 969 kernel_size = load_image_targphys(machine->kernel_filename, 970 cur_base, 971 ram_size - cur_base); 972 if (kernel_size < 0) { 973 fprintf(stderr, "qemu: could not load kernel '%s'\n", 974 machine->kernel_filename); 975 exit(1); 976 } 977 978 cur_base += kernel_size; 979 } 980 981 /* Load initrd. */ 982 if (machine->initrd_filename) { 983 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 984 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 985 ram_size - initrd_base); 986 987 if (initrd_size < 0) { 988 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 989 machine->initrd_filename); 990 exit(1); 991 } 992 993 cur_base = initrd_base + initrd_size; 994 } 995 996 /* 997 * Smart firmware defaults ahead! 998 * 999 * We follow the following table to select which payload we execute. 1000 * 1001 * -kernel | -bios | payload 1002 * ---------+-------+--------- 1003 * N | Y | u-boot 1004 * N | N | u-boot 1005 * Y | Y | u-boot 1006 * Y | N | kernel 1007 * 1008 * This ensures backwards compatibility with how we used to expose 1009 * -kernel to users but allows them to run through u-boot as well. 1010 */ 1011 if (bios_name == NULL) { 1012 if (machine->kernel_filename) { 1013 bios_name = machine->kernel_filename; 1014 } else { 1015 bios_name = "u-boot.e500"; 1016 } 1017 } 1018 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1019 1020 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 1021 1, PPC_ELF_MACHINE, 0, 0); 1022 if (bios_size < 0) { 1023 /* 1024 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1025 * ePAPR compliant kernel 1026 */ 1027 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1028 NULL, NULL); 1029 if (kernel_size < 0) { 1030 fprintf(stderr, "qemu: could not load firmware '%s'\n", filename); 1031 exit(1); 1032 } 1033 } 1034 g_free(filename); 1035 1036 /* Reserve space for dtb */ 1037 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1038 1039 dt_size = ppce500_prep_device_tree(machine, params, dt_base, 1040 initrd_base, initrd_size, 1041 kernel_base, kernel_size); 1042 if (dt_size < 0) { 1043 fprintf(stderr, "couldn't load device tree\n"); 1044 exit(1); 1045 } 1046 assert(dt_size < DTB_MAX_SIZE); 1047 1048 boot_info = env->load_info; 1049 boot_info->entry = bios_entry; 1050 boot_info->dt_base = dt_base; 1051 boot_info->dt_size = dt_size; 1052 } 1053 1054 static int e500_ccsr_initfn(SysBusDevice *dev) 1055 { 1056 PPCE500CCSRState *ccsr; 1057 1058 ccsr = CCSR(dev); 1059 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 1060 MPC8544_CCSRBAR_SIZE); 1061 return 0; 1062 } 1063 1064 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 1065 { 1066 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1067 k->init = e500_ccsr_initfn; 1068 } 1069 1070 static const TypeInfo e500_ccsr_info = { 1071 .name = TYPE_CCSR, 1072 .parent = TYPE_SYS_BUS_DEVICE, 1073 .instance_size = sizeof(PPCE500CCSRState), 1074 .class_init = e500_ccsr_class_init, 1075 }; 1076 1077 static void e500_register_types(void) 1078 { 1079 type_register_static(&e500_ccsr_info); 1080 } 1081 1082 type_init(e500_register_types) 1083