1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu-common.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "e500.h" 22 #include "e500-ccsr.h" 23 #include "net/net.h" 24 #include "qemu/config-file.h" 25 #include "hw/char/serial.h" 26 #include "hw/pci/pci.h" 27 #include "hw/boards.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "sysemu/reset.h" 31 #include "sysemu/runstate.h" 32 #include "kvm_ppc.h" 33 #include "sysemu/device_tree.h" 34 #include "hw/ppc/openpic.h" 35 #include "hw/ppc/openpic_kvm.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/loader.h" 39 #include "elf.h" 40 #include "hw/sysbus.h" 41 #include "exec/address-spaces.h" 42 #include "qemu/host-utils.h" 43 #include "qemu/option.h" 44 #include "hw/pci-host/ppce500.h" 45 #include "qemu/error-report.h" 46 #include "hw/platform-bus.h" 47 #include "hw/net/fsl_etsec/etsec.h" 48 #include "hw/i2c/i2c.h" 49 #include "hw/irq.h" 50 51 #define EPAPR_MAGIC (0x45504150) 52 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 53 #define DTC_LOAD_PAD 0x1800000 54 #define DTC_PAD_MASK 0xFFFFF 55 #define DTB_MAX_SIZE (8 * MiB) 56 #define INITRD_LOAD_PAD 0x2000000 57 #define INITRD_PAD_MASK 0xFFFFFF 58 59 #define RAM_SIZES_ALIGN (64 * MiB) 60 61 /* TODO: parameterize */ 62 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 63 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 64 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 65 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 66 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 67 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 68 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 69 #define MPC8544_UTIL_OFFSET 0xe0000ULL 70 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 71 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 72 #define MPC8XXX_GPIO_IRQ 47 73 #define MPC8544_I2C_IRQ 43 74 #define RTC_REGS_OFFSET 0x68 75 76 struct boot_info 77 { 78 uint32_t dt_base; 79 uint32_t dt_size; 80 uint32_t entry; 81 }; 82 83 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 84 int nr_slots, int *len) 85 { 86 int i = 0; 87 int slot; 88 int pci_irq; 89 int host_irq; 90 int last_slot = first_slot + nr_slots; 91 uint32_t *pci_map; 92 93 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 94 pci_map = g_malloc(*len); 95 96 for (slot = first_slot; slot < last_slot; slot++) { 97 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 98 pci_map[i++] = cpu_to_be32(slot << 11); 99 pci_map[i++] = cpu_to_be32(0x0); 100 pci_map[i++] = cpu_to_be32(0x0); 101 pci_map[i++] = cpu_to_be32(pci_irq + 1); 102 pci_map[i++] = cpu_to_be32(mpic); 103 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 104 pci_map[i++] = cpu_to_be32(host_irq + 1); 105 pci_map[i++] = cpu_to_be32(0x1); 106 } 107 } 108 109 assert((i * sizeof(uint32_t)) == *len); 110 111 return pci_map; 112 } 113 114 static void dt_serial_create(void *fdt, unsigned long long offset, 115 const char *soc, const char *mpic, 116 const char *alias, int idx, bool defcon) 117 { 118 char *ser; 119 120 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 121 qemu_fdt_add_subnode(fdt, ser); 122 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 123 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 124 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 125 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 126 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 127 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 128 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 129 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 130 131 if (defcon) { 132 /* 133 * "linux,stdout-path" and "stdout" properties are deprecated by linux 134 * kernel. New platforms should only use the "stdout-path" property. Set 135 * the new property and continue using older property to remain 136 * compatible with the existing firmware. 137 */ 138 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 139 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 140 } 141 g_free(ser); 142 } 143 144 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 145 { 146 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 147 int irq0 = MPC8XXX_GPIO_IRQ; 148 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 149 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 150 int gpio_ph; 151 152 qemu_fdt_add_subnode(fdt, node); 153 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 154 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 155 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 156 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 157 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 158 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 159 gpio_ph = qemu_fdt_alloc_phandle(fdt); 160 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 161 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 162 163 /* Power Off Pin */ 164 qemu_fdt_add_subnode(fdt, poweroff); 165 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 166 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 167 168 g_free(node); 169 g_free(poweroff); 170 } 171 172 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 173 { 174 int offset = RTC_REGS_OFFSET; 175 176 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 177 qemu_fdt_add_subnode(fdt, rtc); 178 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 179 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 180 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 181 182 g_free(rtc); 183 } 184 185 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 186 const char *alias) 187 { 188 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 189 int irq0 = MPC8544_I2C_IRQ; 190 191 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 192 qemu_fdt_add_subnode(fdt, i2c); 193 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 194 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 195 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 196 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 197 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 198 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 199 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 200 201 g_free(i2c); 202 } 203 204 205 typedef struct PlatformDevtreeData { 206 void *fdt; 207 const char *mpic; 208 int irq_start; 209 const char *node; 210 PlatformBusDevice *pbus; 211 } PlatformDevtreeData; 212 213 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 214 { 215 eTSEC *etsec = ETSEC_COMMON(sbdev); 216 PlatformBusDevice *pbus = data->pbus; 217 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 218 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 219 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 220 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 221 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 222 gchar *group = g_strdup_printf("%s/queue-group", node); 223 void *fdt = data->fdt; 224 225 assert((int64_t)mmio0 >= 0); 226 assert(irq0 >= 0); 227 assert(irq1 >= 0); 228 assert(irq2 >= 0); 229 230 qemu_fdt_add_subnode(fdt, node); 231 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 232 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 233 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 234 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 235 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 236 237 qemu_fdt_add_subnode(fdt, group); 238 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 239 qemu_fdt_setprop_cells(fdt, group, "interrupts", 240 data->irq_start + irq0, 0x2, 241 data->irq_start + irq1, 0x2, 242 data->irq_start + irq2, 0x2); 243 244 g_free(node); 245 g_free(group); 246 247 return 0; 248 } 249 250 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 251 { 252 PlatformDevtreeData *data = opaque; 253 bool matched = false; 254 255 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 256 create_devtree_etsec(sbdev, data); 257 matched = true; 258 } 259 260 if (!matched) { 261 error_report("Device %s is not supported by this machine yet.", 262 qdev_fw_name(DEVICE(sbdev))); 263 exit(1); 264 } 265 } 266 267 static void platform_bus_create_devtree(PPCE500MachineState *pms, 268 void *fdt, const char *mpic) 269 { 270 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 271 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 272 const char platcomp[] = "qemu,platform\0simple-bus"; 273 uint64_t addr = pmc->platform_bus_base; 274 uint64_t size = pmc->platform_bus_size; 275 int irq_start = pmc->platform_bus_first_irq; 276 277 /* Create a /platform node that we can put all devices into */ 278 279 qemu_fdt_add_subnode(fdt, node); 280 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 281 282 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 283 address and size */ 284 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 285 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 286 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 287 288 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 289 290 /* Create dt nodes for dynamic devices */ 291 PlatformDevtreeData data = { 292 .fdt = fdt, 293 .mpic = mpic, 294 .irq_start = irq_start, 295 .node = node, 296 .pbus = pms->pbus_dev, 297 }; 298 299 /* Loop through all dynamic sysbus devices and create nodes for them */ 300 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 301 302 g_free(node); 303 } 304 305 static int ppce500_load_device_tree(PPCE500MachineState *pms, 306 hwaddr addr, 307 hwaddr initrd_base, 308 hwaddr initrd_size, 309 hwaddr kernel_base, 310 hwaddr kernel_size, 311 bool dry_run) 312 { 313 MachineState *machine = MACHINE(pms); 314 unsigned int smp_cpus = machine->smp.cpus; 315 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 316 CPUPPCState *env = first_cpu->env_ptr; 317 int ret = -1; 318 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 319 int fdt_size; 320 void *fdt; 321 uint8_t hypercall[16]; 322 uint32_t clock_freq = 400000000; 323 uint32_t tb_freq = 400000000; 324 int i; 325 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 326 char *soc; 327 char *mpic; 328 uint32_t mpic_ph; 329 uint32_t msi_ph; 330 char *gutil; 331 char *pci; 332 char *msi; 333 uint32_t *pci_map = NULL; 334 int len; 335 uint32_t pci_ranges[14] = 336 { 337 0x2000000, 0x0, pmc->pci_mmio_bus_base, 338 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 339 0x0, 0x20000000, 340 341 0x1000000, 0x0, 0x0, 342 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 343 0x0, 0x10000, 344 }; 345 QemuOpts *machine_opts = qemu_get_machine_opts(); 346 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 347 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 348 349 if (dtb_file) { 350 char *filename; 351 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 352 if (!filename) { 353 goto out; 354 } 355 356 fdt = load_device_tree(filename, &fdt_size); 357 g_free(filename); 358 if (!fdt) { 359 goto out; 360 } 361 goto done; 362 } 363 364 fdt = create_device_tree(&fdt_size); 365 if (fdt == NULL) { 366 goto out; 367 } 368 369 /* Manipulate device tree in memory. */ 370 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 371 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 372 373 qemu_fdt_add_subnode(fdt, "/memory"); 374 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 375 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 376 sizeof(mem_reg_property)); 377 378 qemu_fdt_add_subnode(fdt, "/chosen"); 379 if (initrd_size) { 380 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 381 initrd_base); 382 if (ret < 0) { 383 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 384 } 385 386 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 387 (initrd_base + initrd_size)); 388 if (ret < 0) { 389 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 390 } 391 392 } 393 394 if (kernel_base != -1ULL) { 395 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 396 kernel_base >> 32, kernel_base, 397 kernel_size >> 32, kernel_size); 398 } 399 400 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 401 machine->kernel_cmdline); 402 if (ret < 0) 403 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 404 405 if (kvm_enabled()) { 406 /* Read out host's frequencies */ 407 clock_freq = kvmppc_get_clockfreq(); 408 tb_freq = kvmppc_get_tbfreq(); 409 410 /* indicate KVM hypercall interface */ 411 qemu_fdt_add_subnode(fdt, "/hypervisor"); 412 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 413 "linux,kvm"); 414 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 415 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 416 hypercall, sizeof(hypercall)); 417 /* if KVM supports the idle hcall, set property indicating this */ 418 if (kvmppc_get_hasidle(env)) { 419 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 420 } 421 } 422 423 /* Create CPU nodes */ 424 qemu_fdt_add_subnode(fdt, "/cpus"); 425 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 426 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 427 428 /* We need to generate the cpu nodes in reverse order, so Linux can pick 429 the first node as boot node and be happy */ 430 for (i = smp_cpus - 1; i >= 0; i--) { 431 CPUState *cpu; 432 char *cpu_name; 433 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 434 435 cpu = qemu_get_cpu(i); 436 if (cpu == NULL) { 437 continue; 438 } 439 env = cpu->env_ptr; 440 441 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 442 qemu_fdt_add_subnode(fdt, cpu_name); 443 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 444 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 445 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 447 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 448 env->dcache_line_size); 449 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 450 env->icache_line_size); 451 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 452 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 453 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 454 if (cpu->cpu_index) { 455 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 456 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 457 "spin-table"); 458 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 459 cpu_release_addr); 460 } else { 461 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 462 } 463 g_free(cpu_name); 464 } 465 466 qemu_fdt_add_subnode(fdt, "/aliases"); 467 /* XXX These should go into their respective devices' code */ 468 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 469 qemu_fdt_add_subnode(fdt, soc); 470 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 471 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 472 sizeof(compatible_sb)); 473 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 474 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 475 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 476 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 477 MPC8544_CCSRBAR_SIZE); 478 /* XXX should contain a reasonable value */ 479 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 480 481 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 482 qemu_fdt_add_subnode(fdt, mpic); 483 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 484 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 485 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 486 0x40000); 487 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 488 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 489 mpic_ph = qemu_fdt_alloc_phandle(fdt); 490 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 491 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 492 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 493 494 /* 495 * We have to generate ser1 first, because Linux takes the first 496 * device it finds in the dt as serial output device. And we generate 497 * devices in reverse order to the dt. 498 */ 499 if (serial_hd(1)) { 500 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 501 soc, mpic, "serial1", 1, false); 502 } 503 504 if (serial_hd(0)) { 505 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 506 soc, mpic, "serial0", 0, true); 507 } 508 509 /* i2c */ 510 dt_i2c_create(fdt, soc, mpic, "i2c"); 511 512 dt_rtc_create(fdt, "i2c", "rtc"); 513 514 515 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 516 MPC8544_UTIL_OFFSET); 517 qemu_fdt_add_subnode(fdt, gutil); 518 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 519 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 520 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 521 g_free(gutil); 522 523 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 524 qemu_fdt_add_subnode(fdt, msi); 525 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 526 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 527 msi_ph = qemu_fdt_alloc_phandle(fdt); 528 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 529 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 530 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 531 0xe0, 0x0, 532 0xe1, 0x0, 533 0xe2, 0x0, 534 0xe3, 0x0, 535 0xe4, 0x0, 536 0xe5, 0x0, 537 0xe6, 0x0, 538 0xe7, 0x0); 539 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 540 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 541 g_free(msi); 542 543 pci = g_strdup_printf("/pci@%llx", 544 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 545 qemu_fdt_add_subnode(fdt, pci); 546 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 547 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 548 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 549 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 550 0x0, 0x7); 551 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 552 pmc->pci_first_slot, pmc->pci_nr_slots, 553 &len); 554 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 555 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 556 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 557 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 558 for (i = 0; i < 14; i++) { 559 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 560 } 561 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 562 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 563 qemu_fdt_setprop_cells(fdt, pci, "reg", 564 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 565 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 566 0, 0x1000); 567 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 568 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 569 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 570 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 571 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 572 g_free(pci); 573 574 if (pmc->has_mpc8xxx_gpio) { 575 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 576 } 577 g_free(soc); 578 579 if (pms->pbus_dev) { 580 platform_bus_create_devtree(pms, fdt, mpic); 581 } 582 g_free(mpic); 583 584 pmc->fixup_devtree(fdt); 585 586 if (toplevel_compat) { 587 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 588 strlen(toplevel_compat) + 1); 589 } 590 591 done: 592 if (!dry_run) { 593 qemu_fdt_dumpdtb(fdt, fdt_size); 594 cpu_physical_memory_write(addr, fdt, fdt_size); 595 } 596 ret = fdt_size; 597 g_free(fdt); 598 599 out: 600 g_free(pci_map); 601 602 return ret; 603 } 604 605 typedef struct DeviceTreeParams { 606 PPCE500MachineState *machine; 607 hwaddr addr; 608 hwaddr initrd_base; 609 hwaddr initrd_size; 610 hwaddr kernel_base; 611 hwaddr kernel_size; 612 Notifier notifier; 613 } DeviceTreeParams; 614 615 static void ppce500_reset_device_tree(void *opaque) 616 { 617 DeviceTreeParams *p = opaque; 618 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 619 p->initrd_size, p->kernel_base, p->kernel_size, 620 false); 621 } 622 623 static void ppce500_init_notify(Notifier *notifier, void *data) 624 { 625 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 626 ppce500_reset_device_tree(p); 627 } 628 629 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 630 hwaddr addr, 631 hwaddr initrd_base, 632 hwaddr initrd_size, 633 hwaddr kernel_base, 634 hwaddr kernel_size) 635 { 636 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 637 p->machine = machine; 638 p->addr = addr; 639 p->initrd_base = initrd_base; 640 p->initrd_size = initrd_size; 641 p->kernel_base = kernel_base; 642 p->kernel_size = kernel_size; 643 644 qemu_register_reset(ppce500_reset_device_tree, p); 645 p->notifier.notify = ppce500_init_notify; 646 qemu_add_machine_init_done_notifier(&p->notifier); 647 648 /* Issue the device tree loader once, so that we get the size of the blob */ 649 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 650 kernel_base, kernel_size, true); 651 } 652 653 /* Create -kernel TLB entries for BookE. */ 654 hwaddr booke206_page_size_to_tlb(uint64_t size) 655 { 656 return 63 - clz64(size / KiB); 657 } 658 659 static int booke206_initial_map_tsize(CPUPPCState *env) 660 { 661 struct boot_info *bi = env->load_info; 662 hwaddr dt_end; 663 int ps; 664 665 /* Our initial TLB entry needs to cover everything from 0 to 666 the device tree top */ 667 dt_end = bi->dt_base + bi->dt_size; 668 ps = booke206_page_size_to_tlb(dt_end) + 1; 669 if (ps & 1) { 670 /* e500v2 can only do even TLB size bits */ 671 ps++; 672 } 673 return ps; 674 } 675 676 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 677 { 678 int tsize; 679 680 tsize = booke206_initial_map_tsize(env); 681 return (1ULL << 10 << tsize); 682 } 683 684 static void mmubooke_create_initial_mapping(CPUPPCState *env) 685 { 686 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 687 hwaddr size; 688 int ps; 689 690 ps = booke206_initial_map_tsize(env); 691 size = (ps << MAS1_TSIZE_SHIFT); 692 tlb->mas1 = MAS1_VALID | size; 693 tlb->mas2 = 0; 694 tlb->mas7_3 = 0; 695 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 696 697 env->tlb_dirty = true; 698 } 699 700 static void ppce500_cpu_reset_sec(void *opaque) 701 { 702 PowerPCCPU *cpu = opaque; 703 CPUState *cs = CPU(cpu); 704 705 cpu_reset(cs); 706 707 /* Secondary CPU starts in halted state for now. Needs to change when 708 implementing non-kernel boot. */ 709 cs->halted = 1; 710 cs->exception_index = EXCP_HLT; 711 } 712 713 static void ppce500_cpu_reset(void *opaque) 714 { 715 PowerPCCPU *cpu = opaque; 716 CPUState *cs = CPU(cpu); 717 CPUPPCState *env = &cpu->env; 718 struct boot_info *bi = env->load_info; 719 720 cpu_reset(cs); 721 722 /* Set initial guest state. */ 723 cs->halted = 0; 724 env->gpr[1] = (16 * MiB) - 8; 725 env->gpr[3] = bi->dt_base; 726 env->gpr[4] = 0; 727 env->gpr[5] = 0; 728 env->gpr[6] = EPAPR_MAGIC; 729 env->gpr[7] = mmubooke_initial_mapsize(env); 730 env->gpr[8] = 0; 731 env->gpr[9] = 0; 732 env->nip = bi->entry; 733 mmubooke_create_initial_mapping(env); 734 } 735 736 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 737 IrqLines *irqs) 738 { 739 DeviceState *dev; 740 SysBusDevice *s; 741 int i, j, k; 742 MachineState *machine = MACHINE(pms); 743 unsigned int smp_cpus = machine->smp.cpus; 744 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 745 746 dev = qdev_create(NULL, TYPE_OPENPIC); 747 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 748 &error_fatal); 749 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 750 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 751 752 qdev_init_nofail(dev); 753 s = SYS_BUS_DEVICE(dev); 754 755 k = 0; 756 for (i = 0; i < smp_cpus; i++) { 757 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 758 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 759 } 760 } 761 762 return dev; 763 } 764 765 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 766 IrqLines *irqs, Error **errp) 767 { 768 Error *err = NULL; 769 DeviceState *dev; 770 CPUState *cs; 771 772 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 773 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 774 775 object_property_set_bool(OBJECT(dev), true, "realized", &err); 776 if (err) { 777 error_propagate(errp, err); 778 object_unparent(OBJECT(dev)); 779 return NULL; 780 } 781 782 CPU_FOREACH(cs) { 783 if (kvm_openpic_connect_vcpu(dev, cs)) { 784 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 785 __func__); 786 abort(); 787 } 788 } 789 790 return dev; 791 } 792 793 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 794 MemoryRegion *ccsr, 795 IrqLines *irqs) 796 { 797 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 798 DeviceState *dev = NULL; 799 SysBusDevice *s; 800 801 if (kvm_enabled()) { 802 Error *err = NULL; 803 804 if (kvm_kernel_irqchip_allowed()) { 805 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 806 } 807 if (kvm_kernel_irqchip_required() && !dev) { 808 error_reportf_err(err, 809 "kernel_irqchip requested but unavailable: "); 810 exit(1); 811 } 812 } 813 814 if (!dev) { 815 dev = ppce500_init_mpic_qemu(pms, irqs); 816 } 817 818 s = SYS_BUS_DEVICE(dev); 819 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 820 s->mmio[0].memory); 821 822 return dev; 823 } 824 825 static void ppce500_power_off(void *opaque, int line, int on) 826 { 827 if (on) { 828 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 829 } 830 } 831 832 void ppce500_init(MachineState *machine) 833 { 834 MemoryRegion *address_space_mem = get_system_memory(); 835 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 836 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 837 PCIBus *pci_bus; 838 CPUPPCState *env = NULL; 839 uint64_t loadaddr; 840 hwaddr kernel_base = -1LL; 841 int kernel_size = 0; 842 hwaddr dt_base = 0; 843 hwaddr initrd_base = 0; 844 int initrd_size = 0; 845 hwaddr cur_base = 0; 846 char *filename; 847 const char *payload_name; 848 bool kernel_as_payload; 849 hwaddr bios_entry = 0; 850 target_long payload_size; 851 struct boot_info *boot_info; 852 int dt_size; 853 int i; 854 unsigned int smp_cpus = machine->smp.cpus; 855 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 856 * 4 respectively */ 857 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 858 IrqLines *irqs; 859 DeviceState *dev, *mpicdev; 860 CPUPPCState *firstenv = NULL; 861 MemoryRegion *ccsr_addr_space; 862 SysBusDevice *s; 863 PPCE500CCSRState *ccsr; 864 I2CBus *i2c; 865 866 irqs = g_new0(IrqLines, smp_cpus); 867 for (i = 0; i < smp_cpus; i++) { 868 PowerPCCPU *cpu; 869 CPUState *cs; 870 qemu_irq *input; 871 872 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 873 env = &cpu->env; 874 cs = CPU(cpu); 875 876 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 877 error_report("MMU model %i not supported by this machine", 878 env->mmu_model); 879 exit(1); 880 } 881 882 if (!firstenv) { 883 firstenv = env; 884 } 885 886 input = (qemu_irq *)env->irq_inputs; 887 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 888 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 889 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 890 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 891 892 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 893 894 /* Register reset handler */ 895 if (!i) { 896 /* Primary CPU */ 897 struct boot_info *boot_info; 898 boot_info = g_malloc0(sizeof(struct boot_info)); 899 qemu_register_reset(ppce500_cpu_reset, cpu); 900 env->load_info = boot_info; 901 } else { 902 /* Secondary CPUs */ 903 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 904 } 905 } 906 907 env = firstenv; 908 909 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { 910 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); 911 exit(EXIT_FAILURE); 912 } 913 914 /* Register Memory */ 915 memory_region_add_subregion(address_space_mem, 0, machine->ram); 916 917 dev = qdev_create(NULL, "e500-ccsr"); 918 object_property_add_child(qdev_get_machine(), "e500-ccsr", 919 OBJECT(dev), NULL); 920 qdev_init_nofail(dev); 921 ccsr = CCSR(dev); 922 ccsr_addr_space = &ccsr->ccsr_space; 923 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 924 ccsr_addr_space); 925 926 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 927 928 /* Serial */ 929 if (serial_hd(0)) { 930 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 931 0, qdev_get_gpio_in(mpicdev, 42), 399193, 932 serial_hd(0), DEVICE_BIG_ENDIAN); 933 } 934 935 if (serial_hd(1)) { 936 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 937 0, qdev_get_gpio_in(mpicdev, 42), 399193, 938 serial_hd(1), DEVICE_BIG_ENDIAN); 939 } 940 /* I2C */ 941 dev = qdev_create(NULL, "mpc-i2c"); 942 s = SYS_BUS_DEVICE(dev); 943 qdev_init_nofail(dev); 944 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 945 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 946 sysbus_mmio_get_region(s, 0)); 947 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 948 i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET); 949 950 951 /* General Utility device */ 952 dev = qdev_create(NULL, "mpc8544-guts"); 953 qdev_init_nofail(dev); 954 s = SYS_BUS_DEVICE(dev); 955 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 956 sysbus_mmio_get_region(s, 0)); 957 958 /* PCI */ 959 dev = qdev_create(NULL, "e500-pcihost"); 960 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 961 &error_abort); 962 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 963 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 964 qdev_init_nofail(dev); 965 s = SYS_BUS_DEVICE(dev); 966 for (i = 0; i < PCI_NUM_PINS; i++) { 967 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 968 } 969 970 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 971 sysbus_mmio_get_region(s, 0)); 972 973 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 974 if (!pci_bus) 975 printf("couldn't create PCI controller!\n"); 976 977 if (pci_bus) { 978 /* Register network interfaces. */ 979 for (i = 0; i < nb_nics; i++) { 980 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 981 } 982 } 983 984 /* Register spinning region */ 985 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 986 987 if (pmc->has_mpc8xxx_gpio) { 988 qemu_irq poweroff_irq; 989 990 dev = qdev_create(NULL, "mpc8xxx_gpio"); 991 s = SYS_BUS_DEVICE(dev); 992 qdev_init_nofail(dev); 993 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 994 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 995 sysbus_mmio_get_region(s, 0)); 996 997 /* Power Off GPIO at Pin 0 */ 998 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 999 qdev_connect_gpio_out(dev, 0, poweroff_irq); 1000 } 1001 1002 /* Platform Bus Device */ 1003 if (pmc->has_platform_bus) { 1004 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 1005 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1006 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1007 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1008 qdev_init_nofail(dev); 1009 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1010 1011 s = SYS_BUS_DEVICE(pms->pbus_dev); 1012 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1013 int irqn = pmc->platform_bus_first_irq + i; 1014 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1015 } 1016 1017 memory_region_add_subregion(address_space_mem, 1018 pmc->platform_bus_base, 1019 sysbus_mmio_get_region(s, 0)); 1020 } 1021 1022 /* 1023 * Smart firmware defaults ahead! 1024 * 1025 * We follow the following table to select which payload we execute. 1026 * 1027 * -kernel | -bios | payload 1028 * ---------+-------+--------- 1029 * N | Y | u-boot 1030 * N | N | u-boot 1031 * Y | Y | u-boot 1032 * Y | N | kernel 1033 * 1034 * This ensures backwards compatibility with how we used to expose 1035 * -kernel to users but allows them to run through u-boot as well. 1036 */ 1037 kernel_as_payload = false; 1038 if (bios_name == NULL) { 1039 if (machine->kernel_filename) { 1040 payload_name = machine->kernel_filename; 1041 kernel_as_payload = true; 1042 } else { 1043 payload_name = "u-boot.e500"; 1044 } 1045 } else { 1046 payload_name = bios_name; 1047 } 1048 1049 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1050 if (!filename) { 1051 error_report("could not find firmware/kernel file '%s'", payload_name); 1052 exit(1); 1053 } 1054 1055 payload_size = load_elf(filename, NULL, NULL, NULL, 1056 &bios_entry, &loadaddr, NULL, NULL, 1057 1, PPC_ELF_MACHINE, 0, 0); 1058 if (payload_size < 0) { 1059 /* 1060 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1061 * ePAPR compliant kernel 1062 */ 1063 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1064 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1065 NULL, NULL); 1066 if (payload_size < 0) { 1067 error_report("could not load firmware '%s'", filename); 1068 exit(1); 1069 } 1070 } 1071 1072 g_free(filename); 1073 1074 if (kernel_as_payload) { 1075 kernel_base = loadaddr; 1076 kernel_size = payload_size; 1077 } 1078 1079 cur_base = loadaddr + payload_size; 1080 if (cur_base < 32 * MiB) { 1081 /* u-boot occupies memory up to 32MB, so load blobs above */ 1082 cur_base = 32 * MiB; 1083 } 1084 1085 /* Load bare kernel only if no bios/u-boot has been provided */ 1086 if (machine->kernel_filename && !kernel_as_payload) { 1087 kernel_base = cur_base; 1088 kernel_size = load_image_targphys(machine->kernel_filename, 1089 cur_base, 1090 machine->ram_size - cur_base); 1091 if (kernel_size < 0) { 1092 error_report("could not load kernel '%s'", 1093 machine->kernel_filename); 1094 exit(1); 1095 } 1096 1097 cur_base += kernel_size; 1098 } 1099 1100 /* Load initrd. */ 1101 if (machine->initrd_filename) { 1102 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1103 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1104 machine->ram_size - initrd_base); 1105 1106 if (initrd_size < 0) { 1107 error_report("could not load initial ram disk '%s'", 1108 machine->initrd_filename); 1109 exit(1); 1110 } 1111 1112 cur_base = initrd_base + initrd_size; 1113 } 1114 1115 /* 1116 * Reserve space for dtb behind the kernel image because Linux has a bug 1117 * where it can only handle the dtb if it's within the first 64MB of where 1118 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1119 * ensures enough space between kernel and initrd. 1120 */ 1121 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1122 if (dt_base + DTB_MAX_SIZE > machine->ram_size) { 1123 error_report("not enough memory for device tree"); 1124 exit(1); 1125 } 1126 1127 dt_size = ppce500_prep_device_tree(pms, dt_base, 1128 initrd_base, initrd_size, 1129 kernel_base, kernel_size); 1130 if (dt_size < 0) { 1131 error_report("couldn't load device tree"); 1132 exit(1); 1133 } 1134 assert(dt_size < DTB_MAX_SIZE); 1135 1136 boot_info = env->load_info; 1137 boot_info->entry = bios_entry; 1138 boot_info->dt_base = dt_base; 1139 boot_info->dt_size = dt_size; 1140 } 1141 1142 static void e500_ccsr_initfn(Object *obj) 1143 { 1144 PPCE500CCSRState *ccsr = CCSR(obj); 1145 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1146 MPC8544_CCSRBAR_SIZE); 1147 } 1148 1149 static const TypeInfo e500_ccsr_info = { 1150 .name = TYPE_CCSR, 1151 .parent = TYPE_SYS_BUS_DEVICE, 1152 .instance_size = sizeof(PPCE500CCSRState), 1153 .instance_init = e500_ccsr_initfn, 1154 }; 1155 1156 static const TypeInfo ppce500_info = { 1157 .name = TYPE_PPCE500_MACHINE, 1158 .parent = TYPE_MACHINE, 1159 .abstract = true, 1160 .instance_size = sizeof(PPCE500MachineState), 1161 .class_size = sizeof(PPCE500MachineClass), 1162 }; 1163 1164 static void e500_register_types(void) 1165 { 1166 type_register_static(&e500_ccsr_info); 1167 type_register_static(&ppce500_info); 1168 } 1169 1170 type_init(e500_register_types) 1171