1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qapi/error.h" 19 #include "qemu-common.h" 20 #include "e500.h" 21 #include "e500-ccsr.h" 22 #include "net/net.h" 23 #include "qemu/config-file.h" 24 #include "hw/hw.h" 25 #include "hw/char/serial.h" 26 #include "hw/pci/pci.h" 27 #include "hw/boards.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/device_tree.h" 32 #include "hw/ppc/openpic.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/loader.h" 35 #include "elf.h" 36 #include "hw/sysbus.h" 37 #include "exec/address-spaces.h" 38 #include "qemu/host-utils.h" 39 #include "hw/pci-host/ppce500.h" 40 #include "qemu/error-report.h" 41 #include "hw/platform-bus.h" 42 #include "hw/net/fsl_etsec/etsec.h" 43 44 #define EPAPR_MAGIC (0x45504150) 45 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 46 #define DTC_LOAD_PAD 0x1800000 47 #define DTC_PAD_MASK 0xFFFFF 48 #define DTB_MAX_SIZE (8 * 1024 * 1024) 49 #define INITRD_LOAD_PAD 0x2000000 50 #define INITRD_PAD_MASK 0xFFFFFF 51 52 #define RAM_SIZES_ALIGN (64UL << 20) 53 54 /* TODO: parameterize */ 55 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 56 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 57 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 58 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 59 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 60 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 62 #define MPC8544_UTIL_OFFSET 0xe0000ULL 63 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 64 #define MPC8XXX_GPIO_IRQ 47 65 66 struct boot_info 67 { 68 uint32_t dt_base; 69 uint32_t dt_size; 70 uint32_t entry; 71 }; 72 73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 74 int nr_slots, int *len) 75 { 76 int i = 0; 77 int slot; 78 int pci_irq; 79 int host_irq; 80 int last_slot = first_slot + nr_slots; 81 uint32_t *pci_map; 82 83 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 84 pci_map = g_malloc(*len); 85 86 for (slot = first_slot; slot < last_slot; slot++) { 87 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 88 pci_map[i++] = cpu_to_be32(slot << 11); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(pci_irq + 1); 92 pci_map[i++] = cpu_to_be32(mpic); 93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 94 pci_map[i++] = cpu_to_be32(host_irq + 1); 95 pci_map[i++] = cpu_to_be32(0x1); 96 } 97 } 98 99 assert((i * sizeof(uint32_t)) == *len); 100 101 return pci_map; 102 } 103 104 static void dt_serial_create(void *fdt, unsigned long long offset, 105 const char *soc, const char *mpic, 106 const char *alias, int idx, bool defcon) 107 { 108 char ser[128]; 109 110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 111 qemu_fdt_add_subnode(fdt, ser); 112 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 113 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 114 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 115 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 116 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 117 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 118 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 119 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 120 121 if (defcon) { 122 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 123 } 124 } 125 126 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 127 { 128 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 129 int irq0 = MPC8XXX_GPIO_IRQ; 130 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 131 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 132 int gpio_ph; 133 134 qemu_fdt_add_subnode(fdt, node); 135 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 136 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 137 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 138 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 139 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 140 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 141 gpio_ph = qemu_fdt_alloc_phandle(fdt); 142 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 143 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 144 145 /* Power Off Pin */ 146 qemu_fdt_add_subnode(fdt, poweroff); 147 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 148 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 149 150 g_free(node); 151 g_free(poweroff); 152 } 153 154 typedef struct PlatformDevtreeData { 155 void *fdt; 156 const char *mpic; 157 int irq_start; 158 const char *node; 159 PlatformBusDevice *pbus; 160 } PlatformDevtreeData; 161 162 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 163 { 164 eTSEC *etsec = ETSEC_COMMON(sbdev); 165 PlatformBusDevice *pbus = data->pbus; 166 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 167 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 168 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 169 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 170 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 171 gchar *group = g_strdup_printf("%s/queue-group", node); 172 void *fdt = data->fdt; 173 174 assert((int64_t)mmio0 >= 0); 175 assert(irq0 >= 0); 176 assert(irq1 >= 0); 177 assert(irq2 >= 0); 178 179 qemu_fdt_add_subnode(fdt, node); 180 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 181 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 182 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 183 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 184 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 185 186 qemu_fdt_add_subnode(fdt, group); 187 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 188 qemu_fdt_setprop_cells(fdt, group, "interrupts", 189 data->irq_start + irq0, 0x2, 190 data->irq_start + irq1, 0x2, 191 data->irq_start + irq2, 0x2); 192 193 g_free(node); 194 g_free(group); 195 196 return 0; 197 } 198 199 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 200 { 201 PlatformDevtreeData *data = opaque; 202 bool matched = false; 203 204 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 205 create_devtree_etsec(sbdev, data); 206 matched = true; 207 } 208 209 if (!matched) { 210 error_report("Device %s is not supported by this machine yet.", 211 qdev_fw_name(DEVICE(sbdev))); 212 exit(1); 213 } 214 } 215 216 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt, 217 const char *mpic) 218 { 219 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base); 220 const char platcomp[] = "qemu,platform\0simple-bus"; 221 uint64_t addr = params->platform_bus_base; 222 uint64_t size = params->platform_bus_size; 223 int irq_start = params->platform_bus_first_irq; 224 PlatformBusDevice *pbus; 225 DeviceState *dev; 226 227 /* Create a /platform node that we can put all devices into */ 228 229 qemu_fdt_add_subnode(fdt, node); 230 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 231 232 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 233 address and size */ 234 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 235 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 236 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 237 238 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 239 240 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE); 241 pbus = PLATFORM_BUS_DEVICE(dev); 242 243 /* We can only create dt nodes for dynamic devices when they're ready */ 244 if (pbus->done_gathering) { 245 PlatformDevtreeData data = { 246 .fdt = fdt, 247 .mpic = mpic, 248 .irq_start = irq_start, 249 .node = node, 250 .pbus = pbus, 251 }; 252 253 /* Loop through all dynamic sysbus devices and create nodes for them */ 254 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 255 } 256 257 g_free(node); 258 } 259 260 static int ppce500_load_device_tree(MachineState *machine, 261 PPCE500Params *params, 262 hwaddr addr, 263 hwaddr initrd_base, 264 hwaddr initrd_size, 265 hwaddr kernel_base, 266 hwaddr kernel_size, 267 bool dry_run) 268 { 269 CPUPPCState *env = first_cpu->env_ptr; 270 int ret = -1; 271 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 272 int fdt_size; 273 void *fdt; 274 uint8_t hypercall[16]; 275 uint32_t clock_freq = 400000000; 276 uint32_t tb_freq = 400000000; 277 int i; 278 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 279 char soc[128]; 280 char mpic[128]; 281 uint32_t mpic_ph; 282 uint32_t msi_ph; 283 char gutil[128]; 284 char pci[128]; 285 char msi[128]; 286 uint32_t *pci_map = NULL; 287 int len; 288 uint32_t pci_ranges[14] = 289 { 290 0x2000000, 0x0, params->pci_mmio_bus_base, 291 params->pci_mmio_base >> 32, params->pci_mmio_base, 292 0x0, 0x20000000, 293 294 0x1000000, 0x0, 0x0, 295 params->pci_pio_base >> 32, params->pci_pio_base, 296 0x0, 0x10000, 297 }; 298 QemuOpts *machine_opts = qemu_get_machine_opts(); 299 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 300 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 301 302 if (dtb_file) { 303 char *filename; 304 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 305 if (!filename) { 306 goto out; 307 } 308 309 fdt = load_device_tree(filename, &fdt_size); 310 g_free(filename); 311 if (!fdt) { 312 goto out; 313 } 314 goto done; 315 } 316 317 fdt = create_device_tree(&fdt_size); 318 if (fdt == NULL) { 319 goto out; 320 } 321 322 /* Manipulate device tree in memory. */ 323 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 324 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 325 326 qemu_fdt_add_subnode(fdt, "/memory"); 327 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 328 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 329 sizeof(mem_reg_property)); 330 331 qemu_fdt_add_subnode(fdt, "/chosen"); 332 if (initrd_size) { 333 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 334 initrd_base); 335 if (ret < 0) { 336 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 337 } 338 339 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 340 (initrd_base + initrd_size)); 341 if (ret < 0) { 342 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 343 } 344 345 } 346 347 if (kernel_base != -1ULL) { 348 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 349 kernel_base >> 32, kernel_base, 350 kernel_size >> 32, kernel_size); 351 } 352 353 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 354 machine->kernel_cmdline); 355 if (ret < 0) 356 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 357 358 if (kvm_enabled()) { 359 /* Read out host's frequencies */ 360 clock_freq = kvmppc_get_clockfreq(); 361 tb_freq = kvmppc_get_tbfreq(); 362 363 /* indicate KVM hypercall interface */ 364 qemu_fdt_add_subnode(fdt, "/hypervisor"); 365 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 366 "linux,kvm"); 367 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 368 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 369 hypercall, sizeof(hypercall)); 370 /* if KVM supports the idle hcall, set property indicating this */ 371 if (kvmppc_get_hasidle(env)) { 372 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 373 } 374 } 375 376 /* Create CPU nodes */ 377 qemu_fdt_add_subnode(fdt, "/cpus"); 378 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 379 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 380 381 /* We need to generate the cpu nodes in reverse order, so Linux can pick 382 the first node as boot node and be happy */ 383 for (i = smp_cpus - 1; i >= 0; i--) { 384 CPUState *cpu; 385 PowerPCCPU *pcpu; 386 char cpu_name[128]; 387 uint64_t cpu_release_addr = params->spin_base + (i * 0x20); 388 389 cpu = qemu_get_cpu(i); 390 if (cpu == NULL) { 391 continue; 392 } 393 env = cpu->env_ptr; 394 pcpu = POWERPC_CPU(cpu); 395 396 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 397 ppc_get_vcpu_dt_id(pcpu)); 398 qemu_fdt_add_subnode(fdt, cpu_name); 399 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 400 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 401 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 402 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 403 ppc_get_vcpu_dt_id(pcpu)); 404 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 405 env->dcache_line_size); 406 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 407 env->icache_line_size); 408 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 409 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 410 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 411 if (cpu->cpu_index) { 412 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 413 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 414 "spin-table"); 415 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 416 cpu_release_addr); 417 } else { 418 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 419 } 420 } 421 422 qemu_fdt_add_subnode(fdt, "/aliases"); 423 /* XXX These should go into their respective devices' code */ 424 snprintf(soc, sizeof(soc), "/soc@%"PRIx64, params->ccsrbar_base); 425 qemu_fdt_add_subnode(fdt, soc); 426 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 427 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 428 sizeof(compatible_sb)); 429 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 430 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 431 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 432 params->ccsrbar_base >> 32, params->ccsrbar_base, 433 MPC8544_CCSRBAR_SIZE); 434 /* XXX should contain a reasonable value */ 435 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 436 437 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 438 qemu_fdt_add_subnode(fdt, mpic); 439 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 440 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 441 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 442 0x40000); 443 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 444 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 445 mpic_ph = qemu_fdt_alloc_phandle(fdt); 446 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 447 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 448 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 449 450 /* 451 * We have to generate ser1 first, because Linux takes the first 452 * device it finds in the dt as serial output device. And we generate 453 * devices in reverse order to the dt. 454 */ 455 if (serial_hds[1]) { 456 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 457 soc, mpic, "serial1", 1, false); 458 } 459 460 if (serial_hds[0]) { 461 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 462 soc, mpic, "serial0", 0, true); 463 } 464 465 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 466 MPC8544_UTIL_OFFSET); 467 qemu_fdt_add_subnode(fdt, gutil); 468 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 469 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 470 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 471 472 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 473 qemu_fdt_add_subnode(fdt, msi); 474 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 475 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 476 msi_ph = qemu_fdt_alloc_phandle(fdt); 477 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 478 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 479 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 480 0xe0, 0x0, 481 0xe1, 0x0, 482 0xe2, 0x0, 483 0xe3, 0x0, 484 0xe4, 0x0, 485 0xe5, 0x0, 486 0xe6, 0x0, 487 0xe7, 0x0); 488 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 489 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 490 491 snprintf(pci, sizeof(pci), "/pci@%llx", 492 params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 493 qemu_fdt_add_subnode(fdt, pci); 494 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 495 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 496 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 497 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 498 0x0, 0x7); 499 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 500 params->pci_first_slot, params->pci_nr_slots, 501 &len); 502 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 503 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 504 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 505 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 506 for (i = 0; i < 14; i++) { 507 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 508 } 509 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 510 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 511 qemu_fdt_setprop_cells(fdt, pci, "reg", 512 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 513 (params->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 514 0, 0x1000); 515 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 516 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 517 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 518 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 519 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 520 521 if (params->has_mpc8xxx_gpio) { 522 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 523 } 524 525 if (params->has_platform_bus) { 526 platform_bus_create_devtree(params, fdt, mpic); 527 } 528 529 params->fixup_devtree(params, fdt); 530 531 if (toplevel_compat) { 532 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 533 strlen(toplevel_compat) + 1); 534 } 535 536 done: 537 if (!dry_run) { 538 qemu_fdt_dumpdtb(fdt, fdt_size); 539 cpu_physical_memory_write(addr, fdt, fdt_size); 540 } 541 ret = fdt_size; 542 543 out: 544 g_free(pci_map); 545 546 return ret; 547 } 548 549 typedef struct DeviceTreeParams { 550 MachineState *machine; 551 PPCE500Params params; 552 hwaddr addr; 553 hwaddr initrd_base; 554 hwaddr initrd_size; 555 hwaddr kernel_base; 556 hwaddr kernel_size; 557 Notifier notifier; 558 } DeviceTreeParams; 559 560 static void ppce500_reset_device_tree(void *opaque) 561 { 562 DeviceTreeParams *p = opaque; 563 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base, 564 p->initrd_size, p->kernel_base, p->kernel_size, 565 false); 566 } 567 568 static void ppce500_init_notify(Notifier *notifier, void *data) 569 { 570 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 571 ppce500_reset_device_tree(p); 572 } 573 574 static int ppce500_prep_device_tree(MachineState *machine, 575 PPCE500Params *params, 576 hwaddr addr, 577 hwaddr initrd_base, 578 hwaddr initrd_size, 579 hwaddr kernel_base, 580 hwaddr kernel_size) 581 { 582 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 583 p->machine = machine; 584 p->params = *params; 585 p->addr = addr; 586 p->initrd_base = initrd_base; 587 p->initrd_size = initrd_size; 588 p->kernel_base = kernel_base; 589 p->kernel_size = kernel_size; 590 591 qemu_register_reset(ppce500_reset_device_tree, p); 592 p->notifier.notify = ppce500_init_notify; 593 qemu_add_machine_init_done_notifier(&p->notifier); 594 595 /* Issue the device tree loader once, so that we get the size of the blob */ 596 return ppce500_load_device_tree(machine, params, addr, initrd_base, 597 initrd_size, kernel_base, kernel_size, 598 true); 599 } 600 601 /* Create -kernel TLB entries for BookE. */ 602 hwaddr booke206_page_size_to_tlb(uint64_t size) 603 { 604 return 63 - clz64(size >> 10); 605 } 606 607 static int booke206_initial_map_tsize(CPUPPCState *env) 608 { 609 struct boot_info *bi = env->load_info; 610 hwaddr dt_end; 611 int ps; 612 613 /* Our initial TLB entry needs to cover everything from 0 to 614 the device tree top */ 615 dt_end = bi->dt_base + bi->dt_size; 616 ps = booke206_page_size_to_tlb(dt_end) + 1; 617 if (ps & 1) { 618 /* e500v2 can only do even TLB size bits */ 619 ps++; 620 } 621 return ps; 622 } 623 624 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 625 { 626 int tsize; 627 628 tsize = booke206_initial_map_tsize(env); 629 return (1ULL << 10 << tsize); 630 } 631 632 static void mmubooke_create_initial_mapping(CPUPPCState *env) 633 { 634 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 635 hwaddr size; 636 int ps; 637 638 ps = booke206_initial_map_tsize(env); 639 size = (ps << MAS1_TSIZE_SHIFT); 640 tlb->mas1 = MAS1_VALID | size; 641 tlb->mas2 = 0; 642 tlb->mas7_3 = 0; 643 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 644 645 env->tlb_dirty = true; 646 } 647 648 static void ppce500_cpu_reset_sec(void *opaque) 649 { 650 PowerPCCPU *cpu = opaque; 651 CPUState *cs = CPU(cpu); 652 653 cpu_reset(cs); 654 655 /* Secondary CPU starts in halted state for now. Needs to change when 656 implementing non-kernel boot. */ 657 cs->halted = 1; 658 cs->exception_index = EXCP_HLT; 659 } 660 661 static void ppce500_cpu_reset(void *opaque) 662 { 663 PowerPCCPU *cpu = opaque; 664 CPUState *cs = CPU(cpu); 665 CPUPPCState *env = &cpu->env; 666 struct boot_info *bi = env->load_info; 667 668 cpu_reset(cs); 669 670 /* Set initial guest state. */ 671 cs->halted = 0; 672 env->gpr[1] = (16<<20) - 8; 673 env->gpr[3] = bi->dt_base; 674 env->gpr[4] = 0; 675 env->gpr[5] = 0; 676 env->gpr[6] = EPAPR_MAGIC; 677 env->gpr[7] = mmubooke_initial_mapsize(env); 678 env->gpr[8] = 0; 679 env->gpr[9] = 0; 680 env->nip = bi->entry; 681 mmubooke_create_initial_mapping(env); 682 } 683 684 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 685 qemu_irq **irqs) 686 { 687 DeviceState *dev; 688 SysBusDevice *s; 689 int i, j, k; 690 691 dev = qdev_create(NULL, TYPE_OPENPIC); 692 qdev_prop_set_uint32(dev, "model", params->mpic_version); 693 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 694 695 qdev_init_nofail(dev); 696 s = SYS_BUS_DEVICE(dev); 697 698 k = 0; 699 for (i = 0; i < smp_cpus; i++) { 700 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 701 sysbus_connect_irq(s, k++, irqs[i][j]); 702 } 703 } 704 705 return dev; 706 } 707 708 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 709 qemu_irq **irqs, Error **errp) 710 { 711 Error *err = NULL; 712 DeviceState *dev; 713 CPUState *cs; 714 715 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 716 qdev_prop_set_uint32(dev, "model", params->mpic_version); 717 718 object_property_set_bool(OBJECT(dev), true, "realized", &err); 719 if (err) { 720 error_propagate(errp, err); 721 object_unparent(OBJECT(dev)); 722 return NULL; 723 } 724 725 CPU_FOREACH(cs) { 726 if (kvm_openpic_connect_vcpu(dev, cs)) { 727 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 728 __func__); 729 abort(); 730 } 731 } 732 733 return dev; 734 } 735 736 static qemu_irq *ppce500_init_mpic(MachineState *machine, PPCE500Params *params, 737 MemoryRegion *ccsr, qemu_irq **irqs) 738 { 739 qemu_irq *mpic; 740 DeviceState *dev = NULL; 741 SysBusDevice *s; 742 int i; 743 744 mpic = g_new0(qemu_irq, 256); 745 746 if (kvm_enabled()) { 747 Error *err = NULL; 748 749 if (machine_kernel_irqchip_allowed(machine)) { 750 dev = ppce500_init_mpic_kvm(params, irqs, &err); 751 } 752 if (machine_kernel_irqchip_required(machine) && !dev) { 753 error_reportf_err(err, 754 "kernel_irqchip requested but unavailable: "); 755 exit(1); 756 } 757 } 758 759 if (!dev) { 760 dev = ppce500_init_mpic_qemu(params, irqs); 761 } 762 763 for (i = 0; i < 256; i++) { 764 mpic[i] = qdev_get_gpio_in(dev, i); 765 } 766 767 s = SYS_BUS_DEVICE(dev); 768 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 769 s->mmio[0].memory); 770 771 return mpic; 772 } 773 774 static void ppce500_power_off(void *opaque, int line, int on) 775 { 776 if (on) { 777 qemu_system_shutdown_request(); 778 } 779 } 780 781 void ppce500_init(MachineState *machine, PPCE500Params *params) 782 { 783 MemoryRegion *address_space_mem = get_system_memory(); 784 MemoryRegion *ram = g_new(MemoryRegion, 1); 785 PCIBus *pci_bus; 786 CPUPPCState *env = NULL; 787 uint64_t loadaddr; 788 hwaddr kernel_base = -1LL; 789 int kernel_size = 0; 790 hwaddr dt_base = 0; 791 hwaddr initrd_base = 0; 792 int initrd_size = 0; 793 hwaddr cur_base = 0; 794 char *filename; 795 hwaddr bios_entry = 0; 796 target_long bios_size; 797 struct boot_info *boot_info; 798 int dt_size; 799 int i; 800 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 801 * 4 respectively */ 802 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 803 qemu_irq **irqs, *mpic; 804 DeviceState *dev; 805 CPUPPCState *firstenv = NULL; 806 MemoryRegion *ccsr_addr_space; 807 SysBusDevice *s; 808 PPCE500CCSRState *ccsr; 809 810 /* Setup CPUs */ 811 if (machine->cpu_model == NULL) { 812 machine->cpu_model = "e500v2_v30"; 813 } 814 815 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 816 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 817 for (i = 0; i < smp_cpus; i++) { 818 PowerPCCPU *cpu; 819 CPUState *cs; 820 qemu_irq *input; 821 822 cpu = cpu_ppc_init(machine->cpu_model); 823 if (cpu == NULL) { 824 fprintf(stderr, "Unable to initialize CPU!\n"); 825 exit(1); 826 } 827 env = &cpu->env; 828 cs = CPU(cpu); 829 830 if (!firstenv) { 831 firstenv = env; 832 } 833 834 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 835 input = (qemu_irq *)env->irq_inputs; 836 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 837 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 838 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 839 env->mpic_iack = params->ccsrbar_base + 840 MPC8544_MPIC_REGS_OFFSET + 0xa0; 841 842 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 843 844 /* Register reset handler */ 845 if (!i) { 846 /* Primary CPU */ 847 struct boot_info *boot_info; 848 boot_info = g_malloc0(sizeof(struct boot_info)); 849 qemu_register_reset(ppce500_cpu_reset, cpu); 850 env->load_info = boot_info; 851 } else { 852 /* Secondary CPUs */ 853 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 854 } 855 } 856 857 env = firstenv; 858 859 /* Fixup Memory size on a alignment boundary */ 860 ram_size &= ~(RAM_SIZES_ALIGN - 1); 861 machine->ram_size = ram_size; 862 863 /* Register Memory */ 864 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 865 memory_region_add_subregion(address_space_mem, 0, ram); 866 867 dev = qdev_create(NULL, "e500-ccsr"); 868 object_property_add_child(qdev_get_machine(), "e500-ccsr", 869 OBJECT(dev), NULL); 870 qdev_init_nofail(dev); 871 ccsr = CCSR(dev); 872 ccsr_addr_space = &ccsr->ccsr_space; 873 memory_region_add_subregion(address_space_mem, params->ccsrbar_base, 874 ccsr_addr_space); 875 876 mpic = ppce500_init_mpic(machine, params, ccsr_addr_space, irqs); 877 878 /* Serial */ 879 if (serial_hds[0]) { 880 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 881 0, mpic[42], 399193, 882 serial_hds[0], DEVICE_BIG_ENDIAN); 883 } 884 885 if (serial_hds[1]) { 886 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 887 0, mpic[42], 399193, 888 serial_hds[1], DEVICE_BIG_ENDIAN); 889 } 890 891 /* General Utility device */ 892 dev = qdev_create(NULL, "mpc8544-guts"); 893 qdev_init_nofail(dev); 894 s = SYS_BUS_DEVICE(dev); 895 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 896 sysbus_mmio_get_region(s, 0)); 897 898 /* PCI */ 899 dev = qdev_create(NULL, "e500-pcihost"); 900 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 901 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 902 qdev_init_nofail(dev); 903 s = SYS_BUS_DEVICE(dev); 904 for (i = 0; i < PCI_NUM_PINS; i++) { 905 sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]); 906 } 907 908 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 909 sysbus_mmio_get_region(s, 0)); 910 911 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 912 if (!pci_bus) 913 printf("couldn't create PCI controller!\n"); 914 915 if (pci_bus) { 916 /* Register network interfaces. */ 917 for (i = 0; i < nb_nics; i++) { 918 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 919 } 920 } 921 922 /* Register spinning region */ 923 sysbus_create_simple("e500-spin", params->spin_base, NULL); 924 925 if (cur_base < (32 * 1024 * 1024)) { 926 /* u-boot occupies memory up to 32MB, so load blobs above */ 927 cur_base = (32 * 1024 * 1024); 928 } 929 930 if (params->has_mpc8xxx_gpio) { 931 qemu_irq poweroff_irq; 932 933 dev = qdev_create(NULL, "mpc8xxx_gpio"); 934 s = SYS_BUS_DEVICE(dev); 935 qdev_init_nofail(dev); 936 sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]); 937 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 938 sysbus_mmio_get_region(s, 0)); 939 940 /* Power Off GPIO at Pin 0 */ 941 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 942 qdev_connect_gpio_out(dev, 0, poweroff_irq); 943 } 944 945 /* Platform Bus Device */ 946 if (params->has_platform_bus) { 947 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 948 dev->id = TYPE_PLATFORM_BUS_DEVICE; 949 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs); 950 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size); 951 qdev_init_nofail(dev); 952 s = SYS_BUS_DEVICE(dev); 953 954 for (i = 0; i < params->platform_bus_num_irqs; i++) { 955 int irqn = params->platform_bus_first_irq + i; 956 sysbus_connect_irq(s, i, mpic[irqn]); 957 } 958 959 memory_region_add_subregion(address_space_mem, 960 params->platform_bus_base, 961 sysbus_mmio_get_region(s, 0)); 962 } 963 964 /* Load kernel. */ 965 if (machine->kernel_filename) { 966 kernel_base = cur_base; 967 kernel_size = load_image_targphys(machine->kernel_filename, 968 cur_base, 969 ram_size - cur_base); 970 if (kernel_size < 0) { 971 fprintf(stderr, "qemu: could not load kernel '%s'\n", 972 machine->kernel_filename); 973 exit(1); 974 } 975 976 cur_base += kernel_size; 977 } 978 979 /* Load initrd. */ 980 if (machine->initrd_filename) { 981 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 982 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 983 ram_size - initrd_base); 984 985 if (initrd_size < 0) { 986 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 987 machine->initrd_filename); 988 exit(1); 989 } 990 991 cur_base = initrd_base + initrd_size; 992 } 993 994 /* 995 * Smart firmware defaults ahead! 996 * 997 * We follow the following table to select which payload we execute. 998 * 999 * -kernel | -bios | payload 1000 * ---------+-------+--------- 1001 * N | Y | u-boot 1002 * N | N | u-boot 1003 * Y | Y | u-boot 1004 * Y | N | kernel 1005 * 1006 * This ensures backwards compatibility with how we used to expose 1007 * -kernel to users but allows them to run through u-boot as well. 1008 */ 1009 if (bios_name == NULL) { 1010 if (machine->kernel_filename) { 1011 bios_name = machine->kernel_filename; 1012 } else { 1013 bios_name = "u-boot.e500"; 1014 } 1015 } 1016 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1017 1018 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL, 1019 1, PPC_ELF_MACHINE, 0, 0); 1020 if (bios_size < 0) { 1021 /* 1022 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1023 * ePAPR compliant kernel 1024 */ 1025 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1026 NULL, NULL); 1027 if (kernel_size < 0) { 1028 fprintf(stderr, "qemu: could not load firmware '%s'\n", filename); 1029 exit(1); 1030 } 1031 } 1032 g_free(filename); 1033 1034 /* Reserve space for dtb */ 1035 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1036 1037 dt_size = ppce500_prep_device_tree(machine, params, dt_base, 1038 initrd_base, initrd_size, 1039 kernel_base, kernel_size); 1040 if (dt_size < 0) { 1041 fprintf(stderr, "couldn't load device tree\n"); 1042 exit(1); 1043 } 1044 assert(dt_size < DTB_MAX_SIZE); 1045 1046 boot_info = env->load_info; 1047 boot_info->entry = bios_entry; 1048 boot_info->dt_base = dt_base; 1049 boot_info->dt_size = dt_size; 1050 } 1051 1052 static int e500_ccsr_initfn(SysBusDevice *dev) 1053 { 1054 PPCE500CCSRState *ccsr; 1055 1056 ccsr = CCSR(dev); 1057 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 1058 MPC8544_CCSRBAR_SIZE); 1059 return 0; 1060 } 1061 1062 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 1063 { 1064 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 1065 k->init = e500_ccsr_initfn; 1066 } 1067 1068 static const TypeInfo e500_ccsr_info = { 1069 .name = TYPE_CCSR, 1070 .parent = TYPE_SYS_BUS_DEVICE, 1071 .instance_size = sizeof(PPCE500CCSRState), 1072 .class_init = e500_ccsr_class_init, 1073 }; 1074 1075 static void e500_register_types(void) 1076 { 1077 type_register_static(&e500_ccsr_info); 1078 } 1079 1080 type_init(e500_register_types) 1081