1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "qemu/units.h" 19 #include "qapi/error.h" 20 #include "e500.h" 21 #include "e500-ccsr.h" 22 #include "net/net.h" 23 #include "qemu/config-file.h" 24 #include "hw/hw.h" 25 #include "hw/char/serial.h" 26 #include "hw/pci/pci.h" 27 #include "hw/boards.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/kvm.h" 30 #include "kvm_ppc.h" 31 #include "sysemu/device_tree.h" 32 #include "hw/ppc/openpic.h" 33 #include "hw/ppc/openpic_kvm.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/loader.h" 36 #include "elf.h" 37 #include "hw/sysbus.h" 38 #include "exec/address-spaces.h" 39 #include "qemu/host-utils.h" 40 #include "qemu/option.h" 41 #include "hw/pci-host/ppce500.h" 42 #include "qemu/error-report.h" 43 #include "hw/platform-bus.h" 44 #include "hw/net/fsl_etsec/etsec.h" 45 #include "hw/i2c/i2c.h" 46 47 #define EPAPR_MAGIC (0x45504150) 48 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 49 #define DTC_LOAD_PAD 0x1800000 50 #define DTC_PAD_MASK 0xFFFFF 51 #define DTB_MAX_SIZE (8 * MiB) 52 #define INITRD_LOAD_PAD 0x2000000 53 #define INITRD_PAD_MASK 0xFFFFFF 54 55 #define RAM_SIZES_ALIGN (64 * MiB) 56 57 /* TODO: parameterize */ 58 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 59 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 60 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 61 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 62 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 63 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 64 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 65 #define MPC8544_UTIL_OFFSET 0xe0000ULL 66 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL 67 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL 68 #define MPC8XXX_GPIO_IRQ 47 69 #define MPC8544_I2C_IRQ 43 70 #define RTC_REGS_OFFSET 0x68 71 72 struct boot_info 73 { 74 uint32_t dt_base; 75 uint32_t dt_size; 76 uint32_t entry; 77 }; 78 79 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 80 int nr_slots, int *len) 81 { 82 int i = 0; 83 int slot; 84 int pci_irq; 85 int host_irq; 86 int last_slot = first_slot + nr_slots; 87 uint32_t *pci_map; 88 89 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 90 pci_map = g_malloc(*len); 91 92 for (slot = first_slot; slot < last_slot; slot++) { 93 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 94 pci_map[i++] = cpu_to_be32(slot << 11); 95 pci_map[i++] = cpu_to_be32(0x0); 96 pci_map[i++] = cpu_to_be32(0x0); 97 pci_map[i++] = cpu_to_be32(pci_irq + 1); 98 pci_map[i++] = cpu_to_be32(mpic); 99 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 100 pci_map[i++] = cpu_to_be32(host_irq + 1); 101 pci_map[i++] = cpu_to_be32(0x1); 102 } 103 } 104 105 assert((i * sizeof(uint32_t)) == *len); 106 107 return pci_map; 108 } 109 110 static void dt_serial_create(void *fdt, unsigned long long offset, 111 const char *soc, const char *mpic, 112 const char *alias, int idx, bool defcon) 113 { 114 char *ser; 115 116 ser = g_strdup_printf("%s/serial@%llx", soc, offset); 117 qemu_fdt_add_subnode(fdt, ser); 118 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 119 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 120 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 121 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 122 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 123 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 124 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 125 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 126 127 if (defcon) { 128 /* 129 * "linux,stdout-path" and "stdout" properties are deprecated by linux 130 * kernel. New platforms should only use the "stdout-path" property. Set 131 * the new property and continue using older property to remain 132 * compatible with the existing firmware. 133 */ 134 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 135 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser); 136 } 137 g_free(ser); 138 } 139 140 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic) 141 { 142 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET; 143 int irq0 = MPC8XXX_GPIO_IRQ; 144 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0); 145 gchar *poweroff = g_strdup_printf("%s/power-off", soc); 146 int gpio_ph; 147 148 qemu_fdt_add_subnode(fdt, node); 149 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio"); 150 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000); 151 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2); 152 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 153 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2); 154 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0); 155 gpio_ph = qemu_fdt_alloc_phandle(fdt); 156 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph); 157 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph); 158 159 /* Power Off Pin */ 160 qemu_fdt_add_subnode(fdt, poweroff); 161 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff"); 162 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0); 163 164 g_free(node); 165 g_free(poweroff); 166 } 167 168 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias) 169 { 170 int offset = RTC_REGS_OFFSET; 171 172 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset); 173 qemu_fdt_add_subnode(fdt, rtc); 174 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338"); 175 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset); 176 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc); 177 178 g_free(rtc); 179 } 180 181 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic, 182 const char *alias) 183 { 184 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET; 185 int irq0 = MPC8544_I2C_IRQ; 186 187 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0); 188 qemu_fdt_add_subnode(fdt, i2c); 189 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c"); 190 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c"); 191 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14); 192 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0); 193 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2); 194 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic); 195 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c); 196 197 g_free(i2c); 198 } 199 200 201 typedef struct PlatformDevtreeData { 202 void *fdt; 203 const char *mpic; 204 int irq_start; 205 const char *node; 206 PlatformBusDevice *pbus; 207 } PlatformDevtreeData; 208 209 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data) 210 { 211 eTSEC *etsec = ETSEC_COMMON(sbdev); 212 PlatformBusDevice *pbus = data->pbus; 213 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0); 214 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0); 215 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1); 216 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2); 217 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0); 218 gchar *group = g_strdup_printf("%s/queue-group", node); 219 void *fdt = data->fdt; 220 221 assert((int64_t)mmio0 >= 0); 222 assert(irq0 >= 0); 223 assert(irq1 >= 0); 224 assert(irq2 >= 0); 225 226 qemu_fdt_add_subnode(fdt, node); 227 qemu_fdt_setprop_string(fdt, node, "device_type", "network"); 228 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2"); 229 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC"); 230 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6); 231 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0); 232 233 qemu_fdt_add_subnode(fdt, group); 234 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000); 235 qemu_fdt_setprop_cells(fdt, group, "interrupts", 236 data->irq_start + irq0, 0x2, 237 data->irq_start + irq1, 0x2, 238 data->irq_start + irq2, 0x2); 239 240 g_free(node); 241 g_free(group); 242 243 return 0; 244 } 245 246 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque) 247 { 248 PlatformDevtreeData *data = opaque; 249 bool matched = false; 250 251 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) { 252 create_devtree_etsec(sbdev, data); 253 matched = true; 254 } 255 256 if (!matched) { 257 error_report("Device %s is not supported by this machine yet.", 258 qdev_fw_name(DEVICE(sbdev))); 259 exit(1); 260 } 261 } 262 263 static void platform_bus_create_devtree(PPCE500MachineState *pms, 264 void *fdt, const char *mpic) 265 { 266 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 267 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base); 268 const char platcomp[] = "qemu,platform\0simple-bus"; 269 uint64_t addr = pmc->platform_bus_base; 270 uint64_t size = pmc->platform_bus_size; 271 int irq_start = pmc->platform_bus_first_irq; 272 273 /* Create a /platform node that we can put all devices into */ 274 275 qemu_fdt_add_subnode(fdt, node); 276 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp)); 277 278 /* Our platform bus region is less than 32bit big, so 1 cell is enough for 279 address and size */ 280 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1); 281 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1); 282 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size); 283 284 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic); 285 286 /* Create dt nodes for dynamic devices */ 287 PlatformDevtreeData data = { 288 .fdt = fdt, 289 .mpic = mpic, 290 .irq_start = irq_start, 291 .node = node, 292 .pbus = pms->pbus_dev, 293 }; 294 295 /* Loop through all dynamic sysbus devices and create nodes for them */ 296 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data); 297 298 g_free(node); 299 } 300 301 static int ppce500_load_device_tree(PPCE500MachineState *pms, 302 hwaddr addr, 303 hwaddr initrd_base, 304 hwaddr initrd_size, 305 hwaddr kernel_base, 306 hwaddr kernel_size, 307 bool dry_run) 308 { 309 MachineState *machine = MACHINE(pms); 310 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 311 CPUPPCState *env = first_cpu->env_ptr; 312 int ret = -1; 313 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) }; 314 int fdt_size; 315 void *fdt; 316 uint8_t hypercall[16]; 317 uint32_t clock_freq = 400000000; 318 uint32_t tb_freq = 400000000; 319 int i; 320 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 321 char *soc; 322 char *mpic; 323 uint32_t mpic_ph; 324 uint32_t msi_ph; 325 char *gutil; 326 char *pci; 327 char *msi; 328 uint32_t *pci_map = NULL; 329 int len; 330 uint32_t pci_ranges[14] = 331 { 332 0x2000000, 0x0, pmc->pci_mmio_bus_base, 333 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base, 334 0x0, 0x20000000, 335 336 0x1000000, 0x0, 0x0, 337 pmc->pci_pio_base >> 32, pmc->pci_pio_base, 338 0x0, 0x10000, 339 }; 340 QemuOpts *machine_opts = qemu_get_machine_opts(); 341 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 342 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 343 344 if (dtb_file) { 345 char *filename; 346 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 347 if (!filename) { 348 goto out; 349 } 350 351 fdt = load_device_tree(filename, &fdt_size); 352 g_free(filename); 353 if (!fdt) { 354 goto out; 355 } 356 goto done; 357 } 358 359 fdt = create_device_tree(&fdt_size); 360 if (fdt == NULL) { 361 goto out; 362 } 363 364 /* Manipulate device tree in memory. */ 365 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 366 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 367 368 qemu_fdt_add_subnode(fdt, "/memory"); 369 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 370 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 371 sizeof(mem_reg_property)); 372 373 qemu_fdt_add_subnode(fdt, "/chosen"); 374 if (initrd_size) { 375 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 376 initrd_base); 377 if (ret < 0) { 378 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 379 } 380 381 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 382 (initrd_base + initrd_size)); 383 if (ret < 0) { 384 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 385 } 386 387 } 388 389 if (kernel_base != -1ULL) { 390 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel", 391 kernel_base >> 32, kernel_base, 392 kernel_size >> 32, kernel_size); 393 } 394 395 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 396 machine->kernel_cmdline); 397 if (ret < 0) 398 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 399 400 if (kvm_enabled()) { 401 /* Read out host's frequencies */ 402 clock_freq = kvmppc_get_clockfreq(); 403 tb_freq = kvmppc_get_tbfreq(); 404 405 /* indicate KVM hypercall interface */ 406 qemu_fdt_add_subnode(fdt, "/hypervisor"); 407 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 408 "linux,kvm"); 409 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 410 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 411 hypercall, sizeof(hypercall)); 412 /* if KVM supports the idle hcall, set property indicating this */ 413 if (kvmppc_get_hasidle(env)) { 414 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 415 } 416 } 417 418 /* Create CPU nodes */ 419 qemu_fdt_add_subnode(fdt, "/cpus"); 420 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 421 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 422 423 /* We need to generate the cpu nodes in reverse order, so Linux can pick 424 the first node as boot node and be happy */ 425 for (i = smp_cpus - 1; i >= 0; i--) { 426 CPUState *cpu; 427 char *cpu_name; 428 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20); 429 430 cpu = qemu_get_cpu(i); 431 if (cpu == NULL) { 432 continue; 433 } 434 env = cpu->env_ptr; 435 436 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i); 437 qemu_fdt_add_subnode(fdt, cpu_name); 438 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 439 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 440 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 441 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i); 442 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 443 env->dcache_line_size); 444 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 445 env->icache_line_size); 446 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 447 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 448 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 449 if (cpu->cpu_index) { 450 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 451 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 452 "spin-table"); 453 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 454 cpu_release_addr); 455 } else { 456 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 457 } 458 g_free(cpu_name); 459 } 460 461 qemu_fdt_add_subnode(fdt, "/aliases"); 462 /* XXX These should go into their respective devices' code */ 463 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base); 464 qemu_fdt_add_subnode(fdt, soc); 465 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 466 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 467 sizeof(compatible_sb)); 468 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 469 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 470 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 471 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base, 472 MPC8544_CCSRBAR_SIZE); 473 /* XXX should contain a reasonable value */ 474 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 475 476 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 477 qemu_fdt_add_subnode(fdt, mpic); 478 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 479 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 480 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 481 0x40000); 482 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 483 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 484 mpic_ph = qemu_fdt_alloc_phandle(fdt); 485 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 486 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 487 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 488 489 /* 490 * We have to generate ser1 first, because Linux takes the first 491 * device it finds in the dt as serial output device. And we generate 492 * devices in reverse order to the dt. 493 */ 494 if (serial_hd(1)) { 495 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 496 soc, mpic, "serial1", 1, false); 497 } 498 499 if (serial_hd(0)) { 500 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 501 soc, mpic, "serial0", 0, true); 502 } 503 504 /* i2c */ 505 dt_i2c_create(fdt, soc, mpic, "i2c"); 506 507 dt_rtc_create(fdt, "i2c", "rtc"); 508 509 510 gutil = g_strdup_printf("%s/global-utilities@%llx", soc, 511 MPC8544_UTIL_OFFSET); 512 qemu_fdt_add_subnode(fdt, gutil); 513 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 514 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 515 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 516 g_free(gutil); 517 518 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 519 qemu_fdt_add_subnode(fdt, msi); 520 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 521 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 522 msi_ph = qemu_fdt_alloc_phandle(fdt); 523 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 524 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 525 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 526 0xe0, 0x0, 527 0xe1, 0x0, 528 0xe2, 0x0, 529 0xe3, 0x0, 530 0xe4, 0x0, 531 0xe5, 0x0, 532 0xe6, 0x0, 533 0xe7, 0x0); 534 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 535 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 536 g_free(msi); 537 538 pci = g_strdup_printf("/pci@%llx", 539 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET); 540 qemu_fdt_add_subnode(fdt, pci); 541 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 542 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 543 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 544 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 545 0x0, 0x7); 546 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 547 pmc->pci_first_slot, pmc->pci_nr_slots, 548 &len); 549 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 550 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 551 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 552 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 553 for (i = 0; i < 14; i++) { 554 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 555 } 556 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 557 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 558 qemu_fdt_setprop_cells(fdt, pci, "reg", 559 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32, 560 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET), 561 0, 0x1000); 562 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 563 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 564 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 565 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 566 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 567 g_free(pci); 568 569 if (pmc->has_mpc8xxx_gpio) { 570 create_dt_mpc8xxx_gpio(fdt, soc, mpic); 571 } 572 g_free(soc); 573 574 if (pms->pbus_dev) { 575 platform_bus_create_devtree(pms, fdt, mpic); 576 } 577 g_free(mpic); 578 579 pmc->fixup_devtree(fdt); 580 581 if (toplevel_compat) { 582 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 583 strlen(toplevel_compat) + 1); 584 } 585 586 done: 587 if (!dry_run) { 588 qemu_fdt_dumpdtb(fdt, fdt_size); 589 cpu_physical_memory_write(addr, fdt, fdt_size); 590 } 591 ret = fdt_size; 592 593 out: 594 g_free(pci_map); 595 596 return ret; 597 } 598 599 typedef struct DeviceTreeParams { 600 PPCE500MachineState *machine; 601 hwaddr addr; 602 hwaddr initrd_base; 603 hwaddr initrd_size; 604 hwaddr kernel_base; 605 hwaddr kernel_size; 606 Notifier notifier; 607 } DeviceTreeParams; 608 609 static void ppce500_reset_device_tree(void *opaque) 610 { 611 DeviceTreeParams *p = opaque; 612 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base, 613 p->initrd_size, p->kernel_base, p->kernel_size, 614 false); 615 } 616 617 static void ppce500_init_notify(Notifier *notifier, void *data) 618 { 619 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier); 620 ppce500_reset_device_tree(p); 621 } 622 623 static int ppce500_prep_device_tree(PPCE500MachineState *machine, 624 hwaddr addr, 625 hwaddr initrd_base, 626 hwaddr initrd_size, 627 hwaddr kernel_base, 628 hwaddr kernel_size) 629 { 630 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 631 p->machine = machine; 632 p->addr = addr; 633 p->initrd_base = initrd_base; 634 p->initrd_size = initrd_size; 635 p->kernel_base = kernel_base; 636 p->kernel_size = kernel_size; 637 638 qemu_register_reset(ppce500_reset_device_tree, p); 639 p->notifier.notify = ppce500_init_notify; 640 qemu_add_machine_init_done_notifier(&p->notifier); 641 642 /* Issue the device tree loader once, so that we get the size of the blob */ 643 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size, 644 kernel_base, kernel_size, true); 645 } 646 647 /* Create -kernel TLB entries for BookE. */ 648 hwaddr booke206_page_size_to_tlb(uint64_t size) 649 { 650 return 63 - clz64(size / KiB); 651 } 652 653 static int booke206_initial_map_tsize(CPUPPCState *env) 654 { 655 struct boot_info *bi = env->load_info; 656 hwaddr dt_end; 657 int ps; 658 659 /* Our initial TLB entry needs to cover everything from 0 to 660 the device tree top */ 661 dt_end = bi->dt_base + bi->dt_size; 662 ps = booke206_page_size_to_tlb(dt_end) + 1; 663 if (ps & 1) { 664 /* e500v2 can only do even TLB size bits */ 665 ps++; 666 } 667 return ps; 668 } 669 670 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 671 { 672 int tsize; 673 674 tsize = booke206_initial_map_tsize(env); 675 return (1ULL << 10 << tsize); 676 } 677 678 static void mmubooke_create_initial_mapping(CPUPPCState *env) 679 { 680 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 681 hwaddr size; 682 int ps; 683 684 ps = booke206_initial_map_tsize(env); 685 size = (ps << MAS1_TSIZE_SHIFT); 686 tlb->mas1 = MAS1_VALID | size; 687 tlb->mas2 = 0; 688 tlb->mas7_3 = 0; 689 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 690 691 env->tlb_dirty = true; 692 } 693 694 static void ppce500_cpu_reset_sec(void *opaque) 695 { 696 PowerPCCPU *cpu = opaque; 697 CPUState *cs = CPU(cpu); 698 699 cpu_reset(cs); 700 701 /* Secondary CPU starts in halted state for now. Needs to change when 702 implementing non-kernel boot. */ 703 cs->halted = 1; 704 cs->exception_index = EXCP_HLT; 705 } 706 707 static void ppce500_cpu_reset(void *opaque) 708 { 709 PowerPCCPU *cpu = opaque; 710 CPUState *cs = CPU(cpu); 711 CPUPPCState *env = &cpu->env; 712 struct boot_info *bi = env->load_info; 713 714 cpu_reset(cs); 715 716 /* Set initial guest state. */ 717 cs->halted = 0; 718 env->gpr[1] = (16 * MiB) - 8; 719 env->gpr[3] = bi->dt_base; 720 env->gpr[4] = 0; 721 env->gpr[5] = 0; 722 env->gpr[6] = EPAPR_MAGIC; 723 env->gpr[7] = mmubooke_initial_mapsize(env); 724 env->gpr[8] = 0; 725 env->gpr[9] = 0; 726 env->nip = bi->entry; 727 mmubooke_create_initial_mapping(env); 728 } 729 730 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms, 731 IrqLines *irqs) 732 { 733 DeviceState *dev; 734 SysBusDevice *s; 735 int i, j, k; 736 MachineState *machine = MACHINE(pms); 737 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 738 739 dev = qdev_create(NULL, TYPE_OPENPIC); 740 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev), 741 &error_fatal); 742 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 743 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 744 745 qdev_init_nofail(dev); 746 s = SYS_BUS_DEVICE(dev); 747 748 k = 0; 749 for (i = 0; i < smp_cpus; i++) { 750 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 751 sysbus_connect_irq(s, k++, irqs[i].irq[j]); 752 } 753 } 754 755 return dev; 756 } 757 758 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc, 759 IrqLines *irqs, Error **errp) 760 { 761 Error *err = NULL; 762 DeviceState *dev; 763 CPUState *cs; 764 765 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 766 qdev_prop_set_uint32(dev, "model", pmc->mpic_version); 767 768 object_property_set_bool(OBJECT(dev), true, "realized", &err); 769 if (err) { 770 error_propagate(errp, err); 771 object_unparent(OBJECT(dev)); 772 return NULL; 773 } 774 775 CPU_FOREACH(cs) { 776 if (kvm_openpic_connect_vcpu(dev, cs)) { 777 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 778 __func__); 779 abort(); 780 } 781 } 782 783 return dev; 784 } 785 786 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms, 787 MemoryRegion *ccsr, 788 IrqLines *irqs) 789 { 790 MachineState *machine = MACHINE(pms); 791 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms); 792 DeviceState *dev = NULL; 793 SysBusDevice *s; 794 795 if (kvm_enabled()) { 796 Error *err = NULL; 797 798 if (machine_kernel_irqchip_allowed(machine)) { 799 dev = ppce500_init_mpic_kvm(pmc, irqs, &err); 800 } 801 if (machine_kernel_irqchip_required(machine) && !dev) { 802 error_reportf_err(err, 803 "kernel_irqchip requested but unavailable: "); 804 exit(1); 805 } 806 } 807 808 if (!dev) { 809 dev = ppce500_init_mpic_qemu(pms, irqs); 810 } 811 812 s = SYS_BUS_DEVICE(dev); 813 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 814 s->mmio[0].memory); 815 816 return dev; 817 } 818 819 static void ppce500_power_off(void *opaque, int line, int on) 820 { 821 if (on) { 822 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 823 } 824 } 825 826 void ppce500_init(MachineState *machine) 827 { 828 MemoryRegion *address_space_mem = get_system_memory(); 829 MemoryRegion *ram = g_new(MemoryRegion, 1); 830 PPCE500MachineState *pms = PPCE500_MACHINE(machine); 831 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); 832 PCIBus *pci_bus; 833 CPUPPCState *env = NULL; 834 uint64_t loadaddr; 835 hwaddr kernel_base = -1LL; 836 int kernel_size = 0; 837 hwaddr dt_base = 0; 838 hwaddr initrd_base = 0; 839 int initrd_size = 0; 840 hwaddr cur_base = 0; 841 char *filename; 842 const char *payload_name; 843 bool kernel_as_payload; 844 hwaddr bios_entry = 0; 845 target_long payload_size; 846 struct boot_info *boot_info; 847 int dt_size; 848 int i; 849 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and 850 * 4 respectively */ 851 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4}; 852 IrqLines *irqs; 853 DeviceState *dev, *mpicdev; 854 CPUPPCState *firstenv = NULL; 855 MemoryRegion *ccsr_addr_space; 856 SysBusDevice *s; 857 PPCE500CCSRState *ccsr; 858 I2CBus *i2c; 859 860 irqs = g_new0(IrqLines, smp_cpus); 861 for (i = 0; i < smp_cpus; i++) { 862 PowerPCCPU *cpu; 863 CPUState *cs; 864 qemu_irq *input; 865 866 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 867 env = &cpu->env; 868 cs = CPU(cpu); 869 870 if (env->mmu_model != POWERPC_MMU_BOOKE206) { 871 error_report("MMU model %i not supported by this machine", 872 env->mmu_model); 873 exit(1); 874 } 875 876 if (!firstenv) { 877 firstenv = env; 878 } 879 880 input = (qemu_irq *)env->irq_inputs; 881 irqs[i].irq[OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 882 irqs[i].irq[OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 883 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; 884 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0; 885 886 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 887 888 /* Register reset handler */ 889 if (!i) { 890 /* Primary CPU */ 891 struct boot_info *boot_info; 892 boot_info = g_malloc0(sizeof(struct boot_info)); 893 qemu_register_reset(ppce500_cpu_reset, cpu); 894 env->load_info = boot_info; 895 } else { 896 /* Secondary CPUs */ 897 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 898 } 899 } 900 901 env = firstenv; 902 903 /* Fixup Memory size on a alignment boundary */ 904 ram_size &= ~(RAM_SIZES_ALIGN - 1); 905 machine->ram_size = ram_size; 906 907 /* Register Memory */ 908 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); 909 memory_region_add_subregion(address_space_mem, 0, ram); 910 911 dev = qdev_create(NULL, "e500-ccsr"); 912 object_property_add_child(qdev_get_machine(), "e500-ccsr", 913 OBJECT(dev), NULL); 914 qdev_init_nofail(dev); 915 ccsr = CCSR(dev); 916 ccsr_addr_space = &ccsr->ccsr_space; 917 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base, 918 ccsr_addr_space); 919 920 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs); 921 922 /* Serial */ 923 if (serial_hd(0)) { 924 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 925 0, qdev_get_gpio_in(mpicdev, 42), 399193, 926 serial_hd(0), DEVICE_BIG_ENDIAN); 927 } 928 929 if (serial_hd(1)) { 930 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 931 0, qdev_get_gpio_in(mpicdev, 42), 399193, 932 serial_hd(1), DEVICE_BIG_ENDIAN); 933 } 934 /* I2C */ 935 dev = qdev_create(NULL, "mpc-i2c"); 936 s = SYS_BUS_DEVICE(dev); 937 qdev_init_nofail(dev); 938 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ)); 939 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET, 940 sysbus_mmio_get_region(s, 0)); 941 i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c"); 942 i2c_create_slave(i2c, "ds1338", RTC_REGS_OFFSET); 943 944 945 /* General Utility device */ 946 dev = qdev_create(NULL, "mpc8544-guts"); 947 qdev_init_nofail(dev); 948 s = SYS_BUS_DEVICE(dev); 949 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 950 sysbus_mmio_get_region(s, 0)); 951 952 /* PCI */ 953 dev = qdev_create(NULL, "e500-pcihost"); 954 object_property_add_child(qdev_get_machine(), "pci-host", OBJECT(dev), 955 &error_abort); 956 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot); 957 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]); 958 qdev_init_nofail(dev); 959 s = SYS_BUS_DEVICE(dev); 960 for (i = 0; i < PCI_NUM_PINS; i++) { 961 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i])); 962 } 963 964 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 965 sysbus_mmio_get_region(s, 0)); 966 967 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 968 if (!pci_bus) 969 printf("couldn't create PCI controller!\n"); 970 971 if (pci_bus) { 972 /* Register network interfaces. */ 973 for (i = 0; i < nb_nics; i++) { 974 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio-net-pci", NULL); 975 } 976 } 977 978 /* Register spinning region */ 979 sysbus_create_simple("e500-spin", pmc->spin_base, NULL); 980 981 if (pmc->has_mpc8xxx_gpio) { 982 qemu_irq poweroff_irq; 983 984 dev = qdev_create(NULL, "mpc8xxx_gpio"); 985 s = SYS_BUS_DEVICE(dev); 986 qdev_init_nofail(dev); 987 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ)); 988 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET, 989 sysbus_mmio_get_region(s, 0)); 990 991 /* Power Off GPIO at Pin 0 */ 992 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0); 993 qdev_connect_gpio_out(dev, 0, poweroff_irq); 994 } 995 996 /* Platform Bus Device */ 997 if (pmc->has_platform_bus) { 998 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); 999 dev->id = TYPE_PLATFORM_BUS_DEVICE; 1000 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs); 1001 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size); 1002 qdev_init_nofail(dev); 1003 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev); 1004 1005 s = SYS_BUS_DEVICE(pms->pbus_dev); 1006 for (i = 0; i < pmc->platform_bus_num_irqs; i++) { 1007 int irqn = pmc->platform_bus_first_irq + i; 1008 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn)); 1009 } 1010 1011 memory_region_add_subregion(address_space_mem, 1012 pmc->platform_bus_base, 1013 sysbus_mmio_get_region(s, 0)); 1014 } 1015 1016 /* 1017 * Smart firmware defaults ahead! 1018 * 1019 * We follow the following table to select which payload we execute. 1020 * 1021 * -kernel | -bios | payload 1022 * ---------+-------+--------- 1023 * N | Y | u-boot 1024 * N | N | u-boot 1025 * Y | Y | u-boot 1026 * Y | N | kernel 1027 * 1028 * This ensures backwards compatibility with how we used to expose 1029 * -kernel to users but allows them to run through u-boot as well. 1030 */ 1031 kernel_as_payload = false; 1032 if (bios_name == NULL) { 1033 if (machine->kernel_filename) { 1034 payload_name = machine->kernel_filename; 1035 kernel_as_payload = true; 1036 } else { 1037 payload_name = "u-boot.e500"; 1038 } 1039 } else { 1040 payload_name = bios_name; 1041 } 1042 1043 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name); 1044 1045 payload_size = load_elf(filename, NULL, NULL, NULL, 1046 &bios_entry, &loadaddr, NULL, 1047 1, PPC_ELF_MACHINE, 0, 0); 1048 if (payload_size < 0) { 1049 /* 1050 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an 1051 * ePAPR compliant kernel 1052 */ 1053 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID; 1054 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL, 1055 NULL, NULL); 1056 if (payload_size < 0) { 1057 error_report("could not load firmware '%s'", filename); 1058 exit(1); 1059 } 1060 } 1061 1062 g_free(filename); 1063 1064 if (kernel_as_payload) { 1065 kernel_base = loadaddr; 1066 kernel_size = payload_size; 1067 } 1068 1069 cur_base = loadaddr + payload_size; 1070 if (cur_base < 32 * MiB) { 1071 /* u-boot occupies memory up to 32MB, so load blobs above */ 1072 cur_base = 32 * MiB; 1073 } 1074 1075 /* Load bare kernel only if no bios/u-boot has been provided */ 1076 if (machine->kernel_filename && !kernel_as_payload) { 1077 kernel_base = cur_base; 1078 kernel_size = load_image_targphys(machine->kernel_filename, 1079 cur_base, 1080 ram_size - cur_base); 1081 if (kernel_size < 0) { 1082 error_report("could not load kernel '%s'", 1083 machine->kernel_filename); 1084 exit(1); 1085 } 1086 1087 cur_base += kernel_size; 1088 } 1089 1090 /* Load initrd. */ 1091 if (machine->initrd_filename) { 1092 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 1093 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, 1094 ram_size - initrd_base); 1095 1096 if (initrd_size < 0) { 1097 error_report("could not load initial ram disk '%s'", 1098 machine->initrd_filename); 1099 exit(1); 1100 } 1101 1102 cur_base = initrd_base + initrd_size; 1103 } 1104 1105 /* 1106 * Reserve space for dtb behind the kernel image because Linux has a bug 1107 * where it can only handle the dtb if it's within the first 64MB of where 1108 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD 1109 * ensures enough space between kernel and initrd. 1110 */ 1111 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 1112 if (dt_base + DTB_MAX_SIZE > ram_size) { 1113 error_report("not enough memory for device tree"); 1114 exit(1); 1115 } 1116 1117 dt_size = ppce500_prep_device_tree(pms, dt_base, 1118 initrd_base, initrd_size, 1119 kernel_base, kernel_size); 1120 if (dt_size < 0) { 1121 error_report("couldn't load device tree"); 1122 exit(1); 1123 } 1124 assert(dt_size < DTB_MAX_SIZE); 1125 1126 boot_info = env->load_info; 1127 boot_info->entry = bios_entry; 1128 boot_info->dt_base = dt_base; 1129 boot_info->dt_size = dt_size; 1130 } 1131 1132 static void e500_ccsr_initfn(Object *obj) 1133 { 1134 PPCE500CCSRState *ccsr = CCSR(obj); 1135 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr", 1136 MPC8544_CCSRBAR_SIZE); 1137 } 1138 1139 static const TypeInfo e500_ccsr_info = { 1140 .name = TYPE_CCSR, 1141 .parent = TYPE_SYS_BUS_DEVICE, 1142 .instance_size = sizeof(PPCE500CCSRState), 1143 .instance_init = e500_ccsr_initfn, 1144 }; 1145 1146 static const TypeInfo ppce500_info = { 1147 .name = TYPE_PPCE500_MACHINE, 1148 .parent = TYPE_MACHINE, 1149 .abstract = true, 1150 .instance_size = sizeof(PPCE500MachineState), 1151 .class_size = sizeof(PPCE500MachineClass), 1152 }; 1153 1154 static void e500_register_types(void) 1155 { 1156 type_register_static(&e500_ccsr_info); 1157 type_register_static(&ppce500_info); 1158 } 1159 1160 type_init(e500_register_types) 1161