1 /* 2 * QEMU PowerPC e500-based platforms 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc440_bamboo.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "config.h" 18 #include "qemu-common.h" 19 #include "e500.h" 20 #include "e500-ccsr.h" 21 #include "net/net.h" 22 #include "qemu/config-file.h" 23 #include "hw/hw.h" 24 #include "hw/char/serial.h" 25 #include "hw/pci/pci.h" 26 #include "hw/boards.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/kvm.h" 29 #include "kvm_ppc.h" 30 #include "sysemu/device_tree.h" 31 #include "hw/ppc/openpic.h" 32 #include "hw/ppc/ppc.h" 33 #include "hw/loader.h" 34 #include "elf.h" 35 #include "hw/sysbus.h" 36 #include "exec/address-spaces.h" 37 #include "qemu/host-utils.h" 38 #include "hw/pci-host/ppce500.h" 39 40 #define EPAPR_MAGIC (0x45504150) 41 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb" 42 #define UIMAGE_LOAD_BASE 0 43 #define DTC_LOAD_PAD 0x1800000 44 #define DTC_PAD_MASK 0xFFFFF 45 #define DTB_MAX_SIZE (8 * 1024 * 1024) 46 #define INITRD_LOAD_PAD 0x2000000 47 #define INITRD_PAD_MASK 0xFFFFFF 48 49 #define RAM_SIZES_ALIGN (64UL << 20) 50 51 /* TODO: parameterize */ 52 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL 53 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL 54 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL 55 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL 56 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL 57 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL 58 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL 59 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \ 60 MPC8544_PCI_REGS_OFFSET) 61 #define MPC8544_PCI_REGS_SIZE 0x1000ULL 62 #define MPC8544_PCI_IO 0xE1000000ULL 63 #define MPC8544_UTIL_OFFSET 0xe0000ULL 64 #define MPC8544_SPIN_BASE 0xEF000000ULL 65 66 struct boot_info 67 { 68 uint32_t dt_base; 69 uint32_t dt_size; 70 uint32_t entry; 71 }; 72 73 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, 74 int nr_slots, int *len) 75 { 76 int i = 0; 77 int slot; 78 int pci_irq; 79 int host_irq; 80 int last_slot = first_slot + nr_slots; 81 uint32_t *pci_map; 82 83 *len = nr_slots * 4 * 7 * sizeof(uint32_t); 84 pci_map = g_malloc(*len); 85 86 for (slot = first_slot; slot < last_slot; slot++) { 87 for (pci_irq = 0; pci_irq < 4; pci_irq++) { 88 pci_map[i++] = cpu_to_be32(slot << 11); 89 pci_map[i++] = cpu_to_be32(0x0); 90 pci_map[i++] = cpu_to_be32(0x0); 91 pci_map[i++] = cpu_to_be32(pci_irq + 1); 92 pci_map[i++] = cpu_to_be32(mpic); 93 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq); 94 pci_map[i++] = cpu_to_be32(host_irq + 1); 95 pci_map[i++] = cpu_to_be32(0x1); 96 } 97 } 98 99 assert((i * sizeof(uint32_t)) == *len); 100 101 return pci_map; 102 } 103 104 static void dt_serial_create(void *fdt, unsigned long long offset, 105 const char *soc, const char *mpic, 106 const char *alias, int idx, bool defcon) 107 { 108 char ser[128]; 109 110 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset); 111 qemu_fdt_add_subnode(fdt, ser); 112 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial"); 113 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550"); 114 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100); 115 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx); 116 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0); 117 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2); 118 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic); 119 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser); 120 121 if (defcon) { 122 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser); 123 } 124 } 125 126 static int ppce500_load_device_tree(QEMUMachineInitArgs *args, 127 PPCE500Params *params, 128 hwaddr addr, 129 hwaddr initrd_base, 130 hwaddr initrd_size, 131 bool dry_run) 132 { 133 CPUPPCState *env = first_cpu->env_ptr; 134 int ret = -1; 135 uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) }; 136 int fdt_size; 137 void *fdt; 138 uint8_t hypercall[16]; 139 uint32_t clock_freq = 400000000; 140 uint32_t tb_freq = 400000000; 141 int i; 142 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus"; 143 char soc[128]; 144 char mpic[128]; 145 uint32_t mpic_ph; 146 uint32_t msi_ph; 147 char gutil[128]; 148 char pci[128]; 149 char msi[128]; 150 uint32_t *pci_map = NULL; 151 int len; 152 uint32_t pci_ranges[14] = 153 { 154 0x2000000, 0x0, 0xc0000000, 155 0x0, 0xc0000000, 156 0x0, 0x20000000, 157 158 0x1000000, 0x0, 0x0, 159 0x0, 0xe1000000, 160 0x0, 0x10000, 161 }; 162 QemuOpts *machine_opts = qemu_get_machine_opts(); 163 const char *dtb_file = qemu_opt_get(machine_opts, "dtb"); 164 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible"); 165 166 if (dtb_file) { 167 char *filename; 168 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file); 169 if (!filename) { 170 goto out; 171 } 172 173 fdt = load_device_tree(filename, &fdt_size); 174 if (!fdt) { 175 goto out; 176 } 177 goto done; 178 } 179 180 fdt = create_device_tree(&fdt_size); 181 if (fdt == NULL) { 182 goto out; 183 } 184 185 /* Manipulate device tree in memory. */ 186 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2); 187 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2); 188 189 qemu_fdt_add_subnode(fdt, "/memory"); 190 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory"); 191 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property, 192 sizeof(mem_reg_property)); 193 194 qemu_fdt_add_subnode(fdt, "/chosen"); 195 if (initrd_size) { 196 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", 197 initrd_base); 198 if (ret < 0) { 199 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); 200 } 201 202 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", 203 (initrd_base + initrd_size)); 204 if (ret < 0) { 205 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); 206 } 207 } 208 209 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", 210 args->kernel_cmdline); 211 if (ret < 0) 212 fprintf(stderr, "couldn't set /chosen/bootargs\n"); 213 214 if (kvm_enabled()) { 215 /* Read out host's frequencies */ 216 clock_freq = kvmppc_get_clockfreq(); 217 tb_freq = kvmppc_get_tbfreq(); 218 219 /* indicate KVM hypercall interface */ 220 qemu_fdt_add_subnode(fdt, "/hypervisor"); 221 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible", 222 "linux,kvm"); 223 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall)); 224 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions", 225 hypercall, sizeof(hypercall)); 226 /* if KVM supports the idle hcall, set property indicating this */ 227 if (kvmppc_get_hasidle(env)) { 228 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0); 229 } 230 } 231 232 /* Create CPU nodes */ 233 qemu_fdt_add_subnode(fdt, "/cpus"); 234 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1); 235 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0); 236 237 /* We need to generate the cpu nodes in reverse order, so Linux can pick 238 the first node as boot node and be happy */ 239 for (i = smp_cpus - 1; i >= 0; i--) { 240 CPUState *cpu; 241 PowerPCCPU *pcpu; 242 char cpu_name[128]; 243 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20); 244 245 cpu = qemu_get_cpu(i); 246 if (cpu == NULL) { 247 continue; 248 } 249 env = cpu->env_ptr; 250 pcpu = POWERPC_CPU(cpu); 251 252 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", 253 ppc_get_vcpu_dt_id(pcpu)); 254 qemu_fdt_add_subnode(fdt, cpu_name); 255 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq); 256 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq); 257 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 258 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 259 ppc_get_vcpu_dt_id(pcpu)); 260 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size", 261 env->dcache_line_size); 262 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size", 263 env->icache_line_size); 264 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000); 265 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000); 266 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0); 267 if (cpu->cpu_index) { 268 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled"); 269 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method", 270 "spin-table"); 271 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr", 272 cpu_release_addr); 273 } else { 274 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 275 } 276 } 277 278 qemu_fdt_add_subnode(fdt, "/aliases"); 279 /* XXX These should go into their respective devices' code */ 280 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE); 281 qemu_fdt_add_subnode(fdt, soc); 282 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc"); 283 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb, 284 sizeof(compatible_sb)); 285 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1); 286 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1); 287 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0, 288 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE, 289 MPC8544_CCSRBAR_SIZE); 290 /* XXX should contain a reasonable value */ 291 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0); 292 293 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET); 294 qemu_fdt_add_subnode(fdt, mpic); 295 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic"); 296 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic"); 297 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET, 298 0x40000); 299 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0); 300 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2); 301 mpic_ph = qemu_fdt_alloc_phandle(fdt); 302 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph); 303 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph); 304 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0); 305 306 /* 307 * We have to generate ser1 first, because Linux takes the first 308 * device it finds in the dt as serial output device. And we generate 309 * devices in reverse order to the dt. 310 */ 311 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET, 312 soc, mpic, "serial1", 1, false); 313 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET, 314 soc, mpic, "serial0", 0, true); 315 316 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc, 317 MPC8544_UTIL_OFFSET); 318 qemu_fdt_add_subnode(fdt, gutil); 319 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts"); 320 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000); 321 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0); 322 323 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET); 324 qemu_fdt_add_subnode(fdt, msi); 325 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi"); 326 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200); 327 msi_ph = qemu_fdt_alloc_phandle(fdt); 328 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100); 329 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic); 330 qemu_fdt_setprop_cells(fdt, msi, "interrupts", 331 0xe0, 0x0, 332 0xe1, 0x0, 333 0xe2, 0x0, 334 0xe3, 0x0, 335 0xe4, 0x0, 336 0xe5, 0x0, 337 0xe6, 0x0, 338 0xe7, 0x0); 339 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph); 340 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph); 341 342 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE); 343 qemu_fdt_add_subnode(fdt, pci); 344 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0); 345 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci"); 346 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci"); 347 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0, 348 0x0, 0x7); 349 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic), 350 params->pci_first_slot, params->pci_nr_slots, 351 &len); 352 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len); 353 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic); 354 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2); 355 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255); 356 for (i = 0; i < 14; i++) { 357 pci_ranges[i] = cpu_to_be32(pci_ranges[i]); 358 } 359 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph); 360 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges)); 361 qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32, 362 MPC8544_PCI_REGS_BASE, 0, 0x1000); 363 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666); 364 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1); 365 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2); 366 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3); 367 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci); 368 369 params->fixup_devtree(params, fdt); 370 371 if (toplevel_compat) { 372 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat, 373 strlen(toplevel_compat) + 1); 374 } 375 376 done: 377 if (!dry_run) { 378 qemu_fdt_dumpdtb(fdt, fdt_size); 379 cpu_physical_memory_write(addr, fdt, fdt_size); 380 } 381 ret = fdt_size; 382 383 out: 384 g_free(pci_map); 385 386 return ret; 387 } 388 389 typedef struct DeviceTreeParams { 390 QEMUMachineInitArgs args; 391 PPCE500Params params; 392 hwaddr addr; 393 hwaddr initrd_base; 394 hwaddr initrd_size; 395 } DeviceTreeParams; 396 397 static void ppce500_reset_device_tree(void *opaque) 398 { 399 DeviceTreeParams *p = opaque; 400 ppce500_load_device_tree(&p->args, &p->params, p->addr, p->initrd_base, 401 p->initrd_size, false); 402 } 403 404 static int ppce500_prep_device_tree(QEMUMachineInitArgs *args, 405 PPCE500Params *params, 406 hwaddr addr, 407 hwaddr initrd_base, 408 hwaddr initrd_size) 409 { 410 DeviceTreeParams *p = g_new(DeviceTreeParams, 1); 411 p->args = *args; 412 p->params = *params; 413 p->addr = addr; 414 p->initrd_base = initrd_base; 415 p->initrd_size = initrd_size; 416 417 qemu_register_reset(ppce500_reset_device_tree, p); 418 419 /* Issue the device tree loader once, so that we get the size of the blob */ 420 return ppce500_load_device_tree(args, params, addr, initrd_base, 421 initrd_size, true); 422 } 423 424 /* Create -kernel TLB entries for BookE. */ 425 static inline hwaddr booke206_page_size_to_tlb(uint64_t size) 426 { 427 return 63 - clz64(size >> 10); 428 } 429 430 static int booke206_initial_map_tsize(CPUPPCState *env) 431 { 432 struct boot_info *bi = env->load_info; 433 hwaddr dt_end; 434 int ps; 435 436 /* Our initial TLB entry needs to cover everything from 0 to 437 the device tree top */ 438 dt_end = bi->dt_base + bi->dt_size; 439 ps = booke206_page_size_to_tlb(dt_end) + 1; 440 if (ps & 1) { 441 /* e500v2 can only do even TLB size bits */ 442 ps++; 443 } 444 return ps; 445 } 446 447 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env) 448 { 449 int tsize; 450 451 tsize = booke206_initial_map_tsize(env); 452 return (1ULL << 10 << tsize); 453 } 454 455 static void mmubooke_create_initial_mapping(CPUPPCState *env) 456 { 457 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0); 458 hwaddr size; 459 int ps; 460 461 ps = booke206_initial_map_tsize(env); 462 size = (ps << MAS1_TSIZE_SHIFT); 463 tlb->mas1 = MAS1_VALID | size; 464 tlb->mas2 = 0; 465 tlb->mas7_3 = 0; 466 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 467 468 env->tlb_dirty = true; 469 } 470 471 static void ppce500_cpu_reset_sec(void *opaque) 472 { 473 PowerPCCPU *cpu = opaque; 474 CPUState *cs = CPU(cpu); 475 CPUPPCState *env = &cpu->env; 476 477 cpu_reset(cs); 478 479 /* Secondary CPU starts in halted state for now. Needs to change when 480 implementing non-kernel boot. */ 481 cs->halted = 1; 482 env->exception_index = EXCP_HLT; 483 } 484 485 static void ppce500_cpu_reset(void *opaque) 486 { 487 PowerPCCPU *cpu = opaque; 488 CPUState *cs = CPU(cpu); 489 CPUPPCState *env = &cpu->env; 490 struct boot_info *bi = env->load_info; 491 492 cpu_reset(cs); 493 494 /* Set initial guest state. */ 495 cs->halted = 0; 496 env->gpr[1] = (16<<20) - 8; 497 env->gpr[3] = bi->dt_base; 498 env->gpr[4] = 0; 499 env->gpr[5] = 0; 500 env->gpr[6] = EPAPR_MAGIC; 501 env->gpr[7] = mmubooke_initial_mapsize(env); 502 env->gpr[8] = 0; 503 env->gpr[9] = 0; 504 env->nip = bi->entry; 505 mmubooke_create_initial_mapping(env); 506 } 507 508 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params, 509 qemu_irq **irqs) 510 { 511 DeviceState *dev; 512 SysBusDevice *s; 513 int i, j, k; 514 515 dev = qdev_create(NULL, TYPE_OPENPIC); 516 qdev_prop_set_uint32(dev, "model", params->mpic_version); 517 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus); 518 519 qdev_init_nofail(dev); 520 s = SYS_BUS_DEVICE(dev); 521 522 k = 0; 523 for (i = 0; i < smp_cpus; i++) { 524 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) { 525 sysbus_connect_irq(s, k++, irqs[i][j]); 526 } 527 } 528 529 return dev; 530 } 531 532 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params, 533 qemu_irq **irqs) 534 { 535 DeviceState *dev; 536 CPUState *cs; 537 int r; 538 539 dev = qdev_create(NULL, TYPE_KVM_OPENPIC); 540 qdev_prop_set_uint32(dev, "model", params->mpic_version); 541 542 r = qdev_init(dev); 543 if (r) { 544 return NULL; 545 } 546 547 CPU_FOREACH(cs) { 548 if (kvm_openpic_connect_vcpu(dev, cs)) { 549 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n", 550 __func__); 551 abort(); 552 } 553 } 554 555 return dev; 556 } 557 558 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr, 559 qemu_irq **irqs) 560 { 561 qemu_irq *mpic; 562 DeviceState *dev = NULL; 563 SysBusDevice *s; 564 int i; 565 566 mpic = g_new(qemu_irq, 256); 567 568 if (kvm_enabled()) { 569 QemuOpts *machine_opts = qemu_get_machine_opts(); 570 bool irqchip_allowed = qemu_opt_get_bool(machine_opts, 571 "kernel_irqchip", true); 572 bool irqchip_required = qemu_opt_get_bool(machine_opts, 573 "kernel_irqchip", false); 574 575 if (irqchip_allowed) { 576 dev = ppce500_init_mpic_kvm(params, irqs); 577 } 578 579 if (irqchip_required && !dev) { 580 fprintf(stderr, "%s: irqchip requested but unavailable\n", 581 __func__); 582 abort(); 583 } 584 } 585 586 if (!dev) { 587 dev = ppce500_init_mpic_qemu(params, irqs); 588 } 589 590 for (i = 0; i < 256; i++) { 591 mpic[i] = qdev_get_gpio_in(dev, i); 592 } 593 594 s = SYS_BUS_DEVICE(dev); 595 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET, 596 s->mmio[0].memory); 597 598 return mpic; 599 } 600 601 void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params) 602 { 603 MemoryRegion *address_space_mem = get_system_memory(); 604 MemoryRegion *ram = g_new(MemoryRegion, 1); 605 PCIBus *pci_bus; 606 CPUPPCState *env = NULL; 607 uint64_t elf_entry; 608 uint64_t elf_lowaddr; 609 hwaddr entry=0; 610 hwaddr loadaddr=UIMAGE_LOAD_BASE; 611 target_long kernel_size=0; 612 target_ulong dt_base = 0; 613 target_ulong initrd_base = 0; 614 target_long initrd_size = 0; 615 target_ulong cur_base = 0; 616 int i; 617 unsigned int pci_irq_nrs[4] = {1, 2, 3, 4}; 618 qemu_irq **irqs, *mpic; 619 DeviceState *dev; 620 CPUPPCState *firstenv = NULL; 621 MemoryRegion *ccsr_addr_space; 622 SysBusDevice *s; 623 PPCE500CCSRState *ccsr; 624 625 /* Setup CPUs */ 626 if (args->cpu_model == NULL) { 627 args->cpu_model = "e500v2_v30"; 628 } 629 630 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); 631 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); 632 for (i = 0; i < smp_cpus; i++) { 633 PowerPCCPU *cpu; 634 CPUState *cs; 635 qemu_irq *input; 636 637 cpu = cpu_ppc_init(args->cpu_model); 638 if (cpu == NULL) { 639 fprintf(stderr, "Unable to initialize CPU!\n"); 640 exit(1); 641 } 642 env = &cpu->env; 643 cs = CPU(cpu); 644 645 if (!firstenv) { 646 firstenv = env; 647 } 648 649 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB); 650 input = (qemu_irq *)env->irq_inputs; 651 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; 652 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; 653 env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; 654 env->mpic_iack = MPC8544_CCSRBAR_BASE + 655 MPC8544_MPIC_REGS_OFFSET + 0xa0; 656 657 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500); 658 659 /* Register reset handler */ 660 if (!i) { 661 /* Primary CPU */ 662 struct boot_info *boot_info; 663 boot_info = g_malloc0(sizeof(struct boot_info)); 664 qemu_register_reset(ppce500_cpu_reset, cpu); 665 env->load_info = boot_info; 666 } else { 667 /* Secondary CPUs */ 668 qemu_register_reset(ppce500_cpu_reset_sec, cpu); 669 } 670 } 671 672 env = firstenv; 673 674 /* Fixup Memory size on a alignment boundary */ 675 ram_size &= ~(RAM_SIZES_ALIGN - 1); 676 args->ram_size = ram_size; 677 678 /* Register Memory */ 679 memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); 680 vmstate_register_ram_global(ram); 681 memory_region_add_subregion(address_space_mem, 0, ram); 682 683 dev = qdev_create(NULL, "e500-ccsr"); 684 object_property_add_child(qdev_get_machine(), "e500-ccsr", 685 OBJECT(dev), NULL); 686 qdev_init_nofail(dev); 687 ccsr = CCSR(dev); 688 ccsr_addr_space = &ccsr->ccsr_space; 689 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE, 690 ccsr_addr_space); 691 692 mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs); 693 694 /* Serial */ 695 if (serial_hds[0]) { 696 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET, 697 0, mpic[42], 399193, 698 serial_hds[0], DEVICE_BIG_ENDIAN); 699 } 700 701 if (serial_hds[1]) { 702 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET, 703 0, mpic[42], 399193, 704 serial_hds[1], DEVICE_BIG_ENDIAN); 705 } 706 707 /* General Utility device */ 708 dev = qdev_create(NULL, "mpc8544-guts"); 709 qdev_init_nofail(dev); 710 s = SYS_BUS_DEVICE(dev); 711 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET, 712 sysbus_mmio_get_region(s, 0)); 713 714 /* PCI */ 715 dev = qdev_create(NULL, "e500-pcihost"); 716 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot); 717 qdev_init_nofail(dev); 718 s = SYS_BUS_DEVICE(dev); 719 sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); 720 sysbus_connect_irq(s, 1, mpic[pci_irq_nrs[1]]); 721 sysbus_connect_irq(s, 2, mpic[pci_irq_nrs[2]]); 722 sysbus_connect_irq(s, 3, mpic[pci_irq_nrs[3]]); 723 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET, 724 sysbus_mmio_get_region(s, 0)); 725 726 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 727 if (!pci_bus) 728 printf("couldn't create PCI controller!\n"); 729 730 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO); 731 732 if (pci_bus) { 733 /* Register network interfaces. */ 734 for (i = 0; i < nb_nics; i++) { 735 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL); 736 } 737 } 738 739 /* Register spinning region */ 740 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL); 741 742 /* Load kernel. */ 743 if (args->kernel_filename) { 744 kernel_size = load_uimage(args->kernel_filename, &entry, 745 &loadaddr, NULL); 746 if (kernel_size < 0) { 747 kernel_size = load_elf(args->kernel_filename, NULL, NULL, 748 &elf_entry, &elf_lowaddr, NULL, 1, 749 ELF_MACHINE, 0); 750 entry = elf_entry; 751 loadaddr = elf_lowaddr; 752 } 753 /* XXX try again as binary */ 754 if (kernel_size < 0) { 755 fprintf(stderr, "qemu: could not load kernel '%s'\n", 756 args->kernel_filename); 757 exit(1); 758 } 759 760 cur_base = loadaddr + kernel_size; 761 762 /* Reserve space for dtb */ 763 dt_base = (cur_base + DTC_LOAD_PAD) & ~DTC_PAD_MASK; 764 cur_base += DTB_MAX_SIZE; 765 } 766 767 /* Load initrd. */ 768 if (args->initrd_filename) { 769 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; 770 initrd_size = load_image_targphys(args->initrd_filename, initrd_base, 771 ram_size - initrd_base); 772 773 if (initrd_size < 0) { 774 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 775 args->initrd_filename); 776 exit(1); 777 } 778 779 cur_base = initrd_base + initrd_size; 780 } 781 782 /* If we're loading a kernel directly, we must load the device tree too. */ 783 if (args->kernel_filename) { 784 struct boot_info *boot_info; 785 int dt_size; 786 787 dt_size = ppce500_prep_device_tree(args, params, dt_base, 788 initrd_base, initrd_size); 789 if (dt_size < 0) { 790 fprintf(stderr, "couldn't load device tree\n"); 791 exit(1); 792 } 793 assert(dt_size < DTB_MAX_SIZE); 794 795 boot_info = env->load_info; 796 boot_info->entry = entry; 797 boot_info->dt_base = dt_base; 798 boot_info->dt_size = dt_size; 799 } 800 801 if (kvm_enabled()) { 802 kvmppc_init(); 803 } 804 } 805 806 static int e500_ccsr_initfn(SysBusDevice *dev) 807 { 808 PPCE500CCSRState *ccsr; 809 810 ccsr = CCSR(dev); 811 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr", 812 MPC8544_CCSRBAR_SIZE); 813 return 0; 814 } 815 816 static void e500_ccsr_class_init(ObjectClass *klass, void *data) 817 { 818 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 819 k->init = e500_ccsr_initfn; 820 } 821 822 static const TypeInfo e500_ccsr_info = { 823 .name = TYPE_CCSR, 824 .parent = TYPE_SYS_BUS_DEVICE, 825 .instance_size = sizeof(PPCE500CCSRState), 826 .class_init = e500_ccsr_class_init, 827 }; 828 829 static void e500_register_types(void) 830 { 831 type_register_static(&e500_ccsr_info); 832 } 833 834 type_init(e500_register_types) 835