1 #include "qemu-common.h" 2 #include <strings.h> 3 #include <stdint.h> 4 #include "qemu/range.h" 5 #include "qemu/error-report.h" 6 #include "hw/pci/shpc.h" 7 #include "hw/pci/pci.h" 8 #include "hw/pci/pci_bus.h" 9 #include "hw/pci/msi.h" 10 #include "qapi/qmp/qerror.h" 11 12 /* TODO: model power only and disabled slot states. */ 13 /* TODO: handle SERR and wakeups */ 14 /* TODO: consider enabling 66MHz support */ 15 16 /* TODO: remove fully only on state DISABLED and LED off. 17 * track state to properly record this. */ 18 19 /* SHPC Working Register Set */ 20 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */ 21 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */ 22 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */ 23 #define SHPC_NSLOTS 0x0C /* 1 byte */ 24 #define SHPC_FIRST_DEV 0x0D /* 1 byte */ 25 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */ 26 #define SHPC_PHYS_NUM_MAX 0x7ff 27 #define SHPC_PHYS_NUM_UP 0x2000 28 #define SHPC_PHYS_MRL 0x4000 29 #define SHPC_PHYS_BUTTON 0x8000 30 #define SHPC_SEC_BUS 0x10 /* 2 bytes */ 31 #define SHPC_SEC_BUS_33 0x0 32 #define SHPC_SEC_BUS_66 0x1 /* Unused */ 33 #define SHPC_SEC_BUS_MASK 0x7 34 #define SHPC_MSI_CTL 0x12 /* 1 byte */ 35 #define SHPC_PROG_IFC 0x13 /* 1 byte */ 36 #define SHPC_PROG_IFC_1_0 0x1 37 #define SHPC_CMD_CODE 0x14 /* 1 byte */ 38 #define SHPC_CMD_TRGT 0x15 /* 1 byte */ 39 #define SHPC_CMD_TRGT_MIN 0x1 40 #define SHPC_CMD_TRGT_MAX 0x1f 41 #define SHPC_CMD_STATUS 0x16 /* 2 bytes */ 42 #define SHPC_CMD_STATUS_BUSY 0x1 43 #define SHPC_CMD_STATUS_MRL_OPEN 0x2 44 #define SHPC_CMD_STATUS_INVALID_CMD 0x4 45 #define SHPC_CMD_STATUS_INVALID_MODE 0x8 46 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */ 47 #define SHPC_INT_COMMAND 0x1 48 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */ 49 #define SHPC_SERR_INT 0x20 /* 4 bytes */ 50 #define SHPC_INT_DIS 0x1 51 #define SHPC_SERR_DIS 0x2 52 #define SHPC_CMD_INT_DIS 0x4 53 #define SHPC_ARB_SERR_DIS 0x8 54 #define SHPC_CMD_DETECTED 0x10000 55 #define SHPC_ARB_DETECTED 0x20000 56 /* 4 bytes * slot # (start from 0) */ 57 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) 58 /* 2 bytes */ 59 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s)) 60 61 /* Same slot state masks are used for command and status registers */ 62 #define SHPC_SLOT_STATE_MASK 0x03 63 #define SHPC_SLOT_STATE_SHIFT \ 64 ctz32(SHPC_SLOT_STATE_MASK) 65 66 #define SHPC_STATE_NO 0x0 67 #define SHPC_STATE_PWRONLY 0x1 68 #define SHPC_STATE_ENABLED 0x2 69 #define SHPC_STATE_DISABLED 0x3 70 71 #define SHPC_SLOT_PWR_LED_MASK 0xC 72 #define SHPC_SLOT_PWR_LED_SHIFT \ 73 ctz32(SHPC_SLOT_PWR_LED_MASK) 74 #define SHPC_SLOT_ATTN_LED_MASK 0x30 75 #define SHPC_SLOT_ATTN_LED_SHIFT \ 76 ctz32(SHPC_SLOT_ATTN_LED_MASK) 77 78 #define SHPC_LED_NO 0x0 79 #define SHPC_LED_ON 0x1 80 #define SHPC_LED_BLINK 0x2 81 #define SHPC_LED_OFF 0x3 82 83 #define SHPC_SLOT_STATUS_PWR_FAULT 0x40 84 #define SHPC_SLOT_STATUS_BUTTON 0x80 85 #define SHPC_SLOT_STATUS_MRL_OPEN 0x100 86 #define SHPC_SLOT_STATUS_66 0x200 87 #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00 88 #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3 89 #define SHPC_SLOT_STATUS_PRSNT_25W 0x1 90 #define SHPC_SLOT_STATUS_PRSNT_15W 0x2 91 #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0 92 93 #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000 94 95 96 /* 1 byte */ 97 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s)) 98 /* 1 byte */ 99 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s)) 100 #define SHPC_SLOT_EVENT_PRESENCE 0x01 101 #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02 102 #define SHPC_SLOT_EVENT_BUTTON 0x04 103 #define SHPC_SLOT_EVENT_MRL 0x08 104 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10 105 /* Bits below are used for Serr/Int disable only */ 106 #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20 107 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40 108 109 #define SHPC_MIN_SLOTS 1 110 #define SHPC_MAX_SLOTS 31 111 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots) 112 113 /* SHPC Slot identifiers */ 114 115 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0, 116 and give the rest of them physical *and* pci numbers starting from 1, so 117 they match logical numbers. Note: this means that multiple slots must have 118 different chassis number values, to make chassis+physical slot unique. 119 TODO: make this configurable? */ 120 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1) 121 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1) 122 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1) 123 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1) 124 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1) 125 126 static int roundup_pow_of_two(int x) 127 { 128 x |= (x >> 1); 129 x |= (x >> 2); 130 x |= (x >> 4); 131 x |= (x >> 8); 132 x |= (x >> 16); 133 return x + 1; 134 } 135 136 static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk) 137 { 138 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); 139 return (pci_get_word(status) & msk) >> ctz32(msk); 140 } 141 142 static void shpc_set_status(SHPCDevice *shpc, 143 int slot, uint8_t value, uint16_t msk) 144 { 145 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); 146 pci_word_test_and_clear_mask(status, msk); 147 pci_word_test_and_set_mask(status, value << ctz32(msk)); 148 } 149 150 static void shpc_interrupt_update(PCIDevice *d) 151 { 152 SHPCDevice *shpc = d->shpc; 153 int slot; 154 int level = 0; 155 uint32_t serr_int; 156 uint32_t int_locator = 0; 157 158 /* Update interrupt locator register */ 159 for (slot = 0; slot < shpc->nslots; ++slot) { 160 uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)]; 161 uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)]; 162 uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot); 163 if (event & ~disable) { 164 int_locator |= mask; 165 } 166 } 167 serr_int = pci_get_long(shpc->config + SHPC_SERR_INT); 168 if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) { 169 int_locator |= SHPC_INT_COMMAND; 170 } 171 pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator); 172 level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0; 173 if (msi_enabled(d) && shpc->msi_requested != level) 174 msi_notify(d, 0); 175 else 176 pci_set_irq(d, level); 177 shpc->msi_requested = level; 178 } 179 180 static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed) 181 { 182 switch (speed) { 183 case SHPC_SEC_BUS_33: 184 shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK; 185 shpc->config[SHPC_SEC_BUS] |= speed; 186 break; 187 default: 188 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, 189 SHPC_CMD_STATUS_INVALID_MODE); 190 } 191 } 192 193 void shpc_reset(PCIDevice *d) 194 { 195 SHPCDevice *shpc = d->shpc; 196 int nslots = shpc->nslots; 197 int i; 198 memset(shpc->config, 0, SHPC_SIZEOF(d)); 199 pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); 200 pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); 201 pci_set_long(shpc->config + SHPC_SLOTS_66, 0); 202 pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0)); 203 pci_set_word(shpc->config + SHPC_PHYS_SLOT, 204 SHPC_IDX_TO_PHYSICAL(0) | 205 SHPC_PHYS_NUM_UP | 206 SHPC_PHYS_MRL | 207 SHPC_PHYS_BUTTON); 208 pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS | 209 SHPC_SERR_DIS | 210 SHPC_CMD_INT_DIS | 211 SHPC_ARB_SERR_DIS); 212 pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0); 213 pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33); 214 for (i = 0; i < shpc->nslots; ++i) { 215 pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), 216 SHPC_SLOT_EVENT_PRESENCE | 217 SHPC_SLOT_EVENT_ISOLATED_FAULT | 218 SHPC_SLOT_EVENT_BUTTON | 219 SHPC_SLOT_EVENT_MRL | 220 SHPC_SLOT_EVENT_CONNECTED_FAULT | 221 SHPC_SLOT_EVENT_MRL_SERR_DIS | 222 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); 223 if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) { 224 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); 225 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN); 226 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W, 227 SHPC_SLOT_STATUS_PRSNT_MASK); 228 shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK); 229 } else { 230 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); 231 shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN); 232 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY, 233 SHPC_SLOT_STATUS_PRSNT_MASK); 234 shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK); 235 } 236 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66); 237 } 238 shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33); 239 shpc->msi_requested = 0; 240 shpc_interrupt_update(d); 241 } 242 243 static void shpc_invalid_command(SHPCDevice *shpc) 244 { 245 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, 246 SHPC_CMD_STATUS_INVALID_CMD); 247 } 248 249 static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot) 250 { 251 int devfn; 252 int pci_slot = SHPC_IDX_TO_PCI(slot); 253 for (devfn = PCI_DEVFN(pci_slot, 0); 254 devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1); 255 ++devfn) { 256 PCIDevice *affected_dev = shpc->sec_bus->devices[devfn]; 257 if (affected_dev) { 258 object_unparent(OBJECT(affected_dev)); 259 } 260 } 261 } 262 263 static void shpc_slot_command(SHPCDevice *shpc, uint8_t target, 264 uint8_t state, uint8_t power, uint8_t attn) 265 { 266 uint8_t current_state; 267 int slot = SHPC_LOGICAL_TO_IDX(target); 268 if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) { 269 shpc_invalid_command(shpc); 270 return; 271 } 272 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); 273 if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) { 274 shpc_invalid_command(shpc); 275 return; 276 } 277 278 switch (power) { 279 case SHPC_LED_NO: 280 break; 281 default: 282 /* TODO: send event to monitor */ 283 shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK); 284 } 285 switch (attn) { 286 case SHPC_LED_NO: 287 break; 288 default: 289 /* TODO: send event to monitor */ 290 shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK); 291 } 292 293 if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) || 294 (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) { 295 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); 296 } else if ((current_state == SHPC_STATE_ENABLED || 297 current_state == SHPC_STATE_PWRONLY) && 298 state == SHPC_STATE_DISABLED) { 299 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); 300 power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); 301 /* TODO: track what monitor requested. */ 302 /* Look at LED to figure out whether it's ok to remove the device. */ 303 if (power == SHPC_LED_OFF) { 304 shpc_free_devices_in_slot(shpc, slot); 305 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN); 306 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, 307 SHPC_SLOT_STATUS_PRSNT_MASK); 308 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 309 SHPC_SLOT_EVENT_BUTTON | 310 SHPC_SLOT_EVENT_MRL | 311 SHPC_SLOT_EVENT_PRESENCE; 312 } 313 } 314 } 315 316 static void shpc_command(SHPCDevice *shpc) 317 { 318 uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE); 319 uint8_t speed; 320 uint8_t target; 321 uint8_t attn; 322 uint8_t power; 323 uint8_t state; 324 int i; 325 326 /* Clear status from the previous command. */ 327 pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS, 328 SHPC_CMD_STATUS_BUSY | 329 SHPC_CMD_STATUS_MRL_OPEN | 330 SHPC_CMD_STATUS_INVALID_CMD | 331 SHPC_CMD_STATUS_INVALID_MODE); 332 switch (code) { 333 case 0x00 ... 0x3f: 334 target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX; 335 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; 336 power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT; 337 attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT; 338 shpc_slot_command(shpc, target, state, power, attn); 339 break; 340 case 0x40 ... 0x47: 341 speed = code & SHPC_SEC_BUS_MASK; 342 shpc_set_sec_bus_speed(shpc, speed); 343 break; 344 case 0x48: 345 /* Power only all slots */ 346 /* first verify no slots are enabled */ 347 for (i = 0; i < shpc->nslots; ++i) { 348 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); 349 if (state == SHPC_STATE_ENABLED) { 350 shpc_invalid_command(shpc); 351 goto done; 352 } 353 } 354 for (i = 0; i < shpc->nslots; ++i) { 355 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) { 356 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 357 SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO); 358 } else { 359 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 360 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); 361 } 362 } 363 break; 364 case 0x49: 365 /* Enable all slots */ 366 /* TODO: Spec says this shall fail if some are already enabled. 367 * This doesn't make sense - why not? a spec bug? */ 368 for (i = 0; i < shpc->nslots; ++i) { 369 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); 370 if (state == SHPC_STATE_ENABLED) { 371 shpc_invalid_command(shpc); 372 goto done; 373 } 374 } 375 for (i = 0; i < shpc->nslots; ++i) { 376 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) { 377 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 378 SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO); 379 } else { 380 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 381 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); 382 } 383 } 384 break; 385 default: 386 shpc_invalid_command(shpc); 387 break; 388 } 389 done: 390 pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED); 391 } 392 393 static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l) 394 { 395 SHPCDevice *shpc = d->shpc; 396 int i; 397 if (addr >= SHPC_SIZEOF(d)) { 398 return; 399 } 400 l = MIN(l, SHPC_SIZEOF(d) - addr); 401 402 /* TODO: code duplicated from pci.c */ 403 for (i = 0; i < l; val >>= 8, ++i) { 404 unsigned a = addr + i; 405 uint8_t wmask = shpc->wmask[a]; 406 uint8_t w1cmask = shpc->w1cmask[a]; 407 assert(!(wmask & w1cmask)); 408 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); 409 shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 410 } 411 if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) { 412 shpc_command(shpc); 413 } 414 shpc_interrupt_update(d); 415 } 416 417 static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l) 418 { 419 uint64_t val = 0x0; 420 if (addr >= SHPC_SIZEOF(d)) { 421 return val; 422 } 423 l = MIN(l, SHPC_SIZEOF(d) - addr); 424 memcpy(&val, d->shpc->config + addr, l); 425 return val; 426 } 427 428 /* SHPC Bridge Capability */ 429 #define SHPC_CAP_LENGTH 0x08 430 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */ 431 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */ 432 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */ 433 #define SHPC_CAP_CSP_MASK 0x4 434 #define SHPC_CAP_CIP_MASK 0x8 435 436 static uint8_t shpc_cap_dword(PCIDevice *d) 437 { 438 return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT); 439 } 440 441 /* Update dword data capability register */ 442 static void shpc_cap_update_dword(PCIDevice *d) 443 { 444 unsigned data; 445 data = shpc_read(d, shpc_cap_dword(d) * 4, 4); 446 pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data); 447 } 448 449 /* Add SHPC capability to the config space for the device. */ 450 static int shpc_cap_add_config(PCIDevice *d) 451 { 452 uint8_t *config; 453 int config_offset; 454 config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, 455 0, SHPC_CAP_LENGTH); 456 if (config_offset < 0) { 457 return config_offset; 458 } 459 config = d->config + config_offset; 460 461 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); 462 pci_set_byte(config + SHPC_CAP_CxP, 0); 463 pci_set_long(config + SHPC_CAP_DWORD_DATA, 0); 464 d->shpc->cap = config_offset; 465 /* Make dword select and data writeable. */ 466 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); 467 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); 468 return 0; 469 } 470 471 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, 472 unsigned size) 473 { 474 return shpc_read(opaque, addr, size); 475 } 476 477 static void shpc_mmio_write(void *opaque, hwaddr addr, 478 uint64_t val, unsigned size) 479 { 480 shpc_write(opaque, addr, val, size); 481 } 482 483 static const MemoryRegionOps shpc_mmio_ops = { 484 .read = shpc_mmio_read, 485 .write = shpc_mmio_write, 486 .endianness = DEVICE_LITTLE_ENDIAN, 487 .valid = { 488 /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't. 489 * It's easier to suppport all sizes than worry about it. */ 490 .min_access_size = 1, 491 .max_access_size = 4, 492 }, 493 }; 494 static void shpc_device_hotplug_common(PCIDevice *affected_dev, int *slot, 495 SHPCDevice *shpc, Error **errp) 496 { 497 int pci_slot = PCI_SLOT(affected_dev->devfn); 498 *slot = SHPC_PCI_TO_IDX(pci_slot); 499 500 if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) { 501 error_setg(errp, "Unsupported PCI slot %d for standard hotplug " 502 "controller. Valid slots are between %d and %d.", 503 pci_slot, SHPC_IDX_TO_PCI(0), 504 SHPC_IDX_TO_PCI(shpc->nslots) - 1); 505 return; 506 } 507 } 508 509 void shpc_device_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 510 Error **errp) 511 { 512 Error *local_err = NULL; 513 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); 514 SHPCDevice *shpc = pci_hotplug_dev->shpc; 515 int slot; 516 517 shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err); 518 if (local_err) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 523 /* Don't send event when device is enabled during qemu machine creation: 524 * it is present on boot, no hotplug event is necessary. We do send an 525 * event when the device is disabled later. */ 526 if (!dev->hotplugged) { 527 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); 528 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, 529 SHPC_SLOT_STATUS_PRSNT_MASK); 530 return; 531 } 532 533 /* This could be a cancellation of the previous removal. 534 * We check MRL state to figure out. */ 535 if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) { 536 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); 537 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, 538 SHPC_SLOT_STATUS_PRSNT_MASK); 539 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 540 SHPC_SLOT_EVENT_BUTTON | 541 SHPC_SLOT_EVENT_MRL | 542 SHPC_SLOT_EVENT_PRESENCE; 543 } else { 544 /* Press attention button to cancel removal */ 545 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 546 SHPC_SLOT_EVENT_BUTTON; 547 } 548 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); 549 shpc_interrupt_update(pci_hotplug_dev); 550 } 551 552 void shpc_device_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 553 DeviceState *dev, Error **errp) 554 { 555 Error *local_err = NULL; 556 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); 557 SHPCDevice *shpc = pci_hotplug_dev->shpc; 558 uint8_t state; 559 uint8_t led; 560 int slot; 561 562 shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err); 563 if (local_err) { 564 error_propagate(errp, local_err); 565 return; 566 } 567 568 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON; 569 state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); 570 led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); 571 if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) { 572 shpc_free_devices_in_slot(shpc, slot); 573 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN); 574 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, 575 SHPC_SLOT_STATUS_PRSNT_MASK); 576 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 577 SHPC_SLOT_EVENT_MRL | 578 SHPC_SLOT_EVENT_PRESENCE; 579 } 580 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); 581 shpc_interrupt_update(pci_hotplug_dev); 582 } 583 584 /* Initialize the SHPC structure in bridge's BAR. */ 585 int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset) 586 { 587 int i, ret; 588 int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */ 589 SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc)); 590 shpc->sec_bus = sec_bus; 591 ret = shpc_cap_add_config(d); 592 if (ret) { 593 g_free(d->shpc); 594 return ret; 595 } 596 if (nslots < SHPC_MIN_SLOTS) { 597 return 0; 598 } 599 if (nslots > SHPC_MAX_SLOTS || 600 SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) { 601 /* TODO: report an error mesage that makes sense. */ 602 return -EINVAL; 603 } 604 shpc->nslots = nslots; 605 shpc->config = g_malloc0(SHPC_SIZEOF(d)); 606 shpc->cmask = g_malloc0(SHPC_SIZEOF(d)); 607 shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); 608 shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d)); 609 610 shpc_reset(d); 611 612 pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset); 613 614 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); 615 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); 616 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); 617 pci_set_long(shpc->wmask + SHPC_SERR_INT, 618 SHPC_INT_DIS | 619 SHPC_SERR_DIS | 620 SHPC_CMD_INT_DIS | 621 SHPC_ARB_SERR_DIS); 622 pci_set_long(shpc->w1cmask + SHPC_SERR_INT, 623 SHPC_CMD_DETECTED | 624 SHPC_ARB_DETECTED); 625 for (i = 0; i < nslots; ++i) { 626 pci_set_byte(shpc->wmask + 627 SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), 628 SHPC_SLOT_EVENT_PRESENCE | 629 SHPC_SLOT_EVENT_ISOLATED_FAULT | 630 SHPC_SLOT_EVENT_BUTTON | 631 SHPC_SLOT_EVENT_MRL | 632 SHPC_SLOT_EVENT_CONNECTED_FAULT | 633 SHPC_SLOT_EVENT_MRL_SERR_DIS | 634 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); 635 pci_set_byte(shpc->w1cmask + 636 SHPC_SLOT_EVENT_LATCH(i), 637 SHPC_SLOT_EVENT_PRESENCE | 638 SHPC_SLOT_EVENT_ISOLATED_FAULT | 639 SHPC_SLOT_EVENT_BUTTON | 640 SHPC_SLOT_EVENT_MRL | 641 SHPC_SLOT_EVENT_CONNECTED_FAULT); 642 } 643 644 /* TODO: init cmask */ 645 memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops, 646 d, "shpc-mmio", SHPC_SIZEOF(d)); 647 shpc_cap_update_dword(d); 648 memory_region_add_subregion(bar, offset, &shpc->mmio); 649 650 qbus_set_hotplug_handler(BUS(sec_bus), DEVICE(d), NULL); 651 652 d->cap_present |= QEMU_PCI_CAP_SHPC; 653 return 0; 654 } 655 656 int shpc_bar_size(PCIDevice *d) 657 { 658 return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); 659 } 660 661 void shpc_cleanup(PCIDevice *d, MemoryRegion *bar) 662 { 663 SHPCDevice *shpc = d->shpc; 664 d->cap_present &= ~QEMU_PCI_CAP_SHPC; 665 memory_region_del_subregion(bar, &shpc->mmio); 666 /* TODO: cleanup config space changes? */ 667 } 668 669 void shpc_free(PCIDevice *d) 670 { 671 SHPCDevice *shpc = d->shpc; 672 if (!shpc) { 673 return; 674 } 675 object_unparent(OBJECT(&shpc->mmio)); 676 g_free(shpc->config); 677 g_free(shpc->cmask); 678 g_free(shpc->wmask); 679 g_free(shpc->w1cmask); 680 g_free(shpc); 681 d->shpc = NULL; 682 } 683 684 void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 685 { 686 if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) { 687 return; 688 } 689 if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) { 690 unsigned dword_data; 691 dword_data = pci_get_long(d->shpc->config + d->shpc->cap 692 + SHPC_CAP_DWORD_DATA); 693 shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4); 694 } 695 /* Update cap dword data in case guest is going to read it. */ 696 shpc_cap_update_dword(d); 697 } 698 699 static void shpc_save(QEMUFile *f, void *pv, size_t size) 700 { 701 PCIDevice *d = container_of(pv, PCIDevice, shpc); 702 qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); 703 } 704 705 static int shpc_load(QEMUFile *f, void *pv, size_t size) 706 { 707 PCIDevice *d = container_of(pv, PCIDevice, shpc); 708 int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); 709 if (ret != SHPC_SIZEOF(d)) { 710 return -EINVAL; 711 } 712 /* Make sure we don't lose notifications. An extra interrupt is harmless. */ 713 d->shpc->msi_requested = 0; 714 shpc_interrupt_update(d); 715 return 0; 716 } 717 718 VMStateInfo shpc_vmstate_info = { 719 .name = "shpc", 720 .get = shpc_load, 721 .put = shpc_save, 722 }; 723