1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "qemu-common.h" 4 #include "qemu/range.h" 5 #include "qemu/error-report.h" 6 #include "hw/pci/shpc.h" 7 #include "hw/pci/pci.h" 8 #include "hw/pci/pci_bus.h" 9 #include "hw/pci/msi.h" 10 11 /* TODO: model power only and disabled slot states. */ 12 /* TODO: handle SERR and wakeups */ 13 /* TODO: consider enabling 66MHz support */ 14 15 /* TODO: remove fully only on state DISABLED and LED off. 16 * track state to properly record this. */ 17 18 /* SHPC Working Register Set */ 19 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */ 20 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */ 21 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */ 22 #define SHPC_NSLOTS 0x0C /* 1 byte */ 23 #define SHPC_FIRST_DEV 0x0D /* 1 byte */ 24 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */ 25 #define SHPC_PHYS_NUM_MAX 0x7ff 26 #define SHPC_PHYS_NUM_UP 0x2000 27 #define SHPC_PHYS_MRL 0x4000 28 #define SHPC_PHYS_BUTTON 0x8000 29 #define SHPC_SEC_BUS 0x10 /* 2 bytes */ 30 #define SHPC_SEC_BUS_33 0x0 31 #define SHPC_SEC_BUS_66 0x1 /* Unused */ 32 #define SHPC_SEC_BUS_MASK 0x7 33 #define SHPC_MSI_CTL 0x12 /* 1 byte */ 34 #define SHPC_PROG_IFC 0x13 /* 1 byte */ 35 #define SHPC_PROG_IFC_1_0 0x1 36 #define SHPC_CMD_CODE 0x14 /* 1 byte */ 37 #define SHPC_CMD_TRGT 0x15 /* 1 byte */ 38 #define SHPC_CMD_TRGT_MIN 0x1 39 #define SHPC_CMD_TRGT_MAX 0x1f 40 #define SHPC_CMD_STATUS 0x16 /* 2 bytes */ 41 #define SHPC_CMD_STATUS_BUSY 0x1 42 #define SHPC_CMD_STATUS_MRL_OPEN 0x2 43 #define SHPC_CMD_STATUS_INVALID_CMD 0x4 44 #define SHPC_CMD_STATUS_INVALID_MODE 0x8 45 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */ 46 #define SHPC_INT_COMMAND 0x1 47 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */ 48 #define SHPC_SERR_INT 0x20 /* 4 bytes */ 49 #define SHPC_INT_DIS 0x1 50 #define SHPC_SERR_DIS 0x2 51 #define SHPC_CMD_INT_DIS 0x4 52 #define SHPC_ARB_SERR_DIS 0x8 53 #define SHPC_CMD_DETECTED 0x10000 54 #define SHPC_ARB_DETECTED 0x20000 55 /* 4 bytes * slot # (start from 0) */ 56 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4) 57 /* 2 bytes */ 58 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s)) 59 60 /* Same slot state masks are used for command and status registers */ 61 #define SHPC_SLOT_STATE_MASK 0x03 62 #define SHPC_SLOT_STATE_SHIFT \ 63 ctz32(SHPC_SLOT_STATE_MASK) 64 65 #define SHPC_STATE_NO 0x0 66 #define SHPC_STATE_PWRONLY 0x1 67 #define SHPC_STATE_ENABLED 0x2 68 #define SHPC_STATE_DISABLED 0x3 69 70 #define SHPC_SLOT_PWR_LED_MASK 0xC 71 #define SHPC_SLOT_PWR_LED_SHIFT \ 72 ctz32(SHPC_SLOT_PWR_LED_MASK) 73 #define SHPC_SLOT_ATTN_LED_MASK 0x30 74 #define SHPC_SLOT_ATTN_LED_SHIFT \ 75 ctz32(SHPC_SLOT_ATTN_LED_MASK) 76 77 #define SHPC_LED_NO 0x0 78 #define SHPC_LED_ON 0x1 79 #define SHPC_LED_BLINK 0x2 80 #define SHPC_LED_OFF 0x3 81 82 #define SHPC_SLOT_STATUS_PWR_FAULT 0x40 83 #define SHPC_SLOT_STATUS_BUTTON 0x80 84 #define SHPC_SLOT_STATUS_MRL_OPEN 0x100 85 #define SHPC_SLOT_STATUS_66 0x200 86 #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00 87 #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3 88 #define SHPC_SLOT_STATUS_PRSNT_25W 0x1 89 #define SHPC_SLOT_STATUS_PRSNT_15W 0x2 90 #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0 91 92 #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000 93 94 95 /* 1 byte */ 96 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s)) 97 /* 1 byte */ 98 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s)) 99 #define SHPC_SLOT_EVENT_PRESENCE 0x01 100 #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02 101 #define SHPC_SLOT_EVENT_BUTTON 0x04 102 #define SHPC_SLOT_EVENT_MRL 0x08 103 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10 104 /* Bits below are used for Serr/Int disable only */ 105 #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20 106 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40 107 108 #define SHPC_MIN_SLOTS 1 109 #define SHPC_MAX_SLOTS 31 110 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots) 111 112 /* SHPC Slot identifiers */ 113 114 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0, 115 and give the rest of them physical *and* pci numbers starting from 1, so 116 they match logical numbers. Note: this means that multiple slots must have 117 different chassis number values, to make chassis+physical slot unique. 118 TODO: make this configurable? */ 119 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1) 120 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1) 121 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1) 122 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1) 123 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1) 124 125 static int roundup_pow_of_two(int x) 126 { 127 x |= (x >> 1); 128 x |= (x >> 2); 129 x |= (x >> 4); 130 x |= (x >> 8); 131 x |= (x >> 16); 132 return x + 1; 133 } 134 135 static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk) 136 { 137 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); 138 return (pci_get_word(status) & msk) >> ctz32(msk); 139 } 140 141 static void shpc_set_status(SHPCDevice *shpc, 142 int slot, uint8_t value, uint16_t msk) 143 { 144 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot); 145 pci_word_test_and_clear_mask(status, msk); 146 pci_word_test_and_set_mask(status, value << ctz32(msk)); 147 } 148 149 static void shpc_interrupt_update(PCIDevice *d) 150 { 151 SHPCDevice *shpc = d->shpc; 152 int slot; 153 int level = 0; 154 uint32_t serr_int; 155 uint32_t int_locator = 0; 156 157 /* Update interrupt locator register */ 158 for (slot = 0; slot < shpc->nslots; ++slot) { 159 uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)]; 160 uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)]; 161 uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot); 162 if (event & ~disable) { 163 int_locator |= mask; 164 } 165 } 166 serr_int = pci_get_long(shpc->config + SHPC_SERR_INT); 167 if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) { 168 int_locator |= SHPC_INT_COMMAND; 169 } 170 pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator); 171 level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0; 172 if (msi_enabled(d) && shpc->msi_requested != level) 173 msi_notify(d, 0); 174 else 175 pci_set_irq(d, level); 176 shpc->msi_requested = level; 177 } 178 179 static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed) 180 { 181 switch (speed) { 182 case SHPC_SEC_BUS_33: 183 shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK; 184 shpc->config[SHPC_SEC_BUS] |= speed; 185 break; 186 default: 187 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, 188 SHPC_CMD_STATUS_INVALID_MODE); 189 } 190 } 191 192 void shpc_reset(PCIDevice *d) 193 { 194 SHPCDevice *shpc = d->shpc; 195 int nslots = shpc->nslots; 196 int i; 197 memset(shpc->config, 0, SHPC_SIZEOF(d)); 198 pci_set_byte(shpc->config + SHPC_NSLOTS, nslots); 199 pci_set_long(shpc->config + SHPC_SLOTS_33, nslots); 200 pci_set_long(shpc->config + SHPC_SLOTS_66, 0); 201 pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0)); 202 pci_set_word(shpc->config + SHPC_PHYS_SLOT, 203 SHPC_IDX_TO_PHYSICAL(0) | 204 SHPC_PHYS_NUM_UP | 205 SHPC_PHYS_MRL | 206 SHPC_PHYS_BUTTON); 207 pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS | 208 SHPC_SERR_DIS | 209 SHPC_CMD_INT_DIS | 210 SHPC_ARB_SERR_DIS); 211 pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0); 212 pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33); 213 for (i = 0; i < shpc->nslots; ++i) { 214 pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), 215 SHPC_SLOT_EVENT_PRESENCE | 216 SHPC_SLOT_EVENT_ISOLATED_FAULT | 217 SHPC_SLOT_EVENT_BUTTON | 218 SHPC_SLOT_EVENT_MRL | 219 SHPC_SLOT_EVENT_CONNECTED_FAULT | 220 SHPC_SLOT_EVENT_MRL_SERR_DIS | 221 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); 222 if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) { 223 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK); 224 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN); 225 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W, 226 SHPC_SLOT_STATUS_PRSNT_MASK); 227 shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK); 228 } else { 229 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK); 230 shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN); 231 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY, 232 SHPC_SLOT_STATUS_PRSNT_MASK); 233 shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK); 234 } 235 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66); 236 } 237 shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33); 238 shpc->msi_requested = 0; 239 shpc_interrupt_update(d); 240 } 241 242 static void shpc_invalid_command(SHPCDevice *shpc) 243 { 244 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS, 245 SHPC_CMD_STATUS_INVALID_CMD); 246 } 247 248 static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot) 249 { 250 int devfn; 251 int pci_slot = SHPC_IDX_TO_PCI(slot); 252 for (devfn = PCI_DEVFN(pci_slot, 0); 253 devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1); 254 ++devfn) { 255 PCIDevice *affected_dev = shpc->sec_bus->devices[devfn]; 256 if (affected_dev) { 257 object_unparent(OBJECT(affected_dev)); 258 } 259 } 260 } 261 262 static void shpc_slot_command(SHPCDevice *shpc, uint8_t target, 263 uint8_t state, uint8_t power, uint8_t attn) 264 { 265 uint8_t current_state; 266 int slot = SHPC_LOGICAL_TO_IDX(target); 267 if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) { 268 shpc_invalid_command(shpc); 269 return; 270 } 271 current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); 272 if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) { 273 shpc_invalid_command(shpc); 274 return; 275 } 276 277 switch (power) { 278 case SHPC_LED_NO: 279 break; 280 default: 281 /* TODO: send event to monitor */ 282 shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK); 283 } 284 switch (attn) { 285 case SHPC_LED_NO: 286 break; 287 default: 288 /* TODO: send event to monitor */ 289 shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK); 290 } 291 292 if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) || 293 (current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) { 294 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); 295 } else if ((current_state == SHPC_STATE_ENABLED || 296 current_state == SHPC_STATE_PWRONLY) && 297 state == SHPC_STATE_DISABLED) { 298 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK); 299 power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); 300 /* TODO: track what monitor requested. */ 301 /* Look at LED to figure out whether it's ok to remove the device. */ 302 if (power == SHPC_LED_OFF) { 303 shpc_free_devices_in_slot(shpc, slot); 304 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN); 305 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, 306 SHPC_SLOT_STATUS_PRSNT_MASK); 307 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 308 SHPC_SLOT_EVENT_BUTTON | 309 SHPC_SLOT_EVENT_MRL | 310 SHPC_SLOT_EVENT_PRESENCE; 311 } 312 } 313 } 314 315 static void shpc_command(SHPCDevice *shpc) 316 { 317 uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE); 318 uint8_t speed; 319 uint8_t target; 320 uint8_t attn; 321 uint8_t power; 322 uint8_t state; 323 int i; 324 325 /* Clear status from the previous command. */ 326 pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS, 327 SHPC_CMD_STATUS_BUSY | 328 SHPC_CMD_STATUS_MRL_OPEN | 329 SHPC_CMD_STATUS_INVALID_CMD | 330 SHPC_CMD_STATUS_INVALID_MODE); 331 switch (code) { 332 case 0x00 ... 0x3f: 333 target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX; 334 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT; 335 power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT; 336 attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT; 337 shpc_slot_command(shpc, target, state, power, attn); 338 break; 339 case 0x40 ... 0x47: 340 speed = code & SHPC_SEC_BUS_MASK; 341 shpc_set_sec_bus_speed(shpc, speed); 342 break; 343 case 0x48: 344 /* Power only all slots */ 345 /* first verify no slots are enabled */ 346 for (i = 0; i < shpc->nslots; ++i) { 347 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); 348 if (state == SHPC_STATE_ENABLED) { 349 shpc_invalid_command(shpc); 350 goto done; 351 } 352 } 353 for (i = 0; i < shpc->nslots; ++i) { 354 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) { 355 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 356 SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO); 357 } else { 358 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 359 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); 360 } 361 } 362 break; 363 case 0x49: 364 /* Enable all slots */ 365 /* TODO: Spec says this shall fail if some are already enabled. 366 * This doesn't make sense - why not? a spec bug? */ 367 for (i = 0; i < shpc->nslots; ++i) { 368 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK); 369 if (state == SHPC_STATE_ENABLED) { 370 shpc_invalid_command(shpc); 371 goto done; 372 } 373 } 374 for (i = 0; i < shpc->nslots; ++i) { 375 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) { 376 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 377 SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO); 378 } else { 379 shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN, 380 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO); 381 } 382 } 383 break; 384 default: 385 shpc_invalid_command(shpc); 386 break; 387 } 388 done: 389 pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED); 390 } 391 392 static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l) 393 { 394 SHPCDevice *shpc = d->shpc; 395 int i; 396 if (addr >= SHPC_SIZEOF(d)) { 397 return; 398 } 399 l = MIN(l, SHPC_SIZEOF(d) - addr); 400 401 /* TODO: code duplicated from pci.c */ 402 for (i = 0; i < l; val >>= 8, ++i) { 403 unsigned a = addr + i; 404 uint8_t wmask = shpc->wmask[a]; 405 uint8_t w1cmask = shpc->w1cmask[a]; 406 assert(!(wmask & w1cmask)); 407 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask); 408 shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ 409 } 410 if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) { 411 shpc_command(shpc); 412 } 413 shpc_interrupt_update(d); 414 } 415 416 static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l) 417 { 418 uint64_t val = 0x0; 419 if (addr >= SHPC_SIZEOF(d)) { 420 return val; 421 } 422 l = MIN(l, SHPC_SIZEOF(d) - addr); 423 memcpy(&val, d->shpc->config + addr, l); 424 return val; 425 } 426 427 /* SHPC Bridge Capability */ 428 #define SHPC_CAP_LENGTH 0x08 429 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */ 430 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */ 431 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */ 432 #define SHPC_CAP_CSP_MASK 0x4 433 #define SHPC_CAP_CIP_MASK 0x8 434 435 static uint8_t shpc_cap_dword(PCIDevice *d) 436 { 437 return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT); 438 } 439 440 /* Update dword data capability register */ 441 static void shpc_cap_update_dword(PCIDevice *d) 442 { 443 unsigned data; 444 data = shpc_read(d, shpc_cap_dword(d) * 4, 4); 445 pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data); 446 } 447 448 /* Add SHPC capability to the config space for the device. */ 449 static int shpc_cap_add_config(PCIDevice *d, Error **errp) 450 { 451 uint8_t *config; 452 int config_offset; 453 config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC, 454 0, SHPC_CAP_LENGTH, 455 errp); 456 if (config_offset < 0) { 457 return config_offset; 458 } 459 config = d->config + config_offset; 460 461 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0); 462 pci_set_byte(config + SHPC_CAP_CxP, 0); 463 pci_set_long(config + SHPC_CAP_DWORD_DATA, 0); 464 d->shpc->cap = config_offset; 465 /* Make dword select and data writeable. */ 466 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff); 467 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff); 468 return 0; 469 } 470 471 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr, 472 unsigned size) 473 { 474 return shpc_read(opaque, addr, size); 475 } 476 477 static void shpc_mmio_write(void *opaque, hwaddr addr, 478 uint64_t val, unsigned size) 479 { 480 shpc_write(opaque, addr, val, size); 481 } 482 483 static const MemoryRegionOps shpc_mmio_ops = { 484 .read = shpc_mmio_read, 485 .write = shpc_mmio_write, 486 .endianness = DEVICE_LITTLE_ENDIAN, 487 .valid = { 488 /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't. 489 * It's easier to suppport all sizes than worry about it. */ 490 .min_access_size = 1, 491 .max_access_size = 4, 492 }, 493 }; 494 static void shpc_device_hotplug_common(PCIDevice *affected_dev, int *slot, 495 SHPCDevice *shpc, Error **errp) 496 { 497 int pci_slot = PCI_SLOT(affected_dev->devfn); 498 *slot = SHPC_PCI_TO_IDX(pci_slot); 499 500 if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) { 501 error_setg(errp, "Unsupported PCI slot %d for standard hotplug " 502 "controller. Valid slots are between %d and %d.", 503 pci_slot, SHPC_IDX_TO_PCI(0), 504 SHPC_IDX_TO_PCI(shpc->nslots) - 1); 505 return; 506 } 507 } 508 509 void shpc_device_hotplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, 510 Error **errp) 511 { 512 Error *local_err = NULL; 513 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); 514 SHPCDevice *shpc = pci_hotplug_dev->shpc; 515 int slot; 516 517 shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err); 518 if (local_err) { 519 error_propagate(errp, local_err); 520 return; 521 } 522 523 /* Don't send event when device is enabled during qemu machine creation: 524 * it is present on boot, no hotplug event is necessary. We do send an 525 * event when the device is disabled later. */ 526 if (!dev->hotplugged) { 527 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); 528 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, 529 SHPC_SLOT_STATUS_PRSNT_MASK); 530 return; 531 } 532 533 /* This could be a cancellation of the previous removal. 534 * We check MRL state to figure out. */ 535 if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) { 536 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN); 537 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W, 538 SHPC_SLOT_STATUS_PRSNT_MASK); 539 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 540 SHPC_SLOT_EVENT_BUTTON | 541 SHPC_SLOT_EVENT_MRL | 542 SHPC_SLOT_EVENT_PRESENCE; 543 } else { 544 /* Press attention button to cancel removal */ 545 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 546 SHPC_SLOT_EVENT_BUTTON; 547 } 548 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); 549 shpc_interrupt_update(pci_hotplug_dev); 550 } 551 552 void shpc_device_hot_unplug_request_cb(HotplugHandler *hotplug_dev, 553 DeviceState *dev, Error **errp) 554 { 555 Error *local_err = NULL; 556 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev); 557 SHPCDevice *shpc = pci_hotplug_dev->shpc; 558 uint8_t state; 559 uint8_t led; 560 int slot; 561 562 shpc_device_hotplug_common(PCI_DEVICE(dev), &slot, shpc, &local_err); 563 if (local_err) { 564 error_propagate(errp, local_err); 565 return; 566 } 567 568 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON; 569 state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK); 570 led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK); 571 if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) { 572 shpc_free_devices_in_slot(shpc, slot); 573 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN); 574 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY, 575 SHPC_SLOT_STATUS_PRSNT_MASK); 576 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= 577 SHPC_SLOT_EVENT_MRL | 578 SHPC_SLOT_EVENT_PRESENCE; 579 } 580 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66); 581 shpc_interrupt_update(pci_hotplug_dev); 582 } 583 584 /* Initialize the SHPC structure in bridge's BAR. */ 585 int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, 586 unsigned offset, Error **errp) 587 { 588 int i, ret; 589 int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */ 590 SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc)); 591 shpc->sec_bus = sec_bus; 592 ret = shpc_cap_add_config(d, errp); 593 if (ret) { 594 g_free(d->shpc); 595 return ret; 596 } 597 if (nslots < SHPC_MIN_SLOTS) { 598 return 0; 599 } 600 if (nslots > SHPC_MAX_SLOTS || 601 SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) { 602 /* TODO: report an error mesage that makes sense. */ 603 return -EINVAL; 604 } 605 shpc->nslots = nslots; 606 shpc->config = g_malloc0(SHPC_SIZEOF(d)); 607 shpc->cmask = g_malloc0(SHPC_SIZEOF(d)); 608 shpc->wmask = g_malloc0(SHPC_SIZEOF(d)); 609 shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d)); 610 611 shpc_reset(d); 612 613 pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset); 614 615 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff); 616 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); 617 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX); 618 pci_set_long(shpc->wmask + SHPC_SERR_INT, 619 SHPC_INT_DIS | 620 SHPC_SERR_DIS | 621 SHPC_CMD_INT_DIS | 622 SHPC_ARB_SERR_DIS); 623 pci_set_long(shpc->w1cmask + SHPC_SERR_INT, 624 SHPC_CMD_DETECTED | 625 SHPC_ARB_DETECTED); 626 for (i = 0; i < nslots; ++i) { 627 pci_set_byte(shpc->wmask + 628 SHPC_SLOT_EVENT_SERR_INT_DIS(d, i), 629 SHPC_SLOT_EVENT_PRESENCE | 630 SHPC_SLOT_EVENT_ISOLATED_FAULT | 631 SHPC_SLOT_EVENT_BUTTON | 632 SHPC_SLOT_EVENT_MRL | 633 SHPC_SLOT_EVENT_CONNECTED_FAULT | 634 SHPC_SLOT_EVENT_MRL_SERR_DIS | 635 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS); 636 pci_set_byte(shpc->w1cmask + 637 SHPC_SLOT_EVENT_LATCH(i), 638 SHPC_SLOT_EVENT_PRESENCE | 639 SHPC_SLOT_EVENT_ISOLATED_FAULT | 640 SHPC_SLOT_EVENT_BUTTON | 641 SHPC_SLOT_EVENT_MRL | 642 SHPC_SLOT_EVENT_CONNECTED_FAULT); 643 } 644 645 /* TODO: init cmask */ 646 memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops, 647 d, "shpc-mmio", SHPC_SIZEOF(d)); 648 shpc_cap_update_dword(d); 649 memory_region_add_subregion(bar, offset, &shpc->mmio); 650 651 qbus_set_hotplug_handler(BUS(sec_bus), DEVICE(d), NULL); 652 653 d->cap_present |= QEMU_PCI_CAP_SHPC; 654 return 0; 655 } 656 657 int shpc_bar_size(PCIDevice *d) 658 { 659 return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS)); 660 } 661 662 void shpc_cleanup(PCIDevice *d, MemoryRegion *bar) 663 { 664 SHPCDevice *shpc = d->shpc; 665 d->cap_present &= ~QEMU_PCI_CAP_SHPC; 666 memory_region_del_subregion(bar, &shpc->mmio); 667 /* TODO: cleanup config space changes? */ 668 } 669 670 void shpc_free(PCIDevice *d) 671 { 672 SHPCDevice *shpc = d->shpc; 673 if (!shpc) { 674 return; 675 } 676 object_unparent(OBJECT(&shpc->mmio)); 677 g_free(shpc->config); 678 g_free(shpc->cmask); 679 g_free(shpc->wmask); 680 g_free(shpc->w1cmask); 681 g_free(shpc); 682 d->shpc = NULL; 683 } 684 685 void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l) 686 { 687 if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) { 688 return; 689 } 690 if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) { 691 unsigned dword_data; 692 dword_data = pci_get_long(d->shpc->config + d->shpc->cap 693 + SHPC_CAP_DWORD_DATA); 694 shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4); 695 } 696 /* Update cap dword data in case guest is going to read it. */ 697 shpc_cap_update_dword(d); 698 } 699 700 static int shpc_save(QEMUFile *f, void *pv, size_t size, VMStateField *field, 701 QJSON *vmdesc) 702 { 703 PCIDevice *d = container_of(pv, PCIDevice, shpc); 704 qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); 705 706 return 0; 707 } 708 709 static int shpc_load(QEMUFile *f, void *pv, size_t size, VMStateField *field) 710 { 711 PCIDevice *d = container_of(pv, PCIDevice, shpc); 712 int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d)); 713 if (ret != SHPC_SIZEOF(d)) { 714 return -EINVAL; 715 } 716 /* Make sure we don't lose notifications. An extra interrupt is harmless. */ 717 d->shpc->msi_requested = 0; 718 shpc_interrupt_update(d); 719 return 0; 720 } 721 722 VMStateInfo shpc_vmstate_info = { 723 .name = "shpc", 724 .get = shpc_load, 725 .put = shpc_save, 726 }; 727