1 #include "qemu/osdep.h"
2 #include "qapi/error.h"
3 #include "qemu/host-utils.h"
4 #include "qemu/range.h"
5 #include "qemu/error-report.h"
6 #include "hw/pci/shpc.h"
7 #include "migration/qemu-file-types.h"
8 #include "hw/pci/pci.h"
9 #include "hw/pci/pci_bus.h"
10 #include "hw/pci/msi.h"
11 #include "trace.h"
12
13 /* TODO: model power only and disabled slot states. */
14 /* TODO: handle SERR and wakeups */
15 /* TODO: consider enabling 66MHz support */
16
17 /* TODO: remove fully only on state DISABLED and LED off.
18 * track state to properly record this. */
19
20 /* SHPC Working Register Set */
21 #define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
22 #define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
23 #define SHPC_SLOTS_66 0x08 /* 4 bytes. */
24 #define SHPC_NSLOTS 0x0C /* 1 byte */
25 #define SHPC_FIRST_DEV 0x0D /* 1 byte */
26 #define SHPC_PHYS_SLOT 0x0E /* 2 byte */
27 #define SHPC_PHYS_NUM_MAX 0x7ff
28 #define SHPC_PHYS_NUM_UP 0x2000
29 #define SHPC_PHYS_MRL 0x4000
30 #define SHPC_PHYS_BUTTON 0x8000
31 #define SHPC_SEC_BUS 0x10 /* 2 bytes */
32 #define SHPC_SEC_BUS_33 0x0
33 #define SHPC_SEC_BUS_66 0x1 /* Unused */
34 #define SHPC_SEC_BUS_MASK 0x7
35 #define SHPC_MSI_CTL 0x12 /* 1 byte */
36 #define SHPC_PROG_IFC 0x13 /* 1 byte */
37 #define SHPC_PROG_IFC_1_0 0x1
38 #define SHPC_CMD_CODE 0x14 /* 1 byte */
39 #define SHPC_CMD_TRGT 0x15 /* 1 byte */
40 #define SHPC_CMD_TRGT_MIN 0x1
41 #define SHPC_CMD_TRGT_MAX 0x1f
42 #define SHPC_CMD_STATUS 0x16 /* 2 bytes */
43 #define SHPC_CMD_STATUS_BUSY 0x1
44 #define SHPC_CMD_STATUS_MRL_OPEN 0x2
45 #define SHPC_CMD_STATUS_INVALID_CMD 0x4
46 #define SHPC_CMD_STATUS_INVALID_MODE 0x8
47 #define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
48 #define SHPC_INT_COMMAND 0x1
49 #define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
50 #define SHPC_SERR_INT 0x20 /* 4 bytes */
51 #define SHPC_INT_DIS 0x1
52 #define SHPC_SERR_DIS 0x2
53 #define SHPC_CMD_INT_DIS 0x4
54 #define SHPC_ARB_SERR_DIS 0x8
55 #define SHPC_CMD_DETECTED 0x10000
56 #define SHPC_ARB_DETECTED 0x20000
57 /* 4 bytes * slot # (start from 0) */
58 #define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
59 /* 2 bytes */
60 #define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
61
62 /* Same slot state masks are used for command and status registers */
63 #define SHPC_SLOT_STATE_MASK 0x03
64 #define SHPC_SLOT_STATE_SHIFT \
65 ctz32(SHPC_SLOT_STATE_MASK)
66
67 #define SHPC_STATE_NO 0x0
68 #define SHPC_STATE_PWRONLY 0x1
69 #define SHPC_STATE_ENABLED 0x2
70 #define SHPC_STATE_DISABLED 0x3
71
72 #define SHPC_SLOT_PWR_LED_MASK 0xC
73 #define SHPC_SLOT_PWR_LED_SHIFT \
74 ctz32(SHPC_SLOT_PWR_LED_MASK)
75 #define SHPC_SLOT_ATTN_LED_MASK 0x30
76 #define SHPC_SLOT_ATTN_LED_SHIFT \
77 ctz32(SHPC_SLOT_ATTN_LED_MASK)
78
79 #define SHPC_LED_NO 0x0
80 #define SHPC_LED_ON 0x1
81 #define SHPC_LED_BLINK 0x2
82 #define SHPC_LED_OFF 0x3
83
84 #define SHPC_SLOT_STATUS_PWR_FAULT 0x40
85 #define SHPC_SLOT_STATUS_BUTTON 0x80
86 #define SHPC_SLOT_STATUS_MRL_OPEN 0x100
87 #define SHPC_SLOT_STATUS_66 0x200
88 #define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
89 #define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
90 #define SHPC_SLOT_STATUS_PRSNT_25W 0x1
91 #define SHPC_SLOT_STATUS_PRSNT_15W 0x2
92 #define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
93
94 #define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
95
96
97 /* 1 byte */
98 #define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
99 /* 1 byte */
100 #define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
101 #define SHPC_SLOT_EVENT_PRESENCE 0x01
102 #define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
103 #define SHPC_SLOT_EVENT_BUTTON 0x04
104 #define SHPC_SLOT_EVENT_MRL 0x08
105 #define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
106 /* Bits below are used for Serr/Int disable only */
107 #define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
108 #define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
109
110 #define SHPC_MIN_SLOTS 1
111 #define SHPC_MAX_SLOTS 31
112 #define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
113
114 /* SHPC Slot identifiers */
115
116 /* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
117 and give the rest of them physical *and* pci numbers starting from 1, so
118 they match logical numbers. Note: this means that multiple slots must have
119 different chassis number values, to make chassis+physical slot unique.
120 TODO: make this configurable? */
121 #define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
122 #define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
123 #define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
124 #define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
125 #define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
126
shpc_led_state_to_str(uint8_t value)127 static const char *shpc_led_state_to_str(uint8_t value)
128 {
129 switch (value) {
130 case SHPC_LED_ON:
131 return "on";
132 case SHPC_LED_BLINK:
133 return "blink";
134 case SHPC_LED_OFF:
135 return "off";
136 default:
137 return "invalid";
138 }
139 }
140
shpc_slot_state_to_str(uint8_t value)141 static const char *shpc_slot_state_to_str(uint8_t value)
142 {
143 switch (value) {
144 case SHPC_STATE_PWRONLY:
145 return "power-only";
146 case SHPC_STATE_ENABLED:
147 return "enabled";
148 case SHPC_STATE_DISABLED:
149 return "disabled";
150 default:
151 return "invalid";
152 }
153 }
154
shpc_get_status(SHPCDevice * shpc,int slot,uint16_t msk)155 static uint8_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
156 {
157 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
158 uint16_t result = (pci_get_word(status) & msk) >> ctz32(msk);
159
160 assert(result <= UINT8_MAX);
161 return result;
162 }
163
shpc_set_status(SHPCDevice * shpc,int slot,uint8_t value,uint16_t msk)164 static void shpc_set_status(SHPCDevice *shpc,
165 int slot, uint8_t value, uint16_t msk)
166 {
167 uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
168 pci_word_test_and_clear_mask(status, msk);
169 pci_word_test_and_set_mask(status, value << ctz32(msk));
170 }
171
shpc_interrupt_update(PCIDevice * d)172 static void shpc_interrupt_update(PCIDevice *d)
173 {
174 SHPCDevice *shpc = d->shpc;
175 int slot;
176 int level = 0;
177 uint32_t serr_int;
178 uint32_t int_locator = 0;
179
180 /* Update interrupt locator register */
181 for (slot = 0; slot < shpc->nslots; ++slot) {
182 uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
183 uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
184 uint32_t mask = 1U << SHPC_IDX_TO_LOGICAL(slot);
185 if (event & ~disable) {
186 int_locator |= mask;
187 }
188 }
189 serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
190 if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
191 int_locator |= SHPC_INT_COMMAND;
192 }
193 pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
194 level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
195 if (msi_enabled(d) && shpc->msi_requested != level)
196 msi_notify(d, 0);
197 else
198 pci_set_irq(d, level);
199 shpc->msi_requested = level;
200 }
201
shpc_set_sec_bus_speed(SHPCDevice * shpc,uint8_t speed)202 static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
203 {
204 switch (speed) {
205 case SHPC_SEC_BUS_33:
206 shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
207 shpc->config[SHPC_SEC_BUS] |= speed;
208 break;
209 default:
210 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
211 SHPC_CMD_STATUS_INVALID_MODE);
212 }
213 }
214
shpc_reset(PCIDevice * d)215 void shpc_reset(PCIDevice *d)
216 {
217 SHPCDevice *shpc = d->shpc;
218 int nslots = shpc->nslots;
219 int i;
220 memset(shpc->config, 0, SHPC_SIZEOF(d));
221 pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
222 pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
223 pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
224 pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
225 pci_set_word(shpc->config + SHPC_PHYS_SLOT,
226 SHPC_IDX_TO_PHYSICAL(0) |
227 SHPC_PHYS_NUM_UP |
228 SHPC_PHYS_MRL |
229 SHPC_PHYS_BUTTON);
230 pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
231 SHPC_SERR_DIS |
232 SHPC_CMD_INT_DIS |
233 SHPC_ARB_SERR_DIS);
234 pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
235 pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
236 for (i = 0; i < shpc->nslots; ++i) {
237 pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
238 SHPC_SLOT_EVENT_PRESENCE |
239 SHPC_SLOT_EVENT_ISOLATED_FAULT |
240 SHPC_SLOT_EVENT_BUTTON |
241 SHPC_SLOT_EVENT_MRL |
242 SHPC_SLOT_EVENT_CONNECTED_FAULT |
243 SHPC_SLOT_EVENT_MRL_SERR_DIS |
244 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
245 if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
246 shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
247 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
248 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
249 SHPC_SLOT_STATUS_PRSNT_MASK);
250 shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
251 } else {
252 shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
253 shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
254 shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
255 SHPC_SLOT_STATUS_PRSNT_MASK);
256 shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
257 }
258 shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_ATTN_LED_MASK);
259 shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
260 }
261 shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
262 shpc->msi_requested = 0;
263 shpc_interrupt_update(d);
264 }
265
shpc_invalid_command(SHPCDevice * shpc)266 static void shpc_invalid_command(SHPCDevice *shpc)
267 {
268 pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
269 SHPC_CMD_STATUS_INVALID_CMD);
270 }
271
shpc_free_devices_in_slot(SHPCDevice * shpc,int slot)272 static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
273 {
274 HotplugHandler *hotplug_ctrl;
275 int devfn;
276 int pci_slot = SHPC_IDX_TO_PCI(slot);
277 for (devfn = PCI_DEVFN(pci_slot, 0);
278 devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
279 ++devfn) {
280 PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
281 if (affected_dev) {
282 hotplug_ctrl = qdev_get_hotplug_handler(DEVICE(affected_dev));
283 hotplug_handler_unplug(hotplug_ctrl, DEVICE(affected_dev),
284 &error_abort);
285 object_unparent(OBJECT(affected_dev));
286 }
287 }
288 }
289
shpc_slot_is_off(uint8_t state,uint8_t power,uint8_t attn)290 static bool shpc_slot_is_off(uint8_t state, uint8_t power, uint8_t attn)
291 {
292 return state == SHPC_STATE_DISABLED && power == SHPC_LED_OFF;
293 }
294
shpc_slot_command(PCIDevice * d,uint8_t target,uint8_t state,uint8_t power,uint8_t attn)295 static void shpc_slot_command(PCIDevice *d, uint8_t target,
296 uint8_t state, uint8_t power, uint8_t attn)
297 {
298 SHPCDevice *shpc = d->shpc;
299 int slot = SHPC_LOGICAL_TO_IDX(target);
300 uint8_t old_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
301 uint8_t old_power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
302 uint8_t old_attn = shpc_get_status(shpc, slot, SHPC_SLOT_ATTN_LED_MASK);
303
304 if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
305 shpc_invalid_command(shpc);
306 return;
307 }
308
309 if (old_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
310 shpc_invalid_command(shpc);
311 return;
312 }
313
314 if (power == SHPC_LED_NO) {
315 power = old_power;
316 } else {
317 /* TODO: send event to monitor */
318 shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
319 }
320
321 if (attn == SHPC_LED_NO) {
322 attn = old_attn;
323 } else {
324 /* TODO: send event to monitor */
325 shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
326 }
327
328 if (state == SHPC_STATE_NO) {
329 state = old_state;
330 } else {
331 shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
332 }
333
334 if (trace_event_get_state_backends(TRACE_SHPC_SLOT_COMMAND)) {
335 DeviceState *parent = DEVICE(d);
336 int pci_slot = SHPC_IDX_TO_PCI(slot);
337 DeviceState *child =
338 DEVICE(shpc->sec_bus->devices[PCI_DEVFN(pci_slot, 0)]);
339
340 trace_shpc_slot_command(
341 parent->canonical_path, pci_slot,
342 child ? child->canonical_path : "no-child",
343 shpc_led_state_to_str(old_power),
344 shpc_led_state_to_str(power),
345 shpc_led_state_to_str(old_attn),
346 shpc_led_state_to_str(attn),
347 shpc_slot_state_to_str(old_state),
348 shpc_slot_state_to_str(state));
349 }
350
351 if (!shpc_slot_is_off(old_state, old_power, old_attn) &&
352 shpc_slot_is_off(state, power, attn))
353 {
354 shpc_free_devices_in_slot(shpc, slot);
355 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
356 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
357 SHPC_SLOT_STATUS_PRSNT_MASK);
358 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
359 SHPC_SLOT_EVENT_MRL |
360 SHPC_SLOT_EVENT_PRESENCE;
361 }
362 }
363
shpc_command(PCIDevice * d)364 static void shpc_command(PCIDevice *d)
365 {
366 SHPCDevice *shpc = d->shpc;
367 uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
368 uint8_t speed;
369 uint8_t target;
370 uint8_t attn;
371 uint8_t power;
372 uint8_t state;
373 int i;
374
375 /* Clear status from the previous command. */
376 pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
377 SHPC_CMD_STATUS_BUSY |
378 SHPC_CMD_STATUS_MRL_OPEN |
379 SHPC_CMD_STATUS_INVALID_CMD |
380 SHPC_CMD_STATUS_INVALID_MODE);
381 switch (code) {
382 case 0x00 ... 0x3f:
383 target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
384 state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
385 power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
386 attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
387 shpc_slot_command(d, target, state, power, attn);
388 break;
389 case 0x40 ... 0x47:
390 speed = code & SHPC_SEC_BUS_MASK;
391 shpc_set_sec_bus_speed(shpc, speed);
392 break;
393 case 0x48:
394 /* Power only all slots */
395 /* first verify no slots are enabled */
396 for (i = 0; i < shpc->nslots; ++i) {
397 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
398 if (state == SHPC_STATE_ENABLED) {
399 shpc_invalid_command(shpc);
400 goto done;
401 }
402 }
403 for (i = 0; i < shpc->nslots; ++i) {
404 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
405 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
406 SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
407 } else {
408 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
409 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
410 }
411 }
412 break;
413 case 0x49:
414 /* Enable all slots */
415 /* TODO: Spec says this shall fail if some are already enabled.
416 * This doesn't make sense - why not? a spec bug? */
417 for (i = 0; i < shpc->nslots; ++i) {
418 state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
419 if (state == SHPC_STATE_ENABLED) {
420 shpc_invalid_command(shpc);
421 goto done;
422 }
423 }
424 for (i = 0; i < shpc->nslots; ++i) {
425 if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
426 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
427 SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
428 } else {
429 shpc_slot_command(d, i + SHPC_CMD_TRGT_MIN,
430 SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
431 }
432 }
433 break;
434 default:
435 shpc_invalid_command(shpc);
436 break;
437 }
438 done:
439 pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
440 }
441
shpc_write(PCIDevice * d,unsigned addr,uint64_t val,int l)442 static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
443 {
444 SHPCDevice *shpc = d->shpc;
445 int i;
446 if (addr >= SHPC_SIZEOF(d)) {
447 return;
448 }
449 l = MIN(l, SHPC_SIZEOF(d) - addr);
450
451 /* TODO: code duplicated from pci.c */
452 for (i = 0; i < l; val >>= 8, ++i) {
453 unsigned a = addr + i;
454 uint8_t wmask = shpc->wmask[a];
455 uint8_t w1cmask = shpc->w1cmask[a];
456 assert(!(wmask & w1cmask));
457 shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
458 shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
459 }
460 if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
461 shpc_command(d);
462 }
463 shpc_interrupt_update(d);
464 }
465
shpc_read(PCIDevice * d,unsigned addr,int l)466 static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
467 {
468 uint64_t val = 0x0;
469 if (addr >= SHPC_SIZEOF(d)) {
470 return val;
471 }
472 l = MIN(l, SHPC_SIZEOF(d) - addr);
473 memcpy(&val, d->shpc->config + addr, l);
474 return val;
475 }
476
477 /* SHPC Bridge Capability */
478 #define SHPC_CAP_LENGTH 0x08
479 #define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
480 #define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
481 #define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
482 #define SHPC_CAP_CSP_MASK 0x4
483 #define SHPC_CAP_CIP_MASK 0x8
484
shpc_cap_dword(PCIDevice * d)485 static uint8_t shpc_cap_dword(PCIDevice *d)
486 {
487 return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
488 }
489
490 /* Update dword data capability register */
shpc_cap_update_dword(PCIDevice * d)491 static void shpc_cap_update_dword(PCIDevice *d)
492 {
493 unsigned data;
494 data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
495 pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
496 }
497
498 /* Add SHPC capability to the config space for the device. */
shpc_cap_add_config(PCIDevice * d,Error ** errp)499 static int shpc_cap_add_config(PCIDevice *d, Error **errp)
500 {
501 uint8_t *config;
502 int config_offset;
503 config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
504 0, SHPC_CAP_LENGTH,
505 errp);
506 if (config_offset < 0) {
507 return config_offset;
508 }
509 config = d->config + config_offset;
510
511 pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
512 pci_set_byte(config + SHPC_CAP_CxP, 0);
513 pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
514 d->shpc->cap = config_offset;
515 /* Make dword select and data writable. */
516 pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
517 pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
518 return 0;
519 }
520
shpc_mmio_read(void * opaque,hwaddr addr,unsigned size)521 static uint64_t shpc_mmio_read(void *opaque, hwaddr addr,
522 unsigned size)
523 {
524 return shpc_read(opaque, addr, size);
525 }
526
shpc_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)527 static void shpc_mmio_write(void *opaque, hwaddr addr,
528 uint64_t val, unsigned size)
529 {
530 shpc_write(opaque, addr, val, size);
531 }
532
533 static const MemoryRegionOps shpc_mmio_ops = {
534 .read = shpc_mmio_read,
535 .write = shpc_mmio_write,
536 .endianness = DEVICE_LITTLE_ENDIAN,
537 .valid = {
538 /* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
539 * It's easier to support all sizes than worry about it.
540 */
541 .min_access_size = 1,
542 .max_access_size = 4,
543 },
544 };
545
shpc_device_get_slot(PCIDevice * affected_dev,int * slot,SHPCDevice * shpc,Error ** errp)546 static bool shpc_device_get_slot(PCIDevice *affected_dev, int *slot,
547 SHPCDevice *shpc, Error **errp)
548 {
549 int pci_slot = PCI_SLOT(affected_dev->devfn);
550 *slot = SHPC_PCI_TO_IDX(pci_slot);
551
552 if (pci_slot < SHPC_IDX_TO_PCI(0) || *slot >= shpc->nslots) {
553 error_setg(errp, "Unsupported PCI slot %d for standard hotplug "
554 "controller. Valid slots are between %d and %d.",
555 pci_slot, SHPC_IDX_TO_PCI(0),
556 SHPC_IDX_TO_PCI(shpc->nslots) - 1);
557 return false;
558 }
559
560 return true;
561 }
562
shpc_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)563 void shpc_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
564 Error **errp)
565 {
566 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
567 SHPCDevice *shpc = pci_hotplug_dev->shpc;
568 int slot;
569
570 if (!shpc_device_get_slot(PCI_DEVICE(dev), &slot, shpc, errp)) {
571 return;
572 }
573
574 /* Don't send event when device is enabled during qemu machine creation:
575 * it is present on boot, no hotplug event is necessary. We do send an
576 * event when the device is disabled later. */
577 if (!dev->hotplugged) {
578 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
579 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
580 SHPC_SLOT_STATUS_PRSNT_MASK);
581 return;
582 }
583
584 /* This could be a cancellation of the previous removal.
585 * We check MRL state to figure out. */
586 if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
587 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
588 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
589 SHPC_SLOT_STATUS_PRSNT_MASK);
590 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
591 SHPC_SLOT_EVENT_BUTTON |
592 SHPC_SLOT_EVENT_MRL |
593 SHPC_SLOT_EVENT_PRESENCE;
594 } else {
595 /* Press attention button to cancel removal */
596 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
597 SHPC_SLOT_EVENT_BUTTON;
598 }
599 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
600 shpc_interrupt_update(pci_hotplug_dev);
601 }
602
shpc_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)603 void shpc_device_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
604 Error **errp)
605 {
606 qdev_unrealize(dev);
607 }
608
shpc_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)609 void shpc_device_unplug_request_cb(HotplugHandler *hotplug_dev,
610 DeviceState *dev, Error **errp)
611 {
612 PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
613 SHPCDevice *shpc = pci_hotplug_dev->shpc;
614 uint8_t state;
615 uint8_t led;
616 int slot;
617
618 if (!shpc_device_get_slot(PCI_DEVICE(dev), &slot, shpc, errp)) {
619 return;
620 }
621
622 state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
623 led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
624
625 if (led == SHPC_LED_BLINK) {
626 error_setg(errp, "Hot-unplug failed: "
627 "guest is busy (power indicator blinking)");
628 return;
629 }
630
631 if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
632 shpc_free_devices_in_slot(shpc, slot);
633 shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
634 shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
635 SHPC_SLOT_STATUS_PRSNT_MASK);
636 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
637 SHPC_SLOT_EVENT_MRL |
638 SHPC_SLOT_EVENT_PRESENCE;
639 } else {
640 shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
641 }
642 shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
643 shpc_interrupt_update(pci_hotplug_dev);
644 }
645
646 /* Initialize the SHPC structure in bridge's BAR. */
shpc_init(PCIDevice * d,PCIBus * sec_bus,MemoryRegion * bar,unsigned offset,Error ** errp)647 int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar,
648 unsigned offset, Error **errp)
649 {
650 int i, ret;
651 int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
652 SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
653 shpc->sec_bus = sec_bus;
654 ret = shpc_cap_add_config(d, errp);
655 if (ret) {
656 g_free(d->shpc);
657 return ret;
658 }
659 if (nslots < SHPC_MIN_SLOTS) {
660 return 0;
661 }
662 if (nslots > SHPC_MAX_SLOTS ||
663 SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
664 /* TODO: report an error message that makes sense. */
665 return -EINVAL;
666 }
667 shpc->nslots = nslots;
668 shpc->config = g_malloc0(SHPC_SIZEOF(d));
669 shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
670 shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
671 shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
672
673 shpc_reset(d);
674
675 pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
676
677 pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
678 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
679 pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
680 pci_set_long(shpc->wmask + SHPC_SERR_INT,
681 SHPC_INT_DIS |
682 SHPC_SERR_DIS |
683 SHPC_CMD_INT_DIS |
684 SHPC_ARB_SERR_DIS);
685 pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
686 SHPC_CMD_DETECTED |
687 SHPC_ARB_DETECTED);
688 for (i = 0; i < nslots; ++i) {
689 pci_set_byte(shpc->wmask +
690 SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
691 SHPC_SLOT_EVENT_PRESENCE |
692 SHPC_SLOT_EVENT_ISOLATED_FAULT |
693 SHPC_SLOT_EVENT_BUTTON |
694 SHPC_SLOT_EVENT_MRL |
695 SHPC_SLOT_EVENT_CONNECTED_FAULT |
696 SHPC_SLOT_EVENT_MRL_SERR_DIS |
697 SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
698 pci_set_byte(shpc->w1cmask +
699 SHPC_SLOT_EVENT_LATCH(i),
700 SHPC_SLOT_EVENT_PRESENCE |
701 SHPC_SLOT_EVENT_ISOLATED_FAULT |
702 SHPC_SLOT_EVENT_BUTTON |
703 SHPC_SLOT_EVENT_MRL |
704 SHPC_SLOT_EVENT_CONNECTED_FAULT);
705 }
706
707 /* TODO: init cmask */
708 memory_region_init_io(&shpc->mmio, OBJECT(d), &shpc_mmio_ops,
709 d, "shpc-mmio", SHPC_SIZEOF(d));
710 shpc_cap_update_dword(d);
711 memory_region_add_subregion(bar, offset, &shpc->mmio);
712
713 qbus_set_hotplug_handler(BUS(sec_bus), OBJECT(d));
714
715 d->cap_present |= QEMU_PCI_CAP_SHPC;
716 return 0;
717 }
718
shpc_bar_size(PCIDevice * d)719 int shpc_bar_size(PCIDevice *d)
720 {
721 return pow2roundup32(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
722 }
723
shpc_cleanup(PCIDevice * d,MemoryRegion * bar)724 void shpc_cleanup(PCIDevice *d, MemoryRegion *bar)
725 {
726 SHPCDevice *shpc = d->shpc;
727 d->cap_present &= ~QEMU_PCI_CAP_SHPC;
728 memory_region_del_subregion(bar, &shpc->mmio);
729 /* TODO: cleanup config space changes? */
730 }
731
shpc_free(PCIDevice * d)732 void shpc_free(PCIDevice *d)
733 {
734 SHPCDevice *shpc = d->shpc;
735 if (!shpc) {
736 return;
737 }
738 object_unparent(OBJECT(&shpc->mmio));
739 g_free(shpc->config);
740 g_free(shpc->cmask);
741 g_free(shpc->wmask);
742 g_free(shpc->w1cmask);
743 g_free(shpc);
744 d->shpc = NULL;
745 }
746
shpc_cap_write_config(PCIDevice * d,uint32_t addr,uint32_t val,int l)747 void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
748 {
749 if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
750 return;
751 }
752 if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
753 unsigned dword_data;
754 dword_data = pci_get_long(d->shpc->config + d->shpc->cap
755 + SHPC_CAP_DWORD_DATA);
756 shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
757 }
758 /* Update cap dword data in case guest is going to read it. */
759 shpc_cap_update_dword(d);
760 }
761
shpc_save(QEMUFile * f,void * pv,size_t size,const VMStateField * field,JSONWriter * vmdesc)762 static int shpc_save(QEMUFile *f, void *pv, size_t size,
763 const VMStateField *field, JSONWriter *vmdesc)
764 {
765 PCIDevice *d = container_of(pv, PCIDevice, shpc);
766 qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
767
768 return 0;
769 }
770
shpc_load(QEMUFile * f,void * pv,size_t size,const VMStateField * field)771 static int shpc_load(QEMUFile *f, void *pv, size_t size,
772 const VMStateField *field)
773 {
774 PCIDevice *d = container_of(pv, PCIDevice, shpc);
775 int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
776 if (ret != SHPC_SIZEOF(d)) {
777 return -EINVAL;
778 }
779 /* Make sure we don't lose notifications. An extra interrupt is harmless. */
780 d->shpc->msi_requested = 0;
781 shpc_interrupt_update(d);
782 return 0;
783 }
784
785 const VMStateInfo shpc_vmstate_info = {
786 .name = "shpc",
787 .get = shpc_load,
788 .put = shpc_save,
789 };
790