1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/range.h" 19 #include "qapi/error.h" 20 #include "trace.h" 21 22 static GHashTable *pfs; 23 24 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 25 { 26 for (uint16_t i = 0; i < total_vfs; i++) { 27 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 28 object_unparent(OBJECT(vf)); 29 object_unref(OBJECT(vf)); 30 } 31 g_free(dev->exp.sriov_pf.vf); 32 dev->exp.sriov_pf.vf = NULL; 33 } 34 35 static void register_vfs(PCIDevice *dev) 36 { 37 uint16_t num_vfs; 38 uint16_t i; 39 uint16_t sriov_cap = dev->exp.sriov_cap; 40 41 assert(sriov_cap > 0); 42 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 43 44 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 45 PCI_FUNC(dev->devfn), num_vfs); 46 for (i = 0; i < num_vfs; i++) { 47 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 48 } 49 50 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0); 51 } 52 53 static void unregister_vfs(PCIDevice *dev) 54 { 55 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 56 uint16_t i; 57 58 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 59 PCI_FUNC(dev->devfn)); 60 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 61 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 62 } 63 64 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff); 65 } 66 67 static void consume_config(PCIDevice *dev) 68 { 69 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 70 71 if (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) { 72 register_vfs(dev); 73 } else { 74 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 75 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF); 76 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI; 77 78 unregister_vfs(dev); 79 80 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) { 81 wmask_val |= PCI_SRIOV_CTRL_VFE; 82 } 83 84 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val); 85 } 86 } 87 88 static bool pcie_sriov_pf_init_common(PCIDevice *dev, uint16_t offset, 89 uint16_t vf_dev_id, uint16_t init_vfs, 90 uint16_t total_vfs, uint16_t vf_offset, 91 uint16_t vf_stride, Error **errp) 92 { 93 int32_t devfn = dev->devfn + vf_offset; 94 uint8_t *cfg = dev->config + offset; 95 uint8_t *wmask; 96 97 if (!pci_is_express(dev)) { 98 error_setg(errp, "PCI Express is required for SR-IOV PF"); 99 return false; 100 } 101 102 if (pci_is_vf(dev)) { 103 error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the same time"); 104 return false; 105 } 106 107 if (total_vfs && 108 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) { 109 error_setg(errp, "VF addr overflows"); 110 return false; 111 } 112 113 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 114 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 115 dev->exp.sriov_cap = offset; 116 dev->exp.sriov_pf.vf = NULL; 117 118 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 119 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 120 121 /* 122 * Mandatory page sizes to support. 123 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 124 * to set more bits: 125 */ 126 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 127 128 /* 129 * Default is to use 4K pages, software can modify it 130 * to any of the supported bits 131 */ 132 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 133 134 /* Set up device ID and initial/total number of VFs available */ 135 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 136 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 137 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 138 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 139 140 /* Write enable control bits */ 141 wmask = dev->wmask + offset; 142 pci_set_word(wmask + PCI_SRIOV_CTRL, 143 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 144 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 145 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 146 147 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 148 149 return true; 150 } 151 152 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 153 const char *vfname, uint16_t vf_dev_id, 154 uint16_t init_vfs, uint16_t total_vfs, 155 uint16_t vf_offset, uint16_t vf_stride, 156 Error **errp) 157 { 158 BusState *bus = qdev_get_parent_bus(&dev->qdev); 159 int32_t devfn = dev->devfn + vf_offset; 160 161 if (pfs && g_hash_table_contains(pfs, dev->qdev.id)) { 162 error_setg(errp, "attaching user-created SR-IOV VF unsupported"); 163 return false; 164 } 165 166 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, init_vfs, 167 total_vfs, vf_offset, vf_stride, errp)) { 168 return false; 169 } 170 171 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 172 173 for (uint16_t i = 0; i < total_vfs; i++) { 174 PCIDevice *vf = pci_new(devfn, vfname); 175 vf->exp.sriov_vf.pf = dev; 176 vf->exp.sriov_vf.vf_number = i; 177 178 if (!qdev_realize(&vf->qdev, bus, errp)) { 179 object_unparent(OBJECT(vf)); 180 object_unref(vf); 181 unparent_vfs(dev, i); 182 return false; 183 } 184 185 /* set vid/did according to sr/iov spec - they are not used */ 186 pci_config_set_vendor_id(vf->config, 0xffff); 187 pci_config_set_device_id(vf->config, 0xffff); 188 189 dev->exp.sriov_pf.vf[i] = vf; 190 devfn += vf_stride; 191 } 192 193 return true; 194 } 195 196 void pcie_sriov_pf_exit(PCIDevice *dev) 197 { 198 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 199 200 if (dev->exp.sriov_pf.vf_user_created) { 201 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID); 202 uint16_t total_vfs = pci_get_word(dev->config + PCI_SRIOV_TOTAL_VF); 203 uint16_t vf_dev_id = pci_get_word(dev->config + PCI_SRIOV_VF_DID); 204 205 unregister_vfs(dev); 206 207 for (uint16_t i = 0; i < total_vfs; i++) { 208 dev->exp.sriov_pf.vf[i]->exp.sriov_vf.pf = NULL; 209 210 pci_config_set_vendor_id(dev->exp.sriov_pf.vf[i]->config, ven_id); 211 pci_config_set_device_id(dev->exp.sriov_pf.vf[i]->config, vf_dev_id); 212 } 213 } else { 214 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 215 } 216 } 217 218 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 219 uint8_t type, dma_addr_t size) 220 { 221 uint32_t addr; 222 uint64_t wmask; 223 uint16_t sriov_cap = dev->exp.sriov_cap; 224 225 assert(sriov_cap > 0); 226 assert(region_num >= 0); 227 assert(region_num < PCI_NUM_REGIONS); 228 assert(region_num != PCI_ROM_SLOT); 229 230 wmask = ~(size - 1); 231 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 232 233 pci_set_long(dev->config + addr, type); 234 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 235 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 236 pci_set_quad(dev->wmask + addr, wmask); 237 pci_set_quad(dev->cmask + addr, ~0ULL); 238 } else { 239 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 240 pci_set_long(dev->cmask + addr, 0xffffffff); 241 } 242 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 243 } 244 245 static gint compare_vf_devfns(gconstpointer a, gconstpointer b) 246 { 247 return (*(PCIDevice **)a)->devfn - (*(PCIDevice **)b)->devfn; 248 } 249 250 int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev, 251 uint16_t offset, 252 Error **errp) 253 { 254 GPtrArray *pf; 255 PCIDevice **vfs; 256 BusState *bus = qdev_get_parent_bus(DEVICE(dev)); 257 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID); 258 uint16_t size = PCI_EXT_CAP_SRIOV_SIZEOF; 259 uint16_t vf_dev_id; 260 uint16_t vf_offset; 261 uint16_t vf_stride; 262 uint16_t i; 263 264 if (!pfs || !dev->qdev.id) { 265 return 0; 266 } 267 268 pf = g_hash_table_lookup(pfs, dev->qdev.id); 269 if (!pf) { 270 return 0; 271 } 272 273 if (pf->len > UINT16_MAX) { 274 error_setg(errp, "too many VFs"); 275 return -1; 276 } 277 278 g_ptr_array_sort(pf, compare_vf_devfns); 279 vfs = (void *)pf->pdata; 280 281 if (vfs[0]->devfn <= dev->devfn) { 282 error_setg(errp, "a VF function number is less than the PF function number"); 283 return -1; 284 } 285 286 vf_dev_id = pci_get_word(vfs[0]->config + PCI_DEVICE_ID); 287 vf_offset = vfs[0]->devfn - dev->devfn; 288 vf_stride = pf->len < 2 ? 0 : vfs[1]->devfn - vfs[0]->devfn; 289 290 for (i = 0; i < pf->len; i++) { 291 if (bus != qdev_get_parent_bus(&vfs[i]->qdev)) { 292 error_setg(errp, "SR-IOV VF parent bus mismatches with PF"); 293 return -1; 294 } 295 296 if (ven_id != pci_get_word(vfs[i]->config + PCI_VENDOR_ID)) { 297 error_setg(errp, "SR-IOV VF vendor ID mismatches with PF"); 298 return -1; 299 } 300 301 if (vf_dev_id != pci_get_word(vfs[i]->config + PCI_DEVICE_ID)) { 302 error_setg(errp, "inconsistent SR-IOV VF device IDs"); 303 return -1; 304 } 305 306 for (size_t j = 0; j < PCI_NUM_REGIONS; j++) { 307 if (vfs[i]->io_regions[j].size != vfs[0]->io_regions[j].size || 308 vfs[i]->io_regions[j].type != vfs[0]->io_regions[j].type) { 309 error_setg(errp, "inconsistent SR-IOV BARs"); 310 return -1; 311 } 312 } 313 314 if (vfs[i]->devfn - vfs[0]->devfn != vf_stride * i) { 315 error_setg(errp, "inconsistent SR-IOV stride"); 316 return -1; 317 } 318 } 319 320 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, pf->len, 321 pf->len, vf_offset, vf_stride, errp)) { 322 return -1; 323 } 324 325 if (!pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI)) { 326 pcie_ari_init(dev, offset + size); 327 size += PCI_ARI_SIZEOF; 328 } 329 330 for (i = 0; i < pf->len; i++) { 331 vfs[i]->exp.sriov_vf.pf = dev; 332 vfs[i]->exp.sriov_vf.vf_number = i; 333 334 /* set vid/did according to sr/iov spec - they are not used */ 335 pci_config_set_vendor_id(vfs[i]->config, 0xffff); 336 pci_config_set_device_id(vfs[i]->config, 0xffff); 337 } 338 339 dev->exp.sriov_pf.vf = vfs; 340 dev->exp.sriov_pf.vf_user_created = true; 341 342 for (i = 0; i < PCI_NUM_REGIONS; i++) { 343 PCIIORegion *region = &vfs[0]->io_regions[i]; 344 345 if (region->size) { 346 pcie_sriov_pf_init_vf_bar(dev, i, region->type, region->size); 347 } 348 } 349 350 return size; 351 } 352 353 bool pcie_sriov_register_device(PCIDevice *dev, Error **errp) 354 { 355 if (!dev->exp.sriov_pf.vf && dev->qdev.id && 356 pfs && g_hash_table_contains(pfs, dev->qdev.id)) { 357 error_setg(errp, "attaching user-created SR-IOV VF unsupported"); 358 return false; 359 } 360 361 if (dev->sriov_pf) { 362 PCIDevice *pci_pf; 363 GPtrArray *pf; 364 365 if (!PCI_DEVICE_GET_CLASS(dev)->sriov_vf_user_creatable) { 366 error_setg(errp, "user cannot create SR-IOV VF with this device type"); 367 return false; 368 } 369 370 if (!pci_is_express(dev)) { 371 error_setg(errp, "PCI Express is required for SR-IOV VF"); 372 return false; 373 } 374 375 if (!pci_qdev_find_device(dev->sriov_pf, &pci_pf)) { 376 error_setg(errp, "PCI device specified as SR-IOV PF already exists"); 377 return false; 378 } 379 380 if (!pfs) { 381 pfs = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, NULL); 382 } 383 384 pf = g_hash_table_lookup(pfs, dev->sriov_pf); 385 if (!pf) { 386 pf = g_ptr_array_new(); 387 g_hash_table_insert(pfs, g_strdup(dev->sriov_pf), pf); 388 } 389 390 g_ptr_array_add(pf, dev); 391 } 392 393 return true; 394 } 395 396 void pcie_sriov_unregister_device(PCIDevice *dev) 397 { 398 if (dev->sriov_pf && pfs) { 399 GPtrArray *pf = g_hash_table_lookup(pfs, dev->sriov_pf); 400 401 if (pf) { 402 g_ptr_array_remove_fast(pf, dev); 403 404 if (!pf->len) { 405 g_hash_table_remove(pfs, dev->sriov_pf); 406 g_ptr_array_free(pf, FALSE); 407 } 408 } 409 } 410 } 411 412 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 413 uint32_t val, int len) 414 { 415 uint32_t off; 416 uint16_t sriov_cap = dev->exp.sriov_cap; 417 418 if (!sriov_cap || address < sriov_cap) { 419 return; 420 } 421 off = address - sriov_cap; 422 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 423 return; 424 } 425 426 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 427 PCI_FUNC(dev->devfn), off, val, len); 428 429 consume_config(dev); 430 } 431 432 void pcie_sriov_pf_post_load(PCIDevice *dev) 433 { 434 if (dev->exp.sriov_cap) { 435 consume_config(dev); 436 } 437 } 438 439 440 /* Reset SR/IOV */ 441 void pcie_sriov_pf_reset(PCIDevice *dev) 442 { 443 uint16_t sriov_cap = dev->exp.sriov_cap; 444 if (!sriov_cap) { 445 return; 446 } 447 448 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 449 unregister_vfs(dev); 450 451 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 452 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL, 453 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 454 455 /* 456 * Default is to use 4K pages, software can modify it 457 * to any of the supported bits 458 */ 459 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 460 461 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 462 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 463 dev->exp.sriov_pf.vf_bar_type[i]); 464 } 465 } 466 467 /* Add optional supported page sizes to the mask of supported page sizes */ 468 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 469 { 470 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 471 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 472 473 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 474 475 sup_pgsize |= opt_sup_pgsize; 476 477 /* 478 * Make sure the new bits are set, and that system page size 479 * also can be set to any of the new values according to spec: 480 */ 481 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 482 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 483 } 484 485 486 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 487 { 488 assert(dev->exp.sriov_vf.pf); 489 return dev->exp.sriov_vf.vf_number; 490 } 491 492 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 493 { 494 return dev->exp.sriov_vf.pf; 495 } 496 497 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 498 { 499 assert(!pci_is_vf(dev)); 500 if (n < pcie_sriov_num_vfs(dev)) { 501 return dev->exp.sriov_pf.vf[n]; 502 } 503 return NULL; 504 } 505 506 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 507 { 508 uint16_t sriov_cap = dev->exp.sriov_cap; 509 uint8_t *cfg = dev->config + sriov_cap; 510 511 return sriov_cap && 512 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 513 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 514 } 515