1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (total_vfs) { 46 uint16_t ari_cap = pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI); 47 uint16_t first_vf_devfn = dev->devfn + vf_offset; 48 uint16_t last_vf_devfn = first_vf_devfn + vf_stride * (total_vfs - 1); 49 50 if ((!ari_cap && PCI_SLOT(dev->devfn) != PCI_SLOT(last_vf_devfn)) || 51 last_vf_devfn >= PCI_DEVFN_MAX) { 52 error_setg(errp, "VF function number overflows"); 53 return false; 54 } 55 } 56 57 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 58 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 59 dev->exp.sriov_cap = offset; 60 dev->exp.sriov_pf.vf = NULL; 61 62 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 63 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 64 65 /* 66 * Mandatory page sizes to support. 67 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 68 * to set more bits: 69 */ 70 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 71 72 /* 73 * Default is to use 4K pages, software can modify it 74 * to any of the supported bits 75 */ 76 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 77 78 /* Set up device ID and initial/total number of VFs available */ 79 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 80 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 81 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 82 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 83 84 /* Write enable control bits */ 85 wmask = dev->wmask + offset; 86 pci_set_word(wmask + PCI_SRIOV_CTRL, 87 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 88 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 89 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 90 91 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 92 93 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 94 95 for (uint16_t i = 0; i < total_vfs; i++) { 96 PCIDevice *vf = pci_new(devfn, vfname); 97 vf->exp.sriov_vf.pf = dev; 98 vf->exp.sriov_vf.vf_number = i; 99 100 if (!qdev_realize(&vf->qdev, bus, errp)) { 101 object_unparent(OBJECT(vf)); 102 object_unref(vf); 103 unparent_vfs(dev, i); 104 return false; 105 } 106 107 /* set vid/did according to sr/iov spec - they are not used */ 108 pci_config_set_vendor_id(vf->config, 0xffff); 109 pci_config_set_device_id(vf->config, 0xffff); 110 111 dev->exp.sriov_pf.vf[i] = vf; 112 devfn += vf_stride; 113 } 114 115 return true; 116 } 117 118 void pcie_sriov_pf_exit(PCIDevice *dev) 119 { 120 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 121 122 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 123 } 124 125 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 126 uint8_t type, dma_addr_t size) 127 { 128 uint32_t addr; 129 uint64_t wmask; 130 uint16_t sriov_cap = dev->exp.sriov_cap; 131 132 assert(sriov_cap > 0); 133 assert(region_num >= 0); 134 assert(region_num < PCI_NUM_REGIONS); 135 assert(region_num != PCI_ROM_SLOT); 136 137 wmask = ~(size - 1); 138 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 139 140 pci_set_long(dev->config + addr, type); 141 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 142 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 143 pci_set_quad(dev->wmask + addr, wmask); 144 pci_set_quad(dev->cmask + addr, ~0ULL); 145 } else { 146 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 147 pci_set_long(dev->cmask + addr, 0xffffffff); 148 } 149 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 150 } 151 152 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 153 MemoryRegion *memory) 154 { 155 PCIIORegion *r; 156 PCIBus *bus = pci_get_bus(dev); 157 uint8_t type; 158 pcibus_t size = memory_region_size(memory); 159 160 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 161 assert(region_num >= 0); 162 assert(region_num < PCI_NUM_REGIONS); 163 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 164 165 if (!is_power_of_2(size)) { 166 error_report("%s: PCI region size must be a power" 167 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 168 __func__, type, size); 169 exit(1); 170 } 171 172 r = &dev->io_regions[region_num]; 173 r->memory = memory; 174 r->address_space = 175 type & PCI_BASE_ADDRESS_SPACE_IO 176 ? bus->address_space_io 177 : bus->address_space_mem; 178 r->size = size; 179 r->type = type; 180 181 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 182 if (r->addr != PCI_BAR_UNMAPPED) { 183 memory_region_add_subregion_overlap(r->address_space, 184 r->addr, r->memory, 1); 185 } 186 } 187 188 static void clear_ctrl_vfe(PCIDevice *dev) 189 { 190 uint8_t *ctrl = dev->config + dev->exp.sriov_cap + PCI_SRIOV_CTRL; 191 pci_set_word(ctrl, pci_get_word(ctrl) & ~PCI_SRIOV_CTRL_VFE); 192 } 193 194 static void register_vfs(PCIDevice *dev) 195 { 196 uint16_t num_vfs; 197 uint16_t i; 198 uint16_t sriov_cap = dev->exp.sriov_cap; 199 200 assert(sriov_cap > 0); 201 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 202 if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_VF)) { 203 clear_ctrl_vfe(dev); 204 return; 205 } 206 207 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 208 PCI_FUNC(dev->devfn), num_vfs); 209 for (i = 0; i < num_vfs; i++) { 210 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 211 } 212 } 213 214 static void unregister_vfs(PCIDevice *dev) 215 { 216 uint16_t i; 217 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 218 219 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 220 PCI_FUNC(dev->devfn)); 221 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 222 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 223 } 224 } 225 226 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 227 uint32_t val, int len) 228 { 229 uint32_t off; 230 uint16_t sriov_cap = dev->exp.sriov_cap; 231 232 if (!sriov_cap || address < sriov_cap) { 233 return; 234 } 235 off = address - sriov_cap; 236 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 237 return; 238 } 239 240 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 241 PCI_FUNC(dev->devfn), off, val, len); 242 243 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 244 if (val & PCI_SRIOV_CTRL_VFE) { 245 register_vfs(dev); 246 } else { 247 unregister_vfs(dev); 248 } 249 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 250 clear_ctrl_vfe(dev); 251 unregister_vfs(dev); 252 } 253 } 254 255 void pcie_sriov_pf_post_load(PCIDevice *dev) 256 { 257 if (dev->exp.sriov_cap) { 258 register_vfs(dev); 259 } 260 } 261 262 263 /* Reset SR/IOV */ 264 void pcie_sriov_pf_reset(PCIDevice *dev) 265 { 266 uint16_t sriov_cap = dev->exp.sriov_cap; 267 if (!sriov_cap) { 268 return; 269 } 270 271 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 272 unregister_vfs(dev); 273 274 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 275 276 /* 277 * Default is to use 4K pages, software can modify it 278 * to any of the supported bits 279 */ 280 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 281 282 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 283 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 284 dev->exp.sriov_pf.vf_bar_type[i]); 285 } 286 } 287 288 /* Add optional supported page sizes to the mask of supported page sizes */ 289 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 290 { 291 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 292 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 293 294 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 295 296 sup_pgsize |= opt_sup_pgsize; 297 298 /* 299 * Make sure the new bits are set, and that system page size 300 * also can be set to any of the new values according to spec: 301 */ 302 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 303 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 304 } 305 306 307 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 308 { 309 assert(pci_is_vf(dev)); 310 return dev->exp.sriov_vf.vf_number; 311 } 312 313 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 314 { 315 return dev->exp.sriov_vf.pf; 316 } 317 318 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 319 { 320 assert(!pci_is_vf(dev)); 321 if (n < pcie_sriov_num_vfs(dev)) { 322 return dev->exp.sriov_pf.vf[n]; 323 } 324 return NULL; 325 } 326 327 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 328 { 329 uint16_t sriov_cap = dev->exp.sriov_cap; 330 uint8_t *cfg = dev->config + sriov_cap; 331 332 return sriov_cap && 333 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 334 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 335 } 336