1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 24 { 25 for (uint16_t i = 0; i < total_vfs; i++) { 26 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 27 object_unparent(OBJECT(vf)); 28 object_unref(OBJECT(vf)); 29 } 30 g_free(dev->exp.sriov_pf.vf); 31 dev->exp.sriov_pf.vf = NULL; 32 } 33 34 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 35 const char *vfname, uint16_t vf_dev_id, 36 uint16_t init_vfs, uint16_t total_vfs, 37 uint16_t vf_offset, uint16_t vf_stride, 38 Error **errp) 39 { 40 BusState *bus = qdev_get_parent_bus(&dev->qdev); 41 int32_t devfn = dev->devfn + vf_offset; 42 uint8_t *cfg = dev->config + offset; 43 uint8_t *wmask; 44 45 if (pci_is_vf(dev)) { 46 error_setg(errp, "a device cannot be a SR-IOV PF and a VF at the same time"); 47 return false; 48 } 49 50 if (total_vfs && 51 (uint32_t)devfn + (uint32_t)(total_vfs - 1) * vf_stride >= PCI_DEVFN_MAX) { 52 error_setg(errp, "VF addr overflows"); 53 return false; 54 } 55 56 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 57 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 58 dev->exp.sriov_cap = offset; 59 dev->exp.sriov_pf.vf = NULL; 60 61 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 62 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 63 64 /* 65 * Mandatory page sizes to support. 66 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 67 * to set more bits: 68 */ 69 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 70 71 /* 72 * Default is to use 4K pages, software can modify it 73 * to any of the supported bits 74 */ 75 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 76 77 /* Set up device ID and initial/total number of VFs available */ 78 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 79 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 80 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 81 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 82 83 /* Write enable control bits */ 84 wmask = dev->wmask + offset; 85 pci_set_word(wmask + PCI_SRIOV_CTRL, 86 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 87 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 88 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 89 90 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 91 92 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 93 94 for (uint16_t i = 0; i < total_vfs; i++) { 95 PCIDevice *vf = pci_new(devfn, vfname); 96 vf->exp.sriov_vf.pf = dev; 97 vf->exp.sriov_vf.vf_number = i; 98 99 if (!qdev_realize(&vf->qdev, bus, errp)) { 100 object_unparent(OBJECT(vf)); 101 object_unref(vf); 102 unparent_vfs(dev, i); 103 return false; 104 } 105 106 /* set vid/did according to sr/iov spec - they are not used */ 107 pci_config_set_vendor_id(vf->config, 0xffff); 108 pci_config_set_device_id(vf->config, 0xffff); 109 110 dev->exp.sriov_pf.vf[i] = vf; 111 devfn += vf_stride; 112 } 113 114 return true; 115 } 116 117 void pcie_sriov_pf_exit(PCIDevice *dev) 118 { 119 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 120 121 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 122 } 123 124 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 125 uint8_t type, dma_addr_t size) 126 { 127 uint32_t addr; 128 uint64_t wmask; 129 uint16_t sriov_cap = dev->exp.sriov_cap; 130 131 assert(sriov_cap > 0); 132 assert(region_num >= 0); 133 assert(region_num < PCI_NUM_REGIONS); 134 assert(region_num != PCI_ROM_SLOT); 135 136 wmask = ~(size - 1); 137 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 138 139 pci_set_long(dev->config + addr, type); 140 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 141 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 142 pci_set_quad(dev->wmask + addr, wmask); 143 pci_set_quad(dev->cmask + addr, ~0ULL); 144 } else { 145 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 146 pci_set_long(dev->cmask + addr, 0xffffffff); 147 } 148 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 149 } 150 151 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 152 MemoryRegion *memory) 153 { 154 PCIIORegion *r; 155 PCIBus *bus = pci_get_bus(dev); 156 uint8_t type; 157 pcibus_t size = memory_region_size(memory); 158 159 assert(pci_is_vf(dev)); /* PFs must use pci_register_bar */ 160 assert(region_num >= 0); 161 assert(region_num < PCI_NUM_REGIONS); 162 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 163 164 if (!is_power_of_2(size)) { 165 error_report("%s: PCI region size must be a power" 166 " of two - type=0x%x, size=0x%"FMT_PCIBUS, 167 __func__, type, size); 168 exit(1); 169 } 170 171 r = &dev->io_regions[region_num]; 172 r->memory = memory; 173 r->address_space = 174 type & PCI_BASE_ADDRESS_SPACE_IO 175 ? bus->address_space_io 176 : bus->address_space_mem; 177 r->size = size; 178 r->type = type; 179 180 r->addr = pci_bar_address(dev, region_num, r->type, r->size); 181 if (r->addr != PCI_BAR_UNMAPPED) { 182 memory_region_add_subregion_overlap(r->address_space, 183 r->addr, r->memory, 1); 184 } 185 } 186 187 static void register_vfs(PCIDevice *dev) 188 { 189 uint16_t num_vfs; 190 uint16_t i; 191 uint16_t sriov_cap = dev->exp.sriov_cap; 192 193 assert(sriov_cap > 0); 194 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 195 196 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 197 PCI_FUNC(dev->devfn), num_vfs); 198 for (i = 0; i < num_vfs; i++) { 199 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 200 } 201 202 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_NUM_VF, 0); 203 } 204 205 static void unregister_vfs(PCIDevice *dev) 206 { 207 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 208 uint16_t i; 209 210 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 211 PCI_FUNC(dev->devfn)); 212 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 213 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 214 } 215 216 pci_set_word(dev->wmask + dev->exp.sriov_cap + PCI_SRIOV_NUM_VF, 0xffff); 217 } 218 219 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 220 uint32_t val, int len) 221 { 222 uint32_t off; 223 uint16_t sriov_cap = dev->exp.sriov_cap; 224 225 if (!sriov_cap || address < sriov_cap) { 226 return; 227 } 228 off = address - sriov_cap; 229 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 230 return; 231 } 232 233 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 234 PCI_FUNC(dev->devfn), off, val, len); 235 236 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 237 if (val & PCI_SRIOV_CTRL_VFE) { 238 register_vfs(dev); 239 } else { 240 unregister_vfs(dev); 241 } 242 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 243 uint8_t *cfg = dev->config + sriov_cap; 244 uint8_t *wmask = dev->wmask + sriov_cap; 245 uint16_t num_vfs = pci_get_word(cfg + PCI_SRIOV_NUM_VF); 246 uint16_t wmask_val = PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI; 247 248 if (num_vfs <= pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)) { 249 wmask_val |= PCI_SRIOV_CTRL_VFE; 250 } 251 252 pci_set_word(wmask + PCI_SRIOV_CTRL, wmask_val); 253 } 254 } 255 256 void pcie_sriov_pf_post_load(PCIDevice *dev) 257 { 258 if (dev->exp.sriov_cap) { 259 register_vfs(dev); 260 } 261 } 262 263 264 /* Reset SR/IOV */ 265 void pcie_sriov_pf_reset(PCIDevice *dev) 266 { 267 uint16_t sriov_cap = dev->exp.sriov_cap; 268 if (!sriov_cap) { 269 return; 270 } 271 272 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 273 unregister_vfs(dev); 274 275 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 276 pci_set_word(dev->wmask + sriov_cap + PCI_SRIOV_CTRL, 277 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 278 279 /* 280 * Default is to use 4K pages, software can modify it 281 * to any of the supported bits 282 */ 283 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 284 285 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 286 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 287 dev->exp.sriov_pf.vf_bar_type[i]); 288 } 289 } 290 291 /* Add optional supported page sizes to the mask of supported page sizes */ 292 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 293 { 294 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 295 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 296 297 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 298 299 sup_pgsize |= opt_sup_pgsize; 300 301 /* 302 * Make sure the new bits are set, and that system page size 303 * also can be set to any of the new values according to spec: 304 */ 305 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 306 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 307 } 308 309 310 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 311 { 312 assert(pci_is_vf(dev)); 313 return dev->exp.sriov_vf.vf_number; 314 } 315 316 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 317 { 318 return dev->exp.sriov_vf.pf; 319 } 320 321 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 322 { 323 assert(!pci_is_vf(dev)); 324 if (n < pcie_sriov_num_vfs(dev)) { 325 return dev->exp.sriov_pf.vf[n]; 326 } 327 return NULL; 328 } 329 330 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 331 { 332 uint16_t sriov_cap = dev->exp.sriov_cap; 333 uint8_t *cfg = dev->config + sriov_cap; 334 335 return sriov_cap && 336 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 337 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 338 } 339