1 /* 2 * pcie_sriov.c: 3 * 4 * Implementation of SR/IOV emulation support. 5 * 6 * Copyright (c) 2015-2017 Knut Omang <knut.omang@oracle.com> 7 * 8 * This work is licensed under the terms of the GNU GPL, version 2 or later. 9 * See the COPYING file in the top-level directory. 10 * 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/pci/pcie.h" 16 #include "hw/pci/pci_bus.h" 17 #include "hw/qdev-properties.h" 18 #include "qemu/error-report.h" 19 #include "qemu/range.h" 20 #include "qapi/error.h" 21 #include "trace.h" 22 23 static GHashTable *pfs; 24 25 static void unparent_vfs(PCIDevice *dev, uint16_t total_vfs) 26 { 27 for (uint16_t i = 0; i < total_vfs; i++) { 28 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 29 object_unparent(OBJECT(vf)); 30 object_unref(OBJECT(vf)); 31 } 32 g_free(dev->exp.sriov_pf.vf); 33 dev->exp.sriov_pf.vf = NULL; 34 } 35 36 static void clear_ctrl_vfe(PCIDevice *dev) 37 { 38 uint8_t *ctrl = dev->config + dev->exp.sriov_cap + PCI_SRIOV_CTRL; 39 pci_set_word(ctrl, pci_get_word(ctrl) & ~PCI_SRIOV_CTRL_VFE); 40 } 41 42 static void register_vfs(PCIDevice *dev) 43 { 44 uint16_t num_vfs; 45 uint16_t i; 46 uint16_t sriov_cap = dev->exp.sriov_cap; 47 48 assert(sriov_cap > 0); 49 num_vfs = pci_get_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF); 50 if (num_vfs > pci_get_word(dev->config + sriov_cap + PCI_SRIOV_TOTAL_VF)) { 51 clear_ctrl_vfe(dev); 52 return; 53 } 54 55 trace_sriov_register_vfs(dev->name, PCI_SLOT(dev->devfn), 56 PCI_FUNC(dev->devfn), num_vfs); 57 for (i = 0; i < num_vfs; i++) { 58 pci_set_enabled(dev->exp.sriov_pf.vf[i], true); 59 } 60 } 61 62 static void unregister_vfs(PCIDevice *dev) 63 { 64 uint16_t i; 65 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 66 67 trace_sriov_unregister_vfs(dev->name, PCI_SLOT(dev->devfn), 68 PCI_FUNC(dev->devfn)); 69 for (i = 0; i < pci_get_word(cfg + PCI_SRIOV_TOTAL_VF); i++) { 70 pci_set_enabled(dev->exp.sriov_pf.vf[i], false); 71 } 72 } 73 74 static bool pcie_sriov_pf_init_common(PCIDevice *dev, uint16_t offset, 75 uint16_t vf_dev_id, uint16_t init_vfs, 76 uint16_t total_vfs, uint16_t vf_offset, 77 uint16_t vf_stride, Error **errp) 78 { 79 uint8_t *cfg = dev->config + offset; 80 uint8_t *wmask; 81 82 if (!pci_is_express(dev)) { 83 error_setg(errp, "PCI Express is required for SR-IOV PF"); 84 return false; 85 } 86 87 if (pci_is_vf(dev)) { 88 error_setg(errp, "a device cannot be both an SR-IOV PF and a VF"); 89 return false; 90 } 91 92 if (total_vfs) { 93 uint16_t ari_cap = pcie_find_capability(dev, PCI_EXT_CAP_ID_ARI); 94 uint16_t first_vf_devfn = dev->devfn + vf_offset; 95 uint16_t last_vf_devfn = first_vf_devfn + vf_stride * (total_vfs - 1); 96 97 if ((!ari_cap && PCI_SLOT(dev->devfn) != PCI_SLOT(last_vf_devfn)) || 98 last_vf_devfn >= PCI_DEVFN_MAX) { 99 error_setg(errp, "VF function number overflows"); 100 return false; 101 } 102 } 103 104 pcie_add_capability(dev, PCI_EXT_CAP_ID_SRIOV, 1, 105 offset, PCI_EXT_CAP_SRIOV_SIZEOF); 106 dev->exp.sriov_cap = offset; 107 dev->exp.sriov_pf.vf = NULL; 108 109 pci_set_word(cfg + PCI_SRIOV_VF_OFFSET, vf_offset); 110 pci_set_word(cfg + PCI_SRIOV_VF_STRIDE, vf_stride); 111 112 /* 113 * Mandatory page sizes to support. 114 * Device implementations can call pcie_sriov_pf_add_sup_pgsize() 115 * to set more bits: 116 */ 117 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, SRIOV_SUP_PGSIZE_MINREQ); 118 119 /* 120 * Default is to use 4K pages, software can modify it 121 * to any of the supported bits 122 */ 123 pci_set_word(cfg + PCI_SRIOV_SYS_PGSIZE, 0x1); 124 125 /* Set up device ID and initial/total number of VFs available */ 126 pci_set_word(cfg + PCI_SRIOV_VF_DID, vf_dev_id); 127 pci_set_word(cfg + PCI_SRIOV_INITIAL_VF, init_vfs); 128 pci_set_word(cfg + PCI_SRIOV_TOTAL_VF, total_vfs); 129 pci_set_word(cfg + PCI_SRIOV_NUM_VF, 0); 130 131 /* Write enable control bits */ 132 wmask = dev->wmask + offset; 133 pci_set_word(wmask + PCI_SRIOV_CTRL, 134 PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE | PCI_SRIOV_CTRL_ARI); 135 pci_set_word(wmask + PCI_SRIOV_NUM_VF, 0xffff); 136 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, 0x553); 137 138 qdev_prop_set_bit(&dev->qdev, "multifunction", true); 139 140 return true; 141 } 142 143 bool pcie_sriov_pf_init(PCIDevice *dev, uint16_t offset, 144 const char *vfname, uint16_t vf_dev_id, 145 uint16_t init_vfs, uint16_t total_vfs, 146 uint16_t vf_offset, uint16_t vf_stride, 147 Error **errp) 148 { 149 BusState *bus = qdev_get_parent_bus(&dev->qdev); 150 int32_t devfn = dev->devfn + vf_offset; 151 152 if (pfs && g_hash_table_contains(pfs, dev->qdev.id)) { 153 error_setg(errp, "attaching user-created SR-IOV VF unsupported"); 154 return false; 155 } 156 157 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, init_vfs, 158 total_vfs, vf_offset, vf_stride, errp)) { 159 return false; 160 } 161 162 dev->exp.sriov_pf.vf = g_new(PCIDevice *, total_vfs); 163 164 for (uint16_t i = 0; i < total_vfs; i++) { 165 PCIDevice *vf = pci_new(devfn, vfname); 166 vf->exp.sriov_vf.pf = dev; 167 vf->exp.sriov_vf.vf_number = i; 168 169 if (!qdev_realize(&vf->qdev, bus, errp)) { 170 object_unparent(OBJECT(vf)); 171 object_unref(vf); 172 unparent_vfs(dev, i); 173 return false; 174 } 175 176 /* set vid/did according to sr/iov spec - they are not used */ 177 pci_config_set_vendor_id(vf->config, 0xffff); 178 pci_config_set_device_id(vf->config, 0xffff); 179 180 dev->exp.sriov_pf.vf[i] = vf; 181 devfn += vf_stride; 182 } 183 184 return true; 185 } 186 187 void pcie_sriov_pf_exit(PCIDevice *dev) 188 { 189 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 190 191 if (dev->exp.sriov_pf.vf_user_created) { 192 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID); 193 uint16_t total_vfs = pci_get_word(dev->config + PCI_SRIOV_TOTAL_VF); 194 uint16_t vf_dev_id = pci_get_word(dev->config + PCI_SRIOV_VF_DID); 195 196 unregister_vfs(dev); 197 198 for (uint16_t i = 0; i < total_vfs; i++) { 199 PCIDevice *vf = dev->exp.sriov_pf.vf[i]; 200 201 vf->exp.sriov_vf.pf = NULL; 202 203 pci_config_set_vendor_id(vf->config, ven_id); 204 pci_config_set_device_id(vf->config, vf_dev_id); 205 } 206 } else { 207 unparent_vfs(dev, pci_get_word(cfg + PCI_SRIOV_TOTAL_VF)); 208 } 209 } 210 211 void pcie_sriov_pf_init_vf_bar(PCIDevice *dev, int region_num, 212 uint8_t type, dma_addr_t size) 213 { 214 uint32_t addr; 215 uint64_t wmask; 216 uint16_t sriov_cap = dev->exp.sriov_cap; 217 218 assert(sriov_cap > 0); 219 assert(region_num >= 0); 220 assert(region_num < PCI_NUM_REGIONS); 221 assert(region_num != PCI_ROM_SLOT); 222 223 wmask = ~(size - 1); 224 addr = sriov_cap + PCI_SRIOV_BAR + region_num * 4; 225 226 pci_set_long(dev->config + addr, type); 227 if (!(type & PCI_BASE_ADDRESS_SPACE_IO) && 228 type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 229 pci_set_quad(dev->wmask + addr, wmask); 230 pci_set_quad(dev->cmask + addr, ~0ULL); 231 } else { 232 pci_set_long(dev->wmask + addr, wmask & 0xffffffff); 233 pci_set_long(dev->cmask + addr, 0xffffffff); 234 } 235 dev->exp.sriov_pf.vf_bar_type[region_num] = type; 236 } 237 238 void pcie_sriov_vf_register_bar(PCIDevice *dev, int region_num, 239 MemoryRegion *memory) 240 { 241 uint8_t type; 242 243 assert(dev->exp.sriov_vf.pf); 244 type = dev->exp.sriov_vf.pf->exp.sriov_pf.vf_bar_type[region_num]; 245 246 return pci_register_bar(dev, region_num, type, memory); 247 } 248 249 static gint compare_vf_devfns(gconstpointer a, gconstpointer b) 250 { 251 return (*(PCIDevice **)a)->devfn - (*(PCIDevice **)b)->devfn; 252 } 253 254 int16_t pcie_sriov_pf_init_from_user_created_vfs(PCIDevice *dev, 255 uint16_t offset, 256 Error **errp) 257 { 258 GPtrArray *pf; 259 PCIDevice **vfs; 260 BusState *bus = qdev_get_parent_bus(DEVICE(dev)); 261 uint16_t ven_id = pci_get_word(dev->config + PCI_VENDOR_ID); 262 uint16_t vf_dev_id; 263 uint16_t vf_offset; 264 uint16_t vf_stride; 265 uint16_t i; 266 267 if (!pfs || !dev->qdev.id) { 268 return 0; 269 } 270 271 pf = g_hash_table_lookup(pfs, dev->qdev.id); 272 if (!pf) { 273 return 0; 274 } 275 276 if (pf->len > UINT16_MAX) { 277 error_setg(errp, "too many VFs"); 278 return -1; 279 } 280 281 g_ptr_array_sort(pf, compare_vf_devfns); 282 vfs = (void *)pf->pdata; 283 284 if (vfs[0]->devfn <= dev->devfn) { 285 error_setg(errp, "a VF function number is less than the PF function number"); 286 return -1; 287 } 288 289 vf_dev_id = pci_get_word(vfs[0]->config + PCI_DEVICE_ID); 290 vf_offset = vfs[0]->devfn - dev->devfn; 291 vf_stride = pf->len < 2 ? 0 : vfs[1]->devfn - vfs[0]->devfn; 292 293 for (i = 0; i < pf->len; i++) { 294 if (bus != qdev_get_parent_bus(&vfs[i]->qdev)) { 295 error_setg(errp, "SR-IOV VF parent bus mismatches with PF"); 296 return -1; 297 } 298 299 if (ven_id != pci_get_word(vfs[i]->config + PCI_VENDOR_ID)) { 300 error_setg(errp, "SR-IOV VF vendor ID mismatches with PF"); 301 return -1; 302 } 303 304 if (vf_dev_id != pci_get_word(vfs[i]->config + PCI_DEVICE_ID)) { 305 error_setg(errp, "inconsistent SR-IOV VF device IDs"); 306 return -1; 307 } 308 309 for (size_t j = 0; j < PCI_NUM_REGIONS; j++) { 310 if (vfs[i]->io_regions[j].size != vfs[0]->io_regions[j].size || 311 vfs[i]->io_regions[j].type != vfs[0]->io_regions[j].type) { 312 error_setg(errp, "inconsistent SR-IOV BARs"); 313 return -1; 314 } 315 } 316 317 if (vfs[i]->devfn - vfs[0]->devfn != vf_stride * i) { 318 error_setg(errp, "inconsistent SR-IOV stride"); 319 return -1; 320 } 321 } 322 323 if (!pcie_sriov_pf_init_common(dev, offset, vf_dev_id, pf->len, 324 pf->len, vf_offset, vf_stride, errp)) { 325 return -1; 326 } 327 328 for (i = 0; i < pf->len; i++) { 329 vfs[i]->exp.sriov_vf.pf = dev; 330 vfs[i]->exp.sriov_vf.vf_number = i; 331 332 /* set vid/did according to sr/iov spec - they are not used */ 333 pci_config_set_vendor_id(vfs[i]->config, 0xffff); 334 pci_config_set_device_id(vfs[i]->config, 0xffff); 335 } 336 337 dev->exp.sriov_pf.vf = vfs; 338 dev->exp.sriov_pf.vf_user_created = true; 339 340 for (i = 0; i < PCI_NUM_REGIONS; i++) { 341 PCIIORegion *region = &vfs[0]->io_regions[i]; 342 343 if (region->size) { 344 pcie_sriov_pf_init_vf_bar(dev, i, region->type, region->size); 345 } 346 } 347 348 return PCI_EXT_CAP_SRIOV_SIZEOF; 349 } 350 351 bool pcie_sriov_register_device(PCIDevice *dev, Error **errp) 352 { 353 if (!dev->exp.sriov_pf.vf && dev->qdev.id && 354 pfs && g_hash_table_contains(pfs, dev->qdev.id)) { 355 error_setg(errp, "attaching user-created SR-IOV VF unsupported"); 356 return false; 357 } 358 359 if (dev->sriov_pf) { 360 PCIDevice *pci_pf; 361 GPtrArray *pf; 362 363 if (!PCI_DEVICE_GET_CLASS(dev)->sriov_vf_user_creatable) { 364 error_setg(errp, "user cannot create SR-IOV VF with this device type"); 365 return false; 366 } 367 368 if (!pci_is_express(dev)) { 369 error_setg(errp, "PCI Express is required for SR-IOV VF"); 370 return false; 371 } 372 373 if (!pci_qdev_find_device(dev->sriov_pf, &pci_pf)) { 374 error_setg(errp, "PCI device specified as SR-IOV PF already exists"); 375 return false; 376 } 377 378 if (!pfs) { 379 pfs = g_hash_table_new_full(g_str_hash, g_str_equal, g_free, NULL); 380 } 381 382 pf = g_hash_table_lookup(pfs, dev->sriov_pf); 383 if (!pf) { 384 pf = g_ptr_array_new(); 385 g_hash_table_insert(pfs, g_strdup(dev->sriov_pf), pf); 386 } 387 388 g_ptr_array_add(pf, dev); 389 } 390 391 return true; 392 } 393 394 void pcie_sriov_unregister_device(PCIDevice *dev) 395 { 396 if (dev->sriov_pf && pfs) { 397 GPtrArray *pf = g_hash_table_lookup(pfs, dev->sriov_pf); 398 399 if (pf) { 400 g_ptr_array_remove_fast(pf, dev); 401 402 if (!pf->len) { 403 g_hash_table_remove(pfs, dev->sriov_pf); 404 g_ptr_array_free(pf, FALSE); 405 } 406 } 407 } 408 } 409 410 void pcie_sriov_config_write(PCIDevice *dev, uint32_t address, 411 uint32_t val, int len) 412 { 413 uint32_t off; 414 uint16_t sriov_cap = dev->exp.sriov_cap; 415 416 if (!sriov_cap || address < sriov_cap) { 417 return; 418 } 419 off = address - sriov_cap; 420 if (off >= PCI_EXT_CAP_SRIOV_SIZEOF) { 421 return; 422 } 423 424 trace_sriov_config_write(dev->name, PCI_SLOT(dev->devfn), 425 PCI_FUNC(dev->devfn), off, val, len); 426 427 if (range_covers_byte(off, len, PCI_SRIOV_CTRL)) { 428 if (val & PCI_SRIOV_CTRL_VFE) { 429 register_vfs(dev); 430 } else { 431 unregister_vfs(dev); 432 } 433 } else if (range_covers_byte(off, len, PCI_SRIOV_NUM_VF)) { 434 clear_ctrl_vfe(dev); 435 unregister_vfs(dev); 436 } 437 } 438 439 void pcie_sriov_pf_post_load(PCIDevice *dev) 440 { 441 if (dev->exp.sriov_cap) { 442 register_vfs(dev); 443 } 444 } 445 446 447 /* Reset SR/IOV */ 448 void pcie_sriov_pf_reset(PCIDevice *dev) 449 { 450 uint16_t sriov_cap = dev->exp.sriov_cap; 451 if (!sriov_cap) { 452 return; 453 } 454 455 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_CTRL, 0); 456 unregister_vfs(dev); 457 458 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_NUM_VF, 0); 459 460 /* 461 * Default is to use 4K pages, software can modify it 462 * to any of the supported bits 463 */ 464 pci_set_word(dev->config + sriov_cap + PCI_SRIOV_SYS_PGSIZE, 0x1); 465 466 for (uint16_t i = 0; i < PCI_NUM_REGIONS; i++) { 467 pci_set_quad(dev->config + sriov_cap + PCI_SRIOV_BAR + i * 4, 468 dev->exp.sriov_pf.vf_bar_type[i]); 469 } 470 } 471 472 /* Add optional supported page sizes to the mask of supported page sizes */ 473 void pcie_sriov_pf_add_sup_pgsize(PCIDevice *dev, uint16_t opt_sup_pgsize) 474 { 475 uint8_t *cfg = dev->config + dev->exp.sriov_cap; 476 uint8_t *wmask = dev->wmask + dev->exp.sriov_cap; 477 478 uint16_t sup_pgsize = pci_get_word(cfg + PCI_SRIOV_SUP_PGSIZE); 479 480 sup_pgsize |= opt_sup_pgsize; 481 482 /* 483 * Make sure the new bits are set, and that system page size 484 * also can be set to any of the new values according to spec: 485 */ 486 pci_set_word(cfg + PCI_SRIOV_SUP_PGSIZE, sup_pgsize); 487 pci_set_word(wmask + PCI_SRIOV_SYS_PGSIZE, sup_pgsize); 488 } 489 490 491 uint16_t pcie_sriov_vf_number(PCIDevice *dev) 492 { 493 assert(dev->exp.sriov_vf.pf); 494 return dev->exp.sriov_vf.vf_number; 495 } 496 497 PCIDevice *pcie_sriov_get_pf(PCIDevice *dev) 498 { 499 return dev->exp.sriov_vf.pf; 500 } 501 502 PCIDevice *pcie_sriov_get_vf_at_index(PCIDevice *dev, int n) 503 { 504 assert(!pci_is_vf(dev)); 505 if (n < pcie_sriov_num_vfs(dev)) { 506 return dev->exp.sriov_pf.vf[n]; 507 } 508 return NULL; 509 } 510 511 uint16_t pcie_sriov_num_vfs(PCIDevice *dev) 512 { 513 uint16_t sriov_cap = dev->exp.sriov_cap; 514 uint8_t *cfg = dev->config + sriov_cap; 515 516 return sriov_cap && 517 (pci_get_word(cfg + PCI_SRIOV_CTRL) & PCI_SRIOV_CTRL_VFE) ? 518 pci_get_word(cfg + PCI_SRIOV_NUM_VF) : 0; 519 } 520