1 /* 2 * pcie_port.c 3 * 4 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 5 * VA Linux Systems Japan K.K. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "hw/pci/pcie_port.h" 23 #include "hw/qdev-properties.h" 24 #include "qemu/module.h" 25 #include "hw/hotplug.h" 26 27 void pcie_port_init_reg(PCIDevice *d) 28 { 29 /* Unlike pci bridge, 30 66MHz and fast back to back don't apply to pci express port. */ 31 pci_set_word(d->config + PCI_STATUS, 0); 32 pci_set_word(d->config + PCI_SEC_STATUS, 0); 33 34 /* 35 * Unlike conventional pci bridge, for some bits the spec states: 36 * Does not apply to PCI Express and must be hardwired to 0. 37 */ 38 pci_word_test_and_clear_mask(d->wmask + PCI_BRIDGE_CONTROL, 39 PCI_BRIDGE_CTL_MASTER_ABORT | 40 PCI_BRIDGE_CTL_FAST_BACK | 41 PCI_BRIDGE_CTL_DISCARD | 42 PCI_BRIDGE_CTL_SEC_DISCARD | 43 PCI_BRIDGE_CTL_DISCARD_STATUS | 44 PCI_BRIDGE_CTL_DISCARD_SERR); 45 } 46 47 /************************************************************************** 48 * (chassis number, pcie physical slot number) -> pcie slot conversion 49 */ 50 struct PCIEChassis { 51 uint8_t number; 52 53 QLIST_HEAD(, PCIESlot) slots; 54 QLIST_ENTRY(PCIEChassis) next; 55 }; 56 57 static QLIST_HEAD(, PCIEChassis) chassis = QLIST_HEAD_INITIALIZER(chassis); 58 59 static struct PCIEChassis *pcie_chassis_find(uint8_t chassis_number) 60 { 61 struct PCIEChassis *c; 62 QLIST_FOREACH(c, &chassis, next) { 63 if (c->number == chassis_number) { 64 break; 65 } 66 } 67 return c; 68 } 69 70 void pcie_chassis_create(uint8_t chassis_number) 71 { 72 struct PCIEChassis *c; 73 c = pcie_chassis_find(chassis_number); 74 if (c) { 75 return; 76 } 77 c = g_malloc0(sizeof(*c)); 78 c->number = chassis_number; 79 QLIST_INIT(&c->slots); 80 QLIST_INSERT_HEAD(&chassis, c, next); 81 } 82 83 static PCIESlot *pcie_chassis_find_slot_with_chassis(struct PCIEChassis *c, 84 uint8_t slot) 85 { 86 PCIESlot *s; 87 QLIST_FOREACH(s, &c->slots, next) { 88 if (s->slot == slot) { 89 break; 90 } 91 } 92 return s; 93 } 94 95 int pcie_chassis_add_slot(struct PCIESlot *slot) 96 { 97 struct PCIEChassis *c; 98 c = pcie_chassis_find(slot->chassis); 99 if (!c) { 100 return -ENODEV; 101 } 102 if (pcie_chassis_find_slot_with_chassis(c, slot->slot)) { 103 return -EBUSY; 104 } 105 QLIST_INSERT_HEAD(&c->slots, slot, next); 106 return 0; 107 } 108 109 void pcie_chassis_del_slot(PCIESlot *s) 110 { 111 QLIST_REMOVE(s, next); 112 } 113 114 static Property pcie_port_props[] = { 115 DEFINE_PROP_UINT8("port", PCIEPort, port, 0), 116 DEFINE_PROP_UINT16("aer_log_max", PCIEPort, 117 parent_obj.parent_obj.exp.aer_log.log_max, 118 PCIE_AER_LOG_MAX_DEFAULT), 119 DEFINE_PROP_END_OF_LIST() 120 }; 121 122 static void pcie_port_class_init(ObjectClass *oc, void *data) 123 { 124 DeviceClass *dc = DEVICE_CLASS(oc); 125 126 device_class_set_props(dc, pcie_port_props); 127 } 128 129 PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn) 130 { 131 int devfn; 132 133 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 134 PCIDevice *d = bus->devices[devfn]; 135 PCIEPort *port; 136 137 if (!d || !pci_is_express(d) || !d->exp.exp_cap) { 138 continue; 139 } 140 141 if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { 142 continue; 143 } 144 145 port = PCIE_PORT(d); 146 if (port->port == pn) { 147 return d; 148 } 149 } 150 151 return NULL; 152 } 153 154 /* Find first port in devfn number order */ 155 PCIDevice *pcie_find_port_first(PCIBus *bus) 156 { 157 int devfn; 158 159 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 160 PCIDevice *d = bus->devices[devfn]; 161 162 if (!d || !pci_is_express(d) || !d->exp.exp_cap) { 163 continue; 164 } 165 166 if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { 167 return d; 168 } 169 } 170 171 return NULL; 172 } 173 174 int pcie_count_ds_ports(PCIBus *bus) 175 { 176 int dsp_count = 0; 177 int devfn; 178 179 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { 180 PCIDevice *d = bus->devices[devfn]; 181 182 if (!d || !pci_is_express(d) || !d->exp.exp_cap) { 183 continue; 184 } 185 if (object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { 186 dsp_count++; 187 } 188 } 189 return dsp_count; 190 } 191 192 static bool pcie_slot_is_hotpluggbale_bus(HotplugHandler *plug_handler, 193 BusState *bus) 194 { 195 PCIESlot *s = PCIE_SLOT(bus->parent); 196 return s->hotplug; 197 } 198 199 static const TypeInfo pcie_port_type_info = { 200 .name = TYPE_PCIE_PORT, 201 .parent = TYPE_PCI_BRIDGE, 202 .instance_size = sizeof(PCIEPort), 203 .abstract = true, 204 .class_init = pcie_port_class_init, 205 }; 206 207 static Property pcie_slot_props[] = { 208 DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), 209 DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), 210 DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true), 211 DEFINE_PROP_BOOL("x-do-not-expose-native-hotplug-cap", PCIESlot, 212 hide_native_hotplug_cap, false), 213 DEFINE_PROP_END_OF_LIST() 214 }; 215 216 static void pcie_slot_class_init(ObjectClass *oc, void *data) 217 { 218 DeviceClass *dc = DEVICE_CLASS(oc); 219 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 220 221 device_class_set_props(dc, pcie_slot_props); 222 hc->pre_plug = pcie_cap_slot_pre_plug_cb; 223 hc->plug = pcie_cap_slot_plug_cb; 224 hc->unplug = pcie_cap_slot_unplug_cb; 225 hc->unplug_request = pcie_cap_slot_unplug_request_cb; 226 hc->is_hotpluggable_bus = pcie_slot_is_hotpluggbale_bus; 227 } 228 229 static const TypeInfo pcie_slot_type_info = { 230 .name = TYPE_PCIE_SLOT, 231 .parent = TYPE_PCIE_PORT, 232 .instance_size = sizeof(PCIESlot), 233 .abstract = true, 234 .class_init = pcie_slot_class_init, 235 .interfaces = (InterfaceInfo[]) { 236 { TYPE_HOTPLUG_HANDLER }, 237 { } 238 } 239 }; 240 241 static void pcie_port_register_types(void) 242 { 243 type_register_static(&pcie_port_type_info); 244 type_register_static(&pcie_slot_type_info); 245 } 246 247 type_init(pcie_port_register_types) 248